JPH0680828B2 - Thin film transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a polysilicon thin film transistor suitable for improving off characteristics.

BACKGROUND OF THE INVENTION Conventional polysilicon thin film transistors have poor off characteristics and are difficult to apply to image displays and the like. As an improvement on such a problem, Japanese Patent Laid-Open No. 171860/1983 has been proposed.
A plurality of thin film transistors are connected in series as disclosed in Japanese Unexamined Patent Application Publication No. 2004-242242, and the electrodes at both ends thereof are used as a source electrode and a drain electrode, and the gate electrodes of the plurality of thin film transistors are all connected in common, thereby A thin film transistor has been proposed in which the electric field concentration applied to each PN junction is weakened to reduce the junction leakage current, that is, the off current.

This type of thin film transistor has a structure as shown in FIG. 3, where FIG. 3A is a plan view and FIG. 3B is 3B-3 of FIG.
It is the B sectional view. In the figure, 1 is a gate wiring having two gate electrodes 1a and 1b, 2 is a signal wiring, 3 is a polysilicon wiring as a semiconductor film, 4 is a pixel electrode, 5 is a passivation film, 6 is a gate insulating film, 7
Is a glass substrate, and a transistor is formed in a region where the gate wiring 1 and the polysilicon wiring 3 are arranged in parallel. Reference numeral 8 is a source region, 9 is an impurity region, and 10 is a drain region.

However, in the thin film transistor having the two gate electrodes 1a and 1b as described above, the voltage between the source and the drain can be applied only about 5V at most, while the gate voltage is about 5V.
It will not turn on unless a high voltage of about 20 V or higher is applied. For this reason, it is necessary to further increase the number of gate electrodes, but the thin film transistor having the above-described configuration requires a large area, and when applied to a switching element of an image display, for example, there is a problem that the aperture ratio of the pixel is lowered. Atsuta In addition, when applied to a scanner which is a peripheral circuit, there is a problem that integration is reduced.

Other prior arts include JP-A-56-26468 and JP-A-
Although there are 59-224822 and JP-A-61-292683, there is no description of a structure in which a single gate electrode and a semiconductor layer are crossed at a plurality of points by bending the semiconductor layer.

[Object of the Invention]

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a polysilicon thin film transistor capable of improving the aperture ratio of a pixel electrode.

Another object of the present invention is to provide a polysilicon thin film transistor that can eliminate the imbalance between the source-drain voltage and the gate voltage and enable integration.

[Outline of Invention]

According to an embodiment of the present invention, a polysilicon thin film transistor is formed by intersecting a polysilicon film with a gate wiring a plurality of times to form a polysilicon thin film transistor, thereby reducing a transistor formation region and improving an aperture ratio of a pixel electrode. Will be provided.

Example of Invention

 Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view of an essential part showing an embodiment of a polysilicon thin film transistor according to the present invention, and the same parts as those in the above-mentioned drawings are designated by the same reference numerals. In the figure, gate wiring 1
In the lower layer, a polysilicon wiring 3'is bent in a meandering manner four times, and is formed so as to intersect through a gate insulating film (not shown). The gate wiring 1 intersects the meandering polysilicon wiring 3 '. Gate electrodes 1c, 1d, 1e, 1
While f is formed, four channels are formed in the polysilicon wiring 3 '.

The polysilicon thin film transistor thus configured is formed as follows. That is, FIG. 3 (B)
In the following description, a polysilicon film is formed on the glass substrate 7 by the LPCVD method, and then, as shown in FIG. 1, etching is performed in a meandering shape to form a meandering polysilicon wiring 3 '. After that, the gate electrodes 1c, 1d, 1e, 1f and the gate wiring 1 are formed on the gate insulating film 6 formed by thermal oxidation, insulated by the passivation film 5, and then a through hole is formed in the contact portion to form a signal. The wiring 2 and the pixel electrode 4 are formed and completed.

According to this structure, the polysilicon wiring 3 ′ intersects the gate wiring 1 a plurality of times and meanders, so that the thin film transistors can be formed only in the peripheral portion of the gate wiring 1. Further, since the gate wiring 1 and the polysilicon wiring 3'are crossed a plurality of times, the number of channels can be easily made plural at the crossing portions.
The integration degree of the thin film transistor can be improved.

FIG. 2 is a plan view of an essential part showing another embodiment of the polysilicon thin film transistor according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, the point different from FIG. 1 is that the gate wiring 1'is formed with a large pattern width only at the portion intersecting with the polysilicon wiring 3 '.

Even in such a configuration, the same effect as described above can be obtained and the specific resistance of the thin film transistor can be increased, so that the surface leak current can be reduced.

〔The invention's effect〕

As described above, according to the present invention, since the polysilicon film as the semiconductor film and the gate wiring are crossed a plurality of times, the thin film transistor can be formed by concentrating only on the peripheral portion of the gate wiring. The aperture ratio of the pixel electrode connected to the drain electrode can be remarkably improved, and extremely excellent effects such as integration can be realized very easily can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view of an essential part showing an embodiment of a polysilicon thin film transistor according to the present invention, FIG. 2 is a plan view showing another embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are conventional drawings. It is a figure explaining a structure. 1 ... Gate wiring, 1c, 1d, 1e, 1f ... Gate electrode, 2 ...
... signal wiring, 3 '... polysilicon wiring, 4 ... pixel electrode, 5 ... passivation film, 6 ... gate insulating film,
7 ... Glass substrate, 8 ... Source region, 9 ... Impurity region, 10 ... Drain region.

Front page continued (72) Inventor Kenkichi Suzuki 3300, Hayano, Mobara-shi, Chiba, Hitachi, Ltd. Mobara factory (72) Inventor Kazuo Shirahashi 3300, Hayano, Mobara, Chiba, Hitachi, Ltd. Mobara, Hitachi, Ltd.

Claims (2)

[Claims] 1. A substrate, a semiconductor layer, a gate insulating film, a gate electrode, a gate wiring, a source electrode, and a drain electrode, and the semiconductor layer is provided between the substrate and the gate electrode. A thin film transistor having a structure in which one gate electrode and the semiconductor layer intersect at a plurality of points by bending the semiconductor layer. 2. The thin film transistor according to claim 1, wherein the gate electrode has a width larger than that of the gate wiring.