JP3535307B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3535307B2 JP3535307B2 JP08753196A JP8753196A JP3535307B2 JP 3535307 B2 JP3535307 B2 JP 3535307B2 JP 08753196 A JP08753196 A JP 08753196A JP 8753196 A JP8753196 A JP 8753196A JP 3535307 B2 JP3535307 B2 JP 3535307B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- thin film
- source region
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 125
- 239000010409 thin film Substances 0.000 claims description 80
- 239000010408 film Substances 0.000 claims description 42
- 239000012212 insulator Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims 6
- 239000000969 carrier Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000007687 exposure technique Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁表面上に形成され
た非単結晶半導体を用いた薄膜集積回路およびそれに用
いる回路素子、例えば、薄膜トランジスタ（ＴＦＴ）の
構造に関するものである。本発明において絶縁表面と
は、絶縁体表面以外に、半導体や金属の表面に設けられ
た絶縁層をも意味する。すなわち、本発明によって作製
される集積回路および薄膜トランジスタは、ガラス等の
絶縁基板上に形成されたものだけでなく、単結晶シリコ
ン等の半導体基板上に形成された絶縁体の上に形成され
たものも含む。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film integrated circuit using a non-single crystal semiconductor formed on an insulating surface and a circuit element used for the thin film integrated circuit, for example, a thin film transistor (TFT) structure. In the present invention, the insulating surface means an insulating layer provided on the surface of a semiconductor or a metal, in addition to the surface of an insulator. That is, the integrated circuit and the thin film transistor manufactured by the present invention are not only those formed on an insulating substrate such as glass, but also those formed on an insulator formed on a semiconductor substrate such as single crystal silicon. Also includes.
【０００２】[0002]
【従来の技術】ＴＦＴのごとき薄膜半導体装置は、絶縁
表面上に実質的に真性な薄膜半導体領域（活性層）を島
状に形成した後、ゲイト絶縁膜として、ＣＶＤ法やスパ
ッタ法によって絶縁被膜を形成し、その上にゲイト電極
を形成して得られる。逆に、ゲイト電極を先に形成し、
その上にゲイト絶縁膜と活性層を形成する場合もある。
前者の場合においては、ソース領域／ドレイン領域は、
真性な薄膜半導体においてＮ型もしくはＰ型の不純物を
拡散（ドープ）せしめて形成される。後者の方法におい
ても不純物拡散の方法が用いられることもあるが、別に
Ｎ型もしくはＰ型の半導体被膜を形成する方法が一般的
である。2. Description of the Related Art In a thin film semiconductor device such as a TFT, a substantially intrinsic thin film semiconductor region (active layer) is formed like an island on an insulating surface and then used as a gate insulating film by an insulating film by a CVD method or a sputtering method. Is formed and a gate electrode is formed on it. Conversely, the gate electrode is formed first,
A gate insulating film and an active layer may be formed on it.
In the former case, the source / drain regions are
It is formed by diffusing (doping) N-type or P-type impurities in an intrinsic thin film semiconductor. In the latter method, an impurity diffusion method may be used, but a method of separately forming an N-type or P-type semiconductor film is generally used.
【０００３】従来のＴＦＴは、Ｎ型もしくはＰ型のソー
ス領域／ドレイン領域と実質的に真性導電型のチャネル
領域と、チャネル領域の上にゲイト絶縁膜とゲイト電極
とを有し、ソース領域とドレイン領域には、外部との電
気的な接続を取るために、配線・電極（それぞれ、ソー
ス電極・配線、ドレイン電極・配線と称する）が接続さ
れ、これらとゲイト電極の３端子によって制御されるも
のである。A conventional TFT has an N-type or P-type source region / drain region, a channel region of substantially intrinsic conductivity type, a gate insulating film and a gate electrode on the channel region, and has a source region. Wirings / electrodes (referred to as a source electrode / wiring and a drain electrode / wiring, respectively) are connected to the drain region in order to establish an electrical connection with the outside, and these are controlled by three terminals of these and a gate electrode. It is a thing.
【０００４】特に回路によっては、ソース領域とドレイ
ン領域の区別は明確でないので、以下の記述では、ソー
ス領域、ドレイン領域とは、回路に基づく区別ではな
く、任意に設定できるものとする。すなわち、任意にソ
ース領域と設定された領域でない、端子の接続されるＮ
型もしくはＰ型の領域が、ドレイン領域と定義される。
近年、ＴＦＴの電界移動度を高める必要から、活性層の
半導体として、アモルファス半導体に代えて、結晶性半
導体を用いることが試みられている。In particular, the distinction between the source region and the drain region is not clear depending on the circuit. Therefore, in the following description, the source region and the drain region are not distinguished based on the circuit, but can be set arbitrarily. That is, the N to which the terminal is connected, which is not a region arbitrarily set as the source region
The region of p-type or p-type is defined as the drain region.
In recent years, it has been attempted to use a crystalline semiconductor instead of an amorphous semiconductor as a semiconductor of an active layer because it is necessary to increase the electric field mobility of a TFT.
【０００５】[0005]
【発明が解決しようする課題】このような非単結晶の半
導体、中でも結晶性の非単結晶半導体（例えば、多結晶
シリコン）を用いたＴＦＴにおける最大の問題点はリー
ク電流（ＯＦＦ電流）が大きいことであった。すなわ
ち、ゲイト電極に電圧が印加されていない、もしくは逆
の電圧が印加されている際（非選択状態、ＯＦＦ状態）
には、チャネル（電流通路）が形成されないので、電流
は流れないはずである。しかしながら、実際には、単結
晶半導体において通常、観察されるリーク電流以上の電
流が見られた。したがって、この現象は非単結晶半導体
に特有のものと考えられる。The biggest problem with a TFT using such a non-single-crystal semiconductor, especially a crystalline non-single-crystal semiconductor (for example, polycrystalline silicon), is a large leak current (OFF current). Was that. That is, when no voltage is applied to the gate electrode or when a reverse voltage is applied (non-selected state, OFF state)
Since no channel (current path) is formed in, no current should flow. However, in reality, a current higher than the leakage current normally observed in a single crystal semiconductor was observed. Therefore, this phenomenon is considered to be peculiar to non-single crystal semiconductors.
【０００６】このような大きなリーク電流は、特にダイ
ナミックな動作（電荷保持等）の要求される用途におい
て問題であった。また、スタティックな動作の要求され
る用途においても、消費電力を増加させるため、好まし
いことではなかった。ＴＦＴの大きな用途として期待さ
れている液晶ディスプレー等のアクティブマトリクス回
路においては、ＴＦＴはマトリクスに設けられた画素の
スイッチングトランジスタとして動作するが、その際に
は、画素電極やその補助のコンデンサー（保持容量）に
蓄積された電荷がリークしないことが必要とされたが、
リーク電流が大きいと十分な時間、電荷を保持すること
ができなかった。Such a large leak current has been a problem particularly in applications requiring dynamic operation (charge retention, etc.). Further, it is not preferable because it increases power consumption even in applications requiring static operation. In an active matrix circuit such as a liquid crystal display, which is expected to have a large use as a TFT, the TFT operates as a switching transistor of a pixel provided in the matrix. At that time, the pixel electrode and its auxiliary capacitor (holding capacity) ) Was required to not leak the charge accumulated in
If the leak current was large, the electric charge could not be retained for a sufficient time.
【０００７】従来、リーク電流が低減するには、チャネ
ル長を長くするか、または、チャネル幅を小さくするこ
とが有効であると考えられていた。しかし、こうする
と、リーク電流の絶対値は小さくなるものの、ゲイト電
極に電圧が印加されている際（選択状態、ＯＮ状態）の
ドレイン電流（ＯＮ電流）も同様に小さくなり、必要と
する動作がおこなえない場合があった。すなわち、この
方法ではドレイン電流とリーク電流の比率（ＯＮ／ＯＦ
Ｆ比）を向上させることはできなかった。本発明は、こ
のような問題を鑑みてなされたものであり、非単結晶半
導体を活性層に用いたＴＦＴにおいて、リーク電流を低
減するとともに、ＯＮ／ＯＦＦ比を改善する方法を提供
することを目的とする。Conventionally, it has been considered effective to reduce the leak current by increasing the channel length or reducing the channel width. However, in this way, although the absolute value of the leak current becomes small, the drain current (ON current) when a voltage is applied to the gate electrode (selected state, ON state) also becomes small, and the required operation is performed. There were cases where it could not be done. That is, in this method, the ratio of the drain current to the leakage current (ON / OF
The F ratio) could not be improved. The present invention has been made in view of such a problem, and provides a method of reducing a leak current and improving an ON / OFF ratio in a TFT using a non-single crystal semiconductor in an active layer. To aim.
【０００８】[0008]
【課題を解決するための手段】本発明は、薄膜半導体
と、ゲイト絶縁膜、ゲイト電極を有する薄膜半導体装置
に関する。本発明では、従来のＴＦＴに加えて、さらに
別のゲイト電極とゲイト絶縁膜を設ける。すなわち、第
１のゲイト電極（従来のゲイト電極と同等なもの）およ
び第２のゲイト電極（本発明において追加するもの）を
形成し、それぞれのゲイト電極に対応するゲイト絶縁膜
も設ける。本発明のもととなる薄膜半導体装置において
は、前記薄膜半導体は島状に形成され、かつ、同一面内
もしくは異なる面内にソース領域、ドレイン領域を有す
る。The present invention relates to a thin film semiconductor device having a thin film semiconductor, a gate insulating film, and a gate electrode. In the present invention, in addition to the conventional TFT, another gate electrode and a gate insulating film are further provided. That is, a first gate electrode (equivalent to a conventional gate electrode) and a second gate electrode (addition in the present invention) are formed, and a gate insulating film corresponding to each gate electrode is also provided. In the thin film semiconductor device on which the present invention is based, the thin film semiconductor is formed in an island shape and has a source region and a drain region in the same plane or in different planes.
【０００９】本発明においては、第２のゲイト電極をソ
ース領域、ドレイン領域とは重ならないように設け、さ
らに、第１のゲイト電極に逆バイアスの電圧が印加され
ている際には、第２のゲイト電極には、順バイアスの電
圧が印加されていることを特徴とする。本発明の第１
は、上記の条件を満たす薄膜半導体装置において、第１
のゲイト電極と第２のゲイト電極を、薄膜半導体をはさ
むように設けることを特徴とする。In the present invention, the second gate electrode is provided so as not to overlap the source region and the drain region, and further, when the reverse bias voltage is applied to the first gate electrode, the second gate electrode is provided. Is characterized in that a forward bias voltage is applied to the gate electrode. First of the present invention
In the thin film semiconductor device satisfying the above conditions,
The gate electrode and the second gate electrode are provided so as to sandwich the thin film semiconductor.
【００１０】また、薄膜半導体は主たる面（主面）が２
つ存在することに着目した場合には、第１のゲイト電極
を第１のゲイト絶縁膜を挟んで前記薄膜半導体の第１の
主面に設け、第２のゲイト電極を第２のゲイト絶縁膜を
挟んで設けることを特徴とする本発明の第２が得られ
る。本発明においては、作製工程を簡略化する意味で、
第２のゲイト電極を、ソース領域もしくはドレイン領域
のいずれか少なくとも一方と接続する配線と同じ被膜か
ら形成してもよい。Further, the main surface (main surface) of the thin film semiconductor is 2
When it is noted that there is one, the first gate electrode is provided on the first main surface of the thin film semiconductor with the first gate insulating film sandwiched therebetween, and the second gate electrode is provided with the second gate insulating film. According to the second aspect of the present invention, which is characterized in that it is provided by sandwiching. In the present invention, to simplify the manufacturing process,
The second gate electrode may be formed from the same film as the wiring that is connected to at least one of the source region and the drain region.
【００１１】また、いわゆるトップゲイト型ＴＦＴ（基
板と薄膜半導体と第１のゲイト電極の位置関係におい
て、薄膜半導体が基板と第１のゲイト電極の間に存在す
る）に本発明を適用してもよいのと同様、ボトムゲイト
型ＴＦＴ（上記位置関係において、第１のゲイト電極が
基板と薄膜半導体の間に存在する）に本発明を適用して
もよい。Also, the present invention is applied to a so-called top gate type TFT (the thin film semiconductor is present between the substrate and the first gate electrode in the positional relationship between the substrate, the thin film semiconductor and the first gate electrode). Similarly, the present invention may be applied to a bottom gate type TFT (the first gate electrode is present between the substrate and the thin film semiconductor in the above positional relationship).
【００１２】本発明の基本的な構成を図１に示す。図１
はボトムゲイト型の例である。図１（Ａ）には、その断
面図を示す。すなわち、基板１上に第１のゲイト電極
２、第１のゲイト絶縁膜３、薄膜半導体４、その両端に
ソース領域５、ドレイン領域６、第２のゲイト絶縁膜
７、第２のゲイト電極８ａ〜８ｃを有する。必要によっ
ては、ソース電極・配線９、ドレイン電極・配線１０を
設けてもよい。（図１（Ａ））
図１（Ａ）では、第２のゲイト電極の配置が不明瞭であ
るので、図１（Ｂ）に積層構造を示す。（図１（Ｂ））The basic configuration of the present invention is shown in FIG. Figure 1
Is an example of bottom gate type. The cross-sectional view is shown in FIG. That is, the first gate electrode 2, the first gate insulating film 3, and the thin film semiconductor 4 are provided on the substrate 1, and the source region 5, the drain region 6, the second gate insulating film 7, and the second gate electrode 8a are provided on both ends thereof. ~ 8c. If necessary, the source electrode / wiring 9 and the drain electrode / wiring 10 may be provided. (FIG. 1A) Since the arrangement of the second gate electrode is not clear in FIG. 1A, a laminated structure is shown in FIG. 1B. (Fig. 1 (B))
【００１３】さらに、上方より見た様子を図１（Ｃ）に
示す。本発明においては、第２のゲイト電極のうち少な
くとも１つは、電気的にソース領域およびドレイン領域
のいずれとも重ならないことが必要である。ここで、
「電気的」という語句の意味は、第２のゲイト電極によ
る電気的な影響を意味し、仮に、幾何学的には、ソース
領域やドレイン領域と重なっていても、第２のゲイト電
極の電気的な作用がその重なり部分に及ばない場合は、
「電気的に」重ならない、と表現する。（図１（Ｃ））Further, FIG. 1C shows a state viewed from above. In the present invention, it is necessary that at least one of the second gate electrodes does not electrically overlap with either the source region or the drain region. here,
The term “electrical” means the electrical influence of the second gate electrode, and even if it is geometrically overlapping with the source region and the drain region, the electrical property of the second gate electrode is not affected. If the dynamic effect does not extend to the overlap,
We say that they do not "electrically" overlap. (Fig. 1 (C))
【００１４】本発明では、図１（Ｃ）のように第２のゲ
イト電極が交互に設けるだけではなく、図１（Ｄ）のよ
うに、第２のゲイト電極８ａと８ｂを同じように設けて
もよい。（図１（Ｄ））
本発明において、薄膜半導体において、第２のゲイト電
極と重ならない部分（第２のゲイト電極による電気的な
作用の及ばない部分）をベース領域と定義した場合、下
記の条件を満足するように、第２のゲイト電極を配置す
ると、より本発明の効果が明確となる。In the present invention, not only the second gate electrodes are alternately provided as shown in FIG. 1C, but also the second gate electrodes 8a and 8b are provided in the same manner as shown in FIG. 1D. May be. (FIG. 1D) In the present invention, in the thin film semiconductor, when a portion which does not overlap with the second gate electrode (a portion which is not electrically operated by the second gate electrode) is defined as a base region, When the second gate electrode is arranged so as to satisfy the conditions, the effect of the present invention becomes clearer.
【００１５】すなわち、本発明の第３は以下の条件を満
足する。「ベース領域のみを経由してソース領域からド
レイン領域へ至る最短距離は、薄膜半導体を経由してソ
ース領域からドレイン領域へ至る最短距離よりも大き
い。」
本発明の第４は以下の条件を満足する。「ベース領域の
面積をベース領域のみを経由してソース領域からドレイ
ン領域へ至る最短経路長により除した値（ベース領域の
平均的な幅）は、薄膜半導体のソース領域とドレイン領
域以外の面積をソース領域からドレイン領域へ至る最短
経路長により除した値（薄膜半導体の幅）よりも小さ
い。」That is, the third aspect of the present invention satisfies the following condition. “The shortest distance from the source region to the drain region via only the base region is larger than the shortest distance from the source region to the drain region via the thin film semiconductor.” The fourth aspect of the present invention satisfies the following condition. To do. "The value obtained by dividing the area of the base region by the shortest path length from the source region to the drain region via only the base region (average width of the base region) is the area of the thin film semiconductor other than the source region and the drain region. It is smaller than the value (width of thin film semiconductor) divided by the shortest path length from the source region to the drain region. "
【００１６】なお、上記のベース領域の定義において
は、第２のゲイト電極の形状そのものは問題ではなく、
電気的な作用が重視されるということに注意すべきであ
る。さらに、本発明においては、後述するように選択、
非選択に関しては、ベース領域のみを電気的に制御でき
ればよいので、第１のゲイト電極は、ベース領域以外の
部分（すなわち、第２のゲイト電極と薄膜半導体の重な
る部分）には存在する必要はない。したがって、下記の
条件を本発明の第３および第４に付加してもよい。「ベ
ース領域は、第１のゲイト電極の形状とが、実質的に同
じである。In the above definition of the base region, the shape of the second gate electrode itself does not matter.
It should be noted that the electrical action is important. Further, in the present invention, as described later, selection,
Regarding the non-selection, only the base region needs to be electrically controlled, and therefore the first gate electrode does not need to be present in a portion other than the base region (that is, a portion where the second gate electrode and the thin film semiconductor overlap). Absent. Therefore, the following conditions may be added to the third and fourth aspects of the present invention. "The base region has substantially the same shape as the first gate electrode.
【００１７】このように、ベース領域と第１のゲイト電
極の形状をほぼ同じとするには、第１のゲイト電極をマ
スクとした自己整合的なフォトリソグラフィー技術によ
って、第２のゲイト電極をパターンを形成すればよい。
このような条件を本発明の第３乃至第６に付加してもよ
い。As described above, in order to make the shape of the base region and that of the first gate electrode substantially the same, the second gate electrode is patterned by the self-aligned photolithography technique using the first gate electrode as a mask. Should be formed.
Such conditions may be added to the third to sixth aspects of the present invention.
【００１８】[0018]
【作用】本発明においては、選択（ＯＮ）状態について
は、従来のＴＦＴと何ら変わることがない。本発明にお
いて特徴となるのは、非選択（ＯＦＦ）状態についてで
ある。図１に示す半導体装置において、第２のゲイト電
極の電位をソース領域と同じとする。一方、第１のゲイ
ト電極においては、比較的大きな逆バイアス電圧を印加
する。Ｎチャネル型半導体装置においては、選択状態
（第１のゲイト電極に順バイアス電圧（すなわち、正電
圧）が印加されている状態）では、図６（Ｂ）に示すよ
うに第１のゲイト電極に面した薄膜半導体に多数キャリ
ヤ（すなわち、電子）が引き寄せられ、これがキャリヤ
となってソース−ドレイン間の導電を担う。（図６
（Ｂ））In the present invention, the selected (ON) state is no different from the conventional TFT. The feature of the present invention is the non-selected (OFF) state. In the semiconductor device shown in FIG. 1, the potential of the second gate electrode is the same as that of the source region. On the other hand, a relatively large reverse bias voltage is applied to the first gate electrode. In the N-channel semiconductor device, in the selected state (the state in which the forward bias voltage (that is, the positive voltage) is applied to the first gate electrode), the first gate electrode is applied to the first gate electrode as shown in FIG. 6B. Majority carriers (that is, electrons) are attracted to the facing thin film semiconductor, and these carriers serve as carriers for conducting the source-drain. (Fig. 6
(B))
【００１９】一方、非選択状態（第１のゲイト電極に逆
バイアス電圧（すなわち、負電圧）が印加されている状
態）では、図６（Ａ）に示すように第１のゲイト電極に
面した薄膜半導体に少数キャリヤ（すなわち、正孔）が
引き寄せられ、これがキャリヤとなる。（図６（Ａ））On the other hand, in the non-selected state (the state in which the reverse bias voltage (ie, negative voltage) is applied to the first gate electrode), the first gate electrode is faced as shown in FIG. 6 (A). Minority carriers (that is, holes) are attracted to the thin film semiconductor and serve as carriers. (Fig. 6 (A))
【００２０】図２（Ａ）のｘ−ｘ’に沿った薄膜半導体
のエネルギーバンドを図４（Ａ）および（Ｂ）に示す。
ＥF はフェルミ準位を意味する。図４（Ａ）は第１のゲ
イト電極の電圧をソース領域の電圧を同じとした状態
（ＶG1＝０）であり、図４（Ｂ）は第１のゲイト電極に
ある大きさの負の電圧（−Ｖ）を印加した状態（ＶG1＝
−Ｖ）を示す。なお、ＶG2は第２のゲイト電極に印加さ
れる電圧の大きさを表す。（図４（Ａ）、（Ｂ））
ソース領域と薄膜半導体、ドレイン領域と薄膜半導体の
間にはギャップが存在し、少数キャリヤである正孔はこ
のギャップを移動できないために、理想的にはソース−
ドレイン間の導電はない。The energy band of the thin film semiconductor along xx 'of FIG. 2A is shown in FIGS. 4A and 4B.
E F means Fermi level. FIG. 4A shows a state in which the voltage of the first gate electrode is the same as the voltage of the source region (V G1 = 0), and FIG. 4B shows a negative voltage of a certain magnitude in the first gate electrode. Voltage (-V) applied (V G1 =
-V) is shown. Note that V G2 represents the magnitude of the voltage applied to the second gate electrode. (FIGS. 4A and 4B) Since there are gaps between the source region and the thin film semiconductor, and between the drain region and the thin film semiconductor, holes which are minority carriers cannot move in this gap, so ideally Source-
There is no conduction between drains.
【００２１】しかしながら、非単結晶半導体において
は、結晶欠陥等に由来する局在準位をホッピングして導
電することが知られており、薄膜半導体表面に誘起され
た正孔も、このメカニズムによってソース領域、ドレイ
ン領域から移動する電子と再結合し、結果として、ソー
ス−ドレイン間の導電（リーク電流）が生じる。図４の
点線の矢印はホッピング伝導を示す。もちろん、ホッピ
ングとは言え、かなりの大きさの抵抗となる。第１のゲ
イト電極に印加される逆バイアス電圧がより大きくなれ
ば、より多くの少数キャリヤ（正孔）が誘起されるの
で、より導電率が高まり、リーク電流が増大することと
なる。However, in non-single-crystal semiconductors, it is known that the localized levels derived from crystal defects and the like are hopped to conduct electricity, and the holes induced on the surface of the thin film semiconductor are also sourced by this mechanism. The electrons are recombined with the electrons moving from the region and the drain region, and as a result, conduction (leakage current) between the source and the drain is generated. The dotted arrow in FIG. 4 indicates hopping conduction. Of course, it is a hopping, but it is a considerable resistance. If the reverse bias voltage applied to the first gate electrode becomes larger, more minority carriers (holes) are induced, so that the conductivity is further increased and the leak current is increased.
【００２２】図２（Ａ）は従来のＴＦＴの非選択状態の
リーク電流の流れを示したものであり、薄膜半導体の全
体を横断して電流が流れる。（図２（Ａ））
次に、第２のゲイト電極にある大きさの正の電圧（＋
ｖ）を印加した状態（ＶG2＝＋Ｖ）を考える。すると、
第２のゲイト電極に面した薄膜半導体の表面には多数キ
ャリヤ（電子）が誘起され、エネルギーバンド図は、図
４（Ｃ）のように複雑な形状となる。（図４（Ｃ））FIG. 2A shows the flow of the leak current in the non-selected state of the conventional TFT, in which the current flows across the entire thin film semiconductor. (FIG. 2 (A)) Next, a positive voltage of a certain magnitude (+
Consider the state (V G2 = + V) to which v) is applied. Then,
Majority carriers (electrons) are induced on the surface of the thin film semiconductor facing the second gate electrode, and the energy band diagram has a complicated shape as shown in FIG. (Fig. 4 (C))
【００２３】図４（Ｂ）および（Ｃ）に示されるエネル
ギーバンド図をもとに、薄膜半導体を電気回路的に表示
すると、図５のようになる。図５（Ａ）は、ソース領域
と薄膜半導体との接合部の抵抗Ｒ1 、ドレイン領域と薄
膜半導体との接合部の抵抗Ｒ2 以外に薄膜半導体自身の
抵抗Ｒ3 の直列抵抗である。しかし、Ｒ3 は第１のゲイ
ト電圧に印加される逆バイアス電圧によって、決定さ
れ、逆バイアス電圧が大きくなればなるほど、多くの少
数キャリヤが誘起され、Ｒ3 は減少し、Ｒ1 、Ｒ2 に比
較して無視しうるほど小さくなり、実質的には、Ｒ1 と
Ｒ2 によって、リーク電流が決定される。（図５
（Ａ））FIG. 5 shows the electric circuit of the thin film semiconductor based on the energy band diagrams shown in FIGS. 4 (B) and 4 (C). FIG. 5A shows the series resistance of the resistance R 1 of the junction between the source region and the thin film semiconductor, the resistance R 2 of the junction between the drain region and the thin film semiconductor, and the resistance R 3 of the thin film semiconductor itself. However, R 3 is determined by the reverse bias voltage applied to the first gate voltage, and as the reverse bias voltage increases, more minority carriers are induced, and R 3 decreases, and R 1 and R 2 decrease. Is negligibly small compared to the above, and R 1 and R 2 substantially determine the leak current. (Fig. 5
(A))
【００２４】しかしながら、第２のゲイト電極に順バイ
アス電圧を印加すると、接合が増える分、直列に挿入さ
れる抵抗も増える。すなわち、第２のゲイト電極１つに
つき、２つの接合による抵抗が生じる。図５（Ｂ）で
は、この２つの抵抗を１つのものとして、Ｒ4 〜Ｒ6 と
表現する。すなわち、第２のゲイト電極は３つあるの
で、抵抗も３つ生じる。これ以外にも薄膜半導体固有の
抵抗があるのだが、ここでは表示していない。（図５
（Ｂ））However, if a forward bias voltage is applied to the second gate electrode, the number of junctions increases and the resistance inserted in series also increases. That is, the resistance due to the two junctions is generated for each second gate electrode. In FIG. 5B, these two resistors are regarded as one and are expressed as R 4 to R 6 . That is, since there are three second gate electrodes, three resistances also occur. There are other resistances specific to thin film semiconductors, but they are not shown here. (Fig. 5
(B))
【００２５】図２（Ｂ）には、同じ状態を上方より見た
様子を示す。第２のゲイト電極の存在する部分には反転
層１１が生じ、それ以外の部分がベース領域１２とな
る。リーク電流の経路としてはｘ−ｘ’の線に沿ったも
の以外に、図に矢印に示すように、ベース領域に沿った
ものも生じる。ベース領域に沿った電流の抵抗をＲ7 〜
Ｒ9 とすると、図５（Ｃ）に示すような回路が得られ
る。（図５（Ｃ））FIG. 2B shows the same state viewed from above. The inversion layer 11 is formed in the portion where the second gate electrode exists, and the other portion becomes the base region 12. In addition to the path of the leakage current along the line xx ′, the path of the leakage current also occurs along the base region as shown by the arrow in the figure. The resistance of the current along the base region is R 7 ~
With R 9 , a circuit as shown in FIG. 5C is obtained. (Fig. 5 (C))
【００２６】実際には、Ｒ4 〜Ｒ6 はＲ7 〜Ｒ9 よりも
はるかに大きいので、リーク電流は主としてＲ7 〜Ｒ9
（すなわち、ベース領域）を流れ、実質的な回路図は図
５（Ｄ）で表される。（図５（Ｄ））
ここで問題となるのは、Ｒ3 と（Ｒ7 ＋Ｒ8 ＋Ｒ9 ）の
大小の比較である。図２（Ａ）と（Ｂ）の対比から明ら
かなように、Ｒ3 （薄膜半導体４）は、（Ｒ7＋Ｒ8 ＋
Ｒ9 ）（ベース領域１２）よりも幅が広く、かつ、短い
ので、前者の抵抗が後者よりも小さいことは明白であ
る。これは、本発明の第３および第４と同じである。す
なわち、第２のゲイト電極を適切に配置し、これに順バ
イアス電圧を印加することにより、非選択時の抵抗を高
め、リーク電流を低減できる。In practice, R 4 to R 6 are much larger than R 7 to R 9, so the leakage current is mainly R 7 to R 9.
(That is, the base region), and a substantial circuit diagram is shown in FIG. (FIG. 5 (D)) The problem here is the comparison between R 3 and (R 7 + R 8 + R 9 ). As is clear from the comparison between FIGS. 2A and 2B, R 3 (thin film semiconductor 4) is (R 7 + R 8 +
Since the width is wider and shorter than R 9 ) (base region 12), it is clear that the resistance of the former is smaller than that of the latter. This is the same as the third and fourth aspects of the present invention. That is, by appropriately arranging the second gate electrode and applying a forward bias voltage to the second gate electrode, the resistance in the non-selected state can be increased and the leak current can be reduced.
【００２７】同じことは図１（Ｄ）のような構造を有す
る薄膜半導体装置についても当てはまる。図から明らか
に、ベース領域の平均的な幅は、薄膜半導体自体の幅よ
り狭い。このようにして、本発明では、非選択状態のリ
ーク電流を低減させる一方で、選択状態のドレイン電流
はそのままとし、結果的にＯＮ／ＯＦＦ比を増大させる
ことが可能となる。また、このことは、本発明が、選択
状態と非選択状態で電流（それぞれ、ドレイン電流とリ
ーク電流）の経路が異なるという特徴を有することとも
同じである。The same applies to a thin film semiconductor device having a structure as shown in FIG. Obviously, the average width of the base region is narrower than that of the thin film semiconductor itself. In this way, in the present invention, it is possible to reduce the leak current in the non-selected state, while keeping the drain current in the selected state as it is, and consequently to increase the ON / OFF ratio. This is also the same as the feature of the present invention that the paths of the currents (drain current and leak current, respectively) are different between the selected state and the non-selected state.
【００２８】非選択状態におけるベース領域の長さをよ
り長くするには、第２のゲイト電極の数を２以上、好ま
しくは、３以上とするとよい。同様にベース領域の幅を
より狭くするには、第２のゲイト電極の間隔を可能な限
り狭めるとよい。また、幅（選択状態でのチャネルの
幅）が広く、かつ、長さ（ソース−ドレイン間の距離）
の短い薄膜半導体を用いると、より、ＯＮ／ＯＦＦ比を
増大せしめることができる。かくすることにより、非選
択状態における実質的なチャネル長を選択状態における
ものの５〜５０倍に、非選択状態における実質的なチャ
ネル幅を選択状態におけるものの１／２〜１／２０倍に
することも可能であり、この結果、ＯＮ／ＯＦＦ比を、
１００倍にまで拡大できる。In order to increase the length of the base region in the non-selected state, the number of second gate electrodes should be 2 or more, preferably 3 or more. Similarly, in order to make the width of the base region narrower, the interval between the second gate electrodes should be narrowed as much as possible. In addition, the width (channel width in the selected state) is wide, and the length (source-drain distance)
The ON / OFF ratio can be further increased by using a thin film semiconductor having a short length. By doing so, the substantial channel length in the non-selected state is made 5 to 50 times that in the selected state, and the substantial channel width in the non-selected state is made 1/2 to 1/20 times that in the selected state. Is also possible, and as a result, the ON / OFF ratio is
It can be expanded up to 100 times.
【００２９】[0029]
〔実施例１〕 図３および図７に本実施例の半導体装置
の断面図（図３）および上面図（図７）を示す。本実施
例では、第１のゲイト電極２を実質的にベース領域（薄
膜半導体のうち、第２のゲイト電極と重ならない部分）
と同じ形状とするものである。すなわち、第１のゲイト
電極と第２のゲイト電極の重なりを可能な限り小さくし
たものである。番号は図１のものと同じものを指す。
（図３）Example 1 FIGS. 3 and 7 are a sectional view (FIG. 3) and a top view (FIG. 7) of a semiconductor device of this example. In the present embodiment, the first gate electrode 2 is formed substantially in the base region (a portion of the thin film semiconductor which does not overlap with the second gate electrode).
It has the same shape as. That is, the overlap between the first gate electrode and the second gate electrode is made as small as possible. The numbers refer to the same as in FIG.
(Figure 3)
【００３０】本実施例では第１のゲイト電極と第２のゲ
イト電極の形状自体の重なりを小さくしたものである
が、仮に形状的には重なりが多くとも電気的に考えた場
合の重なりが小さい場合も本実施例と同じ思想である。
第１のゲイト電極２は、図３では複数あるように見える
が、図７（Ａ）に示すようにひとつの連続したものであ
る。図７（Ｂ）は、第１のゲイト電極２に、薄膜半導体
４、ソース領域５、ドレイン領域６、第２のゲイト電極
８ａ〜８ｃを重ねたものである。（図７）In the present embodiment, the overlap between the shapes of the first gate electrode and the second gate electrode itself is made small. However, if there is a large overlap in shape, the overlap is small when considered electrically. Also in the case, the idea is the same as that of this embodiment.
Although the first gate electrode 2 appears to be plural in FIG. 3, it is one continuous electrode as shown in FIG. 7 (A). In FIG. 7B, the thin film semiconductor 4, the source region 5, the drain region 6, and the second gate electrodes 8a to 8c are superposed on the first gate electrode 2. (Figure 7)
【００３１】このような構造の半導体装置では、非選択
状態では、図１の半導体装置と同じ動作である。すなわ
ち、非選択状態であるので、第１のゲイト電極には逆バ
イアス電圧が印加され、第２のゲイト電極には、順バイ
アス電圧が印加される。そして、少数キャリヤは、図２
に示したものと同じように、ベース領域を迂回して流れ
る。The semiconductor device having such a structure operates in the same manner as the semiconductor device of FIG. 1 in the non-selected state. That is, since it is in the non-selected state, a reverse bias voltage is applied to the first gate electrode and a forward bias voltage is applied to the second gate electrode. And the minority carrier is shown in FIG.
Flows around the base region, similar to that shown in.
【００３２】しかながら、第２のゲイト電極８ａ〜８ｃ
にソース領域と同じ電圧を印加しても、同様な効果が得
られる。この場合には、バンドギャップに由来する図５
の抵抗Ｒ4 〜Ｒ6 は小さくなるが、第２のゲイト電極８
ａ〜８ｃによって誘起されるキャリヤはほとんどないの
で、この部分の抵抗は極めて高い。したがって、第２の
ゲイト電極８ａ〜８ｃにソース領域と同じ電圧を印加し
ても、ほとんどのリーク電流はベース領域を流れる。す
なわち、本実施例での半導体装置では、非選択状態にお
いては、第２のゲイト電極に印加される電圧は逆バイア
スの電圧以外の電圧であり、第２のゲイト電極によっ
て、少数キャリヤが誘起されない電圧であればよい。However, the second gate electrodes 8a to 8c
Even if the same voltage is applied to the source region, the same effect can be obtained. In this case, FIG.
Resistances R 4 to R 6 of the second gate electrode 8 are reduced.
Since there are almost no carriers induced by a to 8c, the resistance in this part is extremely high. Therefore, even if the same voltage as the source region is applied to the second gate electrodes 8a to 8c, most of the leak current flows in the base region. That is, in the semiconductor device of this embodiment, in the non-selected state, the voltage applied to the second gate electrode is a voltage other than the reverse bias voltage, and minority carriers are not induced by the second gate electrode. Any voltage will do.
【００３３】一方、選択状態においては、図１の半導体
装置では、第２のゲイト電極に順バイアス電圧を印加し
ても、あるいはソース領域と同じ電圧を印加してもドレ
イン電流の流れには大きな変動はなかった。しかしなが
ら、本実施例の半導体装置では、第２のゲイト電極には
順バイアス電圧が印加されることが要求される。もし、
そうでなければドレイン電流は非選択状態と同じように
ベース領域を中心に流れるため、選択状態と非選択状態
によって電流の経路を変え、よって、ＯＮ／ＯＦＦ比を
向上させるという本発明の目的が達成できないからであ
る。On the other hand, in the selected state, in the semiconductor device of FIG. 1, even if a forward bias voltage is applied to the second gate electrode or the same voltage as the source region is applied, the drain current flow is large. There was no change. However, in the semiconductor device of this embodiment, it is required that a forward bias voltage be applied to the second gate electrode. if,
Otherwise, since the drain current flows around the base region as in the non-selected state, the path of the current is changed depending on the selected state and the non-selected state, and the object of the present invention is to improve the ON / OFF ratio. Because it cannot be achieved.
【００３４】上記の議論より、本実施例の半導体装置に
おいては、一番容易な駆動方法は、非選択状態、選択状
態に関わらず、常に第２のゲイト電極８ａ〜８ｃに順バ
イアス電圧を印加する方法である。しかしながら、第１
のゲイト電極の電圧に合わせて、第２のゲイト電極に印
加する電圧を変動させる方法も有効である。例えば、選
択状態では、第２のゲイト電極には第１のゲイト電極と
０．５〜２倍の電圧を印加し、非選択状態では、印加す
る電圧をソース領域と同じとする、という方法が有効で
ある。From the above discussion, in the semiconductor device of this embodiment, the easiest driving method is to always apply the forward bias voltage to the second gate electrodes 8a to 8c regardless of the non-selected state or the selected state. Is the way to do it. However, the first
It is also effective to change the voltage applied to the second gate electrode according to the voltage of the gate electrode. For example, in the selected state, a voltage of 0.5 to 2 times that of the first gate electrode is applied to the second gate electrode, and in the non-selected state, the applied voltage is the same as that of the source region. It is valid.
【００３５】〔実施例２〕 図８に本実施例の半導体装
置の作製工程を示す。本実施例の半導体装置の構造は、
実施例１のものと同様に、第１のゲイト電極とベース領
域が実質的に同じ形状となるようにしたものである。そ
のため、本実施例では、自己整合的なパターン形成法を
用いる。以下ではその概略を説明する。詳細な条件・材
料・大きさ等については、公知の方法・技術に示されて
いるものを用いればよい。Example 2 FIG. 8 shows a manufacturing process of a semiconductor device of this example. The structure of the semiconductor device of this embodiment is
Like the first embodiment, the first gate electrode and the base region have substantially the same shape. Therefore, in this embodiment, a self-aligned pattern forming method is used. The outline will be described below. Regarding detailed conditions, materials, sizes, etc., those described in known methods and techniques may be used.
【００３６】まず、ガラス等の透明な基板１０１上に不
透明な材料（例えば、タンタル、アルミニウム、モリブ
テン、タングステン、クロム等）で第１のゲイト電極１
０２を形成する。ここで、「透明」というのは、後の自
己整合的なパターン形成工程において、フォトリソグラ
フィー法で用いる光が透過するという意味である。第１
のゲイト電極１０２の形状は図７（Ａ）に示すものと同
様である。さらに、第１のゲイト絶縁膜１０３を堆積す
る。（図８（Ａ））
そして、薄膜半導体１０４と第２のゲイト絶縁膜１０７
を形成する。（図８（Ｂ））First, the first gate electrode 1 is made of an opaque material (eg, tantalum, aluminum, molybdenum, tungsten, chromium) on a transparent substrate 101 such as glass.
02 is formed. Here, “transparent” means that light used in a photolithography method is transmitted in a later self-aligned pattern forming step. First
The shape of the gate electrode 102 is the same as that shown in FIG. Further, the first gate insulating film 103 is deposited. (FIG. 8A) Then, the thin film semiconductor 104 and the second gate insulating film 107 are formed.
To form. (Fig. 8 (B))
【００３７】次に、絶縁物層を形成する。この絶縁物層
は可能な限り厚く、かつ、誘電率の小さいものが好まし
い。かくすることにより、上に導電体が存在しても、そ
の下の薄膜半導体に及ぼす電気的な影響は極めて小さく
なる。しかしながら、絶縁物層があまり厚いと装置の凹
凸を増すことになり、断線の危険が増加する。また、誘
電率も材料によって、制約される。この絶縁物層の材料
としては、第２のゲイト絶縁物と異なることが望まし
く、後の第２のゲイト絶縁膜のエッチング工程で、エッ
チングされず、マスクとして使用できるようなものが好
ましい。例えば、第２のゲイト絶縁物として窒化珪素を
用いると、本絶縁物層は酸化珪素とすると、誘電率の点
でもエッチング特性の点でも好ましい。Next, an insulating layer is formed. This insulating layer is preferably as thick as possible and has a low dielectric constant. By doing so, even if there is a conductor above, the electrical influence on the thin film semiconductor thereunder becomes extremely small. However, if the insulator layer is too thick, the unevenness of the device increases, and the risk of disconnection increases. The dielectric constant is also limited by the material. The material of this insulating layer is preferably different from that of the second gate insulating material, and it is preferable that it can be used as a mask without being etched in the subsequent step of etching the second gate insulating film. For example, when silicon nitride is used as the second gate insulator, the present insulator layer is preferably made of silicon oxide in terms of dielectric constant and etching characteristics.
【００３８】次に、公知の裏面露光技術（例えば、特開
平５−２７５４５２）を用いて、裏面より光を照射す
る。このときには、フォトレジストとして、光の照射さ
れた部分が剥離されるものを用いる。かくすると、ゲイ
ト電極１０２の上に存在するフォトレジストには光が照
射されないので、その部分のフォトレジストは残り、他
の部分は剥離される。こうして得られたフォトレジスト
のパターンを用いて、絶縁物層をエッチングし、絶縁物
パターン１１３を得る。上記の議論から明らかなよう
に、絶縁物パターンは第１のゲイト電極１０２の上にの
み形成されるので、第１のゲイト電極と同じ形状をして
いる。（図８（Ｃ））Next, light is irradiated from the back surface using a known back surface exposure technique (for example, Japanese Patent Laid-Open No. 5-275452). At this time, as the photoresist, one in which the light-irradiated portion is peeled off is used. In this case, since the photoresist existing on the gate electrode 102 is not irradiated with light, the photoresist in that portion remains and the other portions are peeled off. Using the photoresist pattern thus obtained, the insulating layer is etched to obtain an insulating pattern 113. As is clear from the above discussion, since the insulator pattern is formed only on the first gate electrode 102, it has the same shape as the first gate electrode. (Fig. 8 (C))
【００３９】その後、公知の金属被膜成膜法により、適
切な材料（例えば、アルミニウムやタンタル等）の被膜
を形成し、これを公知のフォトリソグラフィー法および
エッチング法によって、パターン形成とエッチングをお
こない、第２のゲイト電極１０８、ソース電極・配線１
０９、ドレイン電極・配線１１０を形成する。このと
き、第２のゲイト電極は薄膜半導体１０４のほとんどを
覆うような形状である。（図８（Ｄ））After that, a film of an appropriate material (for example, aluminum or tantalum) is formed by a known metal film forming method, and this is subjected to pattern formation and etching by a known photolithography method and etching method, Second gate electrode 108, source electrode / wiring 1
09, the drain electrode / wiring 110 is formed. At this time, the second gate electrode has a shape that covers most of the thin film semiconductor 104. (Figure 8 (D))
【００４０】次に、第２のゲイト絶縁膜をエッチングす
る。この際、第２のゲイト電極１０８、ソース電極・配
線１０９、ドレイン電極・配線１１０、絶縁物パターン
１１３がエッチングされない条件を選択すると、これら
に覆われていない部分のみが選択的にエッチングされ、
ソース領域用の開孔部１１４、ドレイン領域用の開孔部
１１５が形成される。もし、そのようなエッチング条件
がなくとも、再度、裏面露光をおこなえばよい。今回の
露光では、第１のゲイト電極１０２に加えて、第２のゲ
イト電極１０８、ソース電極・配線１０９、ドレイン電
極・配線１１０もマスクとなり、結果的に、開孔部１１
４、１１５に相当する部分のパターンを得ることができ
る。（図８（Ｅ））Next, the second gate insulating film is etched. At this time, if the condition that the second gate electrode 108, the source electrode / wiring 109, the drain electrode / wiring 110, and the insulator pattern 113 are not etched is selected, only the portion not covered by these is selectively etched,
An opening 114 for the source region and an opening 115 for the drain region are formed. Even if there is no such etching condition, the back surface exposure may be performed again. In this exposure, in addition to the first gate electrode 102, the second gate electrode 108, the source electrode / wiring 109, and the drain electrode / wiring 110 also serve as masks, resulting in the opening 11
A pattern of a portion corresponding to 4, 115 can be obtained. (Fig. 8 (E))
【００４１】次に、公知の薄膜半導体形成技術により、
Ｎ型もしくはＰ型にドーピングされた薄膜半導体を形成
し、これをエッチングして、ソース領域１０５、ドレイ
ン領域１０６を得る。これらは開孔部１１４、１１５を
通して、薄膜半導体１０４に接続すると同時、それぞ
れ、ソース電極・配線１０９、ドレイン電極・配線１１
０に接続する。（図８（Ｆ））Next, by a known thin film semiconductor forming technique,
An N-type or P-type doped thin film semiconductor is formed, and this is etched to obtain a source region 105 and a drain region 106. These are connected to the thin film semiconductor 104 through the openings 114 and 115, and at the same time, the source electrode / wiring 109 and the drain electrode / wiring 11 respectively.
Connect to 0. (Figure 8 (F))
【００４２】本実施例では、マスク合わせ工程は、
第１のゲイト電極１０２のパターン形成
薄膜半導体１０４のパターン形成
第２のゲイト電極１０８、ソース電極・配線１０９、
ドレイン電極・配線１１０のパターン形成
ソース領域１０５、ドレイン領域１０６のパターン形
成
の４回であり、他のフォトリソグラフィー工程では、マ
スク合わせは不要で、全て自己整合的にパターン形成で
きる。In the present embodiment, the mask alignment step is performed by patterning the first gate electrode 102, patterning the thin film semiconductor 104, second gate electrode 108, source electrode / wiring 109,
Pattern formation of the drain electrode / wiring 110 is four times of pattern formation of the source region 105 and the drain region 106. In other photolithography processes, mask alignment is not necessary and all patterns can be formed in a self-aligned manner.
【００４３】これに対し、従来の構造のボトムゲイト型
ＴＦＴでも、裏面露光技術を用いた場合のマスク合わせ
の回数は４回であり、本実施例では、第２のゲイト電極
を有するにも関わらず、従来のものと同じ回数である。
このように、本実施例では、従来と比べて、特に作業工
程が増大するということはない。On the other hand, even in the bottom gate type TFT having the conventional structure, the number of times of mask alignment is 4 when the back surface exposure technique is used. In this embodiment, the second gate electrode is provided. No, it is the same number as the conventional one.
As described above, in this embodiment, the number of working steps is not particularly increased as compared with the conventional case.
【００４４】本実施例では、第２のゲイト電極は図７
（Ｂ）に示されるような微細なパターンを有する形状で
はない。しかしながら、電気的には、図７（Ｂ）に示さ
れる第２のゲイト電極と同じである。なぜならば、絶縁
物パターン１１３が存在するために、第２のゲイト電極
のうち、絶縁物パターン１１３の上に存在する部分は、
薄膜半導体に電気的な作用を及ぼしえないからである。
そして、絶縁物層１１３は第１のゲイト電極１０２によ
って、自己整合的にパターン形成されるので、ベース領
域と第１のゲイト電極１０２は実質的に同じ形状であ
る。もし、非自己整合的なパターン形成であれば、マス
ク合わせのズレにより、何らかの重なりを生じる。In the present embodiment, the second gate electrode is shown in FIG.
The shape does not have a fine pattern as shown in FIG. However, electrically, it is the same as the second gate electrode shown in FIG. Because the insulator pattern 113 exists, the portion of the second gate electrode existing on the insulator pattern 113 is
This is because the thin film semiconductor cannot exert an electrical action.
Since the insulating layer 113 is patterned by the first gate electrode 102 in a self-aligned manner, the base region and the first gate electrode 102 have substantially the same shape. If the pattern is formed in a non-self-aligned manner, some misalignment may occur due to mask misalignment.
【００４５】[0045]
【発明の効果】本発明によって、薄膜半導体装置の非選
択時のリーク電流を低減させることが可能となった。し
かし、選択時のドレイン電流は従来のものと遜色ない程
度であり、結果として、ＯＮ／ＯＦＦ比を向上させるこ
とができる。本発明の薄膜半導体装置は、特に、ソース
領域−ドレイン領域間のリーク電流が低いことの要求さ
れる液晶ディスプレーのアクティブマトリクス回路にお
ける画素制御用のトランジスタのようにＯＮ／ＯＦＦ比
が高く、ダイナミックな動きの要求される用途に好まし
い。このように本発明は工業上、有益な発明である。According to the present invention, it becomes possible to reduce the leak current when the thin film semiconductor device is not selected. However, the drain current at the time of selection is comparable to the conventional one, and as a result, the ON / OFF ratio can be improved. The thin film semiconductor device of the present invention has a high ON / OFF ratio and a high dynamic ON / OFF ratio like a pixel control transistor in an active matrix circuit of a liquid crystal display, which requires a low leak current between a source region and a drain region. Suitable for applications that require movement. Thus, the present invention is an industrially useful invention.
【図１】 本発明の半導体装置の基本的な構成を示す。FIG. 1 shows a basic configuration of a semiconductor device of the present invention.
【図２】 本発明の半導体装置の基本的な動作原理を示
す。FIG. 2 shows a basic operation principle of a semiconductor device of the present invention.
【図３】 実施例１の半導体装置の断面図を示す。FIG. 3 is a sectional view of the semiconductor device according to the first embodiment.
【図４】 本発明の半導体装置の基本的な動作原理を示
す。FIG. 4 shows a basic operation principle of the semiconductor device of the present invention.
【図５】 本発明の半導体装置の基本的な動作原理を示
す。FIG. 5 shows a basic operation principle of the semiconductor device of the present invention.
【図６】 本発明の半導体装置の基本的な動作原理を示
す。FIG. 6 shows a basic operation principle of the semiconductor device of the present invention.
【図７】 実施例１の半導体装置の上面図を示す。FIG. 7 is a top view of the semiconductor device according to the first embodiment.
【図８】 実施例２の半導体装置の作製工程を示す。
（断面図）FIG. 8 shows a process of manufacturing a semiconductor device according to a second embodiment.
(Cross section)
１・・・基板 ２・・・第１のゲイト電極 ３・・・第１のゲイト絶縁膜 ４・・・薄膜半導体 ５・・・ソース領域 ６・・・ドレイン領域 ７・・・第２のゲイト絶縁膜 ８・・・第２のゲイト電極 ９・・・ソース電極・配線 １０・・・ドレイン電極・配線 １１・・・反転領域 １２・・・ベース領域 １０１・・・基板 １０２・・・第１のゲイト電極 １０３・・・第１のゲイト絶縁膜 １０４・・・薄膜半導体 １０５・・・ソース領域 １０６・・・ドレイン領域 １０７・・・第２のゲイト絶縁膜 １０８・・・第２のゲイト電極 １０９・・・ソース電極・配線 １１０・・・ドレイン電極・配線 １１３・・・マスク層 １１４・・・ソース領域用開孔部 １１５・・・ドレイン領域用開孔部 1 ... Substrate 2 ... First gate electrode 3 ... First gate insulating film 4 ... Thin film semiconductor 5 ... Source area 6 ... Drain region 7: second gate insulating film 8 ... Second gate electrode 9 ... Source electrode / wiring 10 ... Drain electrode / wiring 11 ... Inversion area 12 ... Base area 101 ... substrate 102 ... First gate electrode 103 ... First gate insulating film 104 ... Thin film semiconductor 105 ... Source area 106 ... Drain region 107 ... second gate insulating film 108: second gate electrode 109 ... Source electrode / wiring 110 ... Drain electrode / wiring 113 ... Mask layer 114 ... Source area aperture 115 ... Opening for drain region
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−82834（ＪＰ，Ａ) 特開 平３−163877（ＪＰ，Ａ) 特開 平４−219980（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/786 H01L 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-82834 (JP, A) JP-A-3-163877 (JP, A) JP-A-4-219980 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 29/786 H01L 21/336
Claims (13)
ス領域と前記ドレイン領域との間に第１の領域を有し、
第１および第２の主面を有する薄膜半導体と、 前記第１の領域の第１の主面に対向して設けられ、正又
は負の電圧を印加することにより選択状態、非選択状態
を制御する第１のゲイト電極と、 前記薄膜半導体と前記第１のゲイト電極との間に設けら
れた第１のゲイト絶縁膜と、 前記第１の領域の第２の主面に対向して設けられ、選択
状態のときに前記第１のゲイト電極と極性が同じ電圧又
は前記ソース領域の電位と同じ電位となるような電圧が
印加され、非選択状態のときに前記第１のゲイト電極と
極性が逆の電圧が印加される複数の第２のゲイト電極
と、 前記薄膜半導体と前記複数の第２のゲイト電極との間に
設けられた第２のゲイト絶縁膜とを有する半導体装置で
あって、前記薄膜半導体の前記第１の領域は、前記複数の第２の
ゲイト電極と重ならないベース領域を有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きい ことを特徴とする半導体装置。1. A have a first region between the source region, the drain region and the source region and the drain region,
A thin film semiconductor having a first and second major surfaces, provided to face the first main surface of said first region, positive or
Is in the selected or non-selected state by applying a negative voltage
A first gate electrode that controls the the first gate insulating film provided between the thin film semiconductor and the first gate electrode, to face the second major surface of said first region Provided and selected
In the state, the voltage or polarity is the same as that of the first gate electrode.
Is a voltage that is the same as the potential of the source region
Applied to the first gate electrode when in a non-selected state
A semiconductor device comprising: a plurality of second gate electrodes to which voltages having opposite polarities are applied; and a second gate insulating film provided between the thin film semiconductor and the plurality of second gate electrodes. And the first region of the thin film semiconductor is
It has a base region that does not overlap with the gate electrode, and the above-mentioned source region passes through only the base region.
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
A semiconductor device characterized by being larger than the separation .
ス領域と前記ドレイン領域との間に第１の領域を有する
薄膜半導体と、 前記薄膜半導体下に第１のゲイト絶縁膜を介して設けら
れ、正又は負の電圧を印加することにより選択状態、非
選択状態を制御する第１のゲイト電極と、 前記薄膜半導体上に第２のゲイト絶縁膜を介して設けら
れ、選択状態のときに前記第１のゲイト電極と極性が同
じ電圧又は前記ソース領域の電位と同じ電位となるよう
な電圧が印加され、非選択状態のときに前記第１のゲイ
ト電極と極性が逆の電圧が印加される複数の第２のゲイ
ト電極とを有する半導体装置であって、前記薄膜半導体の前記第１の領域は、前記複数の第２の
ゲイト電極と重ならないベース領域を有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きい ことを特徴とする半導体装置。Wherein the source region, and a thin film semiconductor having a first region between the drain region and the source region and the drain region, provided via a first gate insulating film under the thin film semiconductor, a positive Or by applying a negative voltage, the selected state
A first gate electrode for controlling a selected state, and a second gate insulating film provided on the thin film semiconductor via a second gate insulating film, and having the same polarity as the first gate electrode in the selected state.
The same voltage or the same potential as the source region
Voltage is applied to the first gay when it is in a non-selected state.
And a plurality of second gate electrodes to which a voltage having a reverse polarity is applied , the first region of the thin film semiconductor being the plurality of second gate electrodes .
It has a base region that does not overlap with the gate electrode, and the above-mentioned source region passes through only the base region.
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
A semiconductor device characterized by being larger than the separation .
ス領域と前記ドレイン領域との間に第１の領域を有し、
第１および第２の主面を有する薄膜半導体と、 前記第１の領域の第１の主面に対向して設けられ、正又
は負の電圧を印加することにより選択状態、非選択状態
を制御する第１のゲイト電極と、 前記薄膜半導体と前記第１のゲイト電極との間に設けら
れた第１のゲイト絶縁膜と、 前記第１の領域の第２の面に対向して設けられ、選択状
態のときに前記第１のゲイト電極と極性が同じ電圧が印
加され、非選択状態のときに前記第１のゲイト電極と極
性が逆の電圧又は前記ソース領域の電位と同じ電位とな
るような電圧が印加される複数の第２のゲイト電極と、 前記薄膜半導体と前記複数の第２のゲイト電極との間に
設けられた第２のゲイト絶縁膜とを有する半導体装置で
あって、前記薄膜半導体の前記第１の領域は、前記複数の第２の
ゲイト電極と重ならないベース領域を有し、 前記第１のゲイト電極は、前記ベース領域と同じ形状を
有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きい ことを特徴とする半導体装置。3. A source region, have a first region between the drain region and the source region and the drain region,
A thin film semiconductor having a first and second major surfaces, provided to face the first main surface of said first region, positive or
Is in the selected or non-selected state by applying a negative voltage
And a first gate insulating film provided between the thin film semiconductor and the first gate electrode, and a first gate electrode for controlling the Selected letter
In this state, a voltage with the same polarity as the first gate electrode is applied.
And the first gate electrode and the pole in the non-selected state.
Of opposite polarity or the same potential as that of the source region.
A plurality of second gate electrodes to which a voltage is applied, and a second gate insulating film provided between the thin film semiconductor and the plurality of second gate electrodes. , The first region of the thin-film semiconductor includes the plurality of second regions.
The first gate electrode has a base region that does not overlap with the gate electrode, and has the same shape as the base region.
From the source region via only the base region
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
A semiconductor device characterized by being larger than the separation .
ス領域と前記ドレイン領域との間に第１の領域を有する
薄膜半導体と、 前記薄膜半導体下に第１のゲイト絶縁膜を介して設けら
れ、正又は負の電圧を印加するこ とにより選択状態、非
選択状態を制御する第１のゲイト電極と、 前記薄膜半導体上に第２のゲイト絶縁膜を介して設けら
れ、選択状態のときに前記第１のゲイト電極と極性が同
じ電圧が印加され、非選択状態のときに前記第１のゲイ
ト電極と極性が逆の電圧又は前記ソース領域の電位と同
じ電位となるような電圧が印加される複数の第２のゲイ
ト電極とを有する半導体装置であって、前記薄膜半導体の前記第１の領域は、前記複数の第２の
ゲイト電極と重ならないベース領域を有し、 前記第１のゲイト電極は、前記ベース領域と同じ形状を
有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きい ことを特徴とする半導体装置。4. A thin film semiconductor having a source region, a drain region, and a first region between the source region and the drain region, and a positive gate insulating film provided under the thin film semiconductor. or negative voltage selected by the child application, non
A first gate electrode for controlling a selected state, and a second gate insulating film provided on the thin film semiconductor via a second gate insulating film, and having the same polarity as the first gate electrode in the selected state.
When the same voltage is applied and the non-selected state, the first gay
Voltage of the same polarity as the source electrode or the same potential as the source region
A semiconductor device having a plurality of second gate electrodes to which a voltage having the same potential is applied , wherein the first region of the thin film semiconductor has a plurality of second gate electrodes .
The first gate electrode has a base region that does not overlap with the gate electrode, and has the same shape as the base region.
From the source region via only the base region
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
A semiconductor device characterized by being larger than the separation .
２のゲイト電極に非選択状態のときに印加する電圧を前
記ソース領域の電位と同じ電位となるような電圧にした
ときに、前記第２のゲイト電極に選択状態のときに印加
する電圧を前記第１のゲイト電極に印加する電圧の０．
５〜２倍にすることを特徴とする半導体装置。 5. The method according to claim 3 or 4,
The voltage applied to the 2nd gate electrode in the non-selected state is
The voltage is set to be the same as the potential of the source region.
When the selected state is applied to the second gate electrode
Of the voltage applied to the first gate electrode is 0.
A semiconductor device characterized by being 5 to 2 times larger.
前記複数の第２のゲイト電極の数は３以上であることを
特徴とする半導体装置。6. The method according to any one of claims 1 to 5,
A semiconductor device, wherein the number of the plurality of second gate electrodes is 3 or more.
ス領域と前記ドレイン領域との間に第１の領域を有し、
第１および第２の主面を有する薄膜半導体と、 前記第１の領域の第１の主面に対向して設けられ、正又
は負の電圧を印加することにより選択状態、非選択状態
を制御する第１のゲイト電極と、 前記薄膜半導体と前記第１のゲイト電極との間に設けら
れた第１のゲイト絶縁膜と、 前記第１の領域の第２の主面に対向して設けられ、選択
状態のときに前記第１のゲイト電極と極性が同じ電圧が
印加され、非選択状態のときに前記第１のゲイト電極と
極性が逆の電圧又は前記ソース領域の電位と同じ電位と
なるような電圧が印加される第２のゲイト電極と、 前記薄膜半導体と前記第２のゲイト電極との間に設けら
れた第２のゲイト絶縁膜及び絶縁物パターンを有する半
導体装置であって、前記絶縁物パターンは、前記第１のゲイト電極と同じ形
状を有し、 前記薄膜半導体の前記第１の領域は、前記絶縁物パター
ンが存在するため前記第２のゲイト電極による電気的な
作用が及ばないベース領域を有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きく、 前記絶縁物パターンは、前記第２の絶縁膜と異なる材料
でなることを特徴とする半導体装置。7. A source region, have a first region between the drain region and the source region and the drain region,
A thin film semiconductor having a first and second major surfaces, provided to face the first main surface of said first region, positive or
Is in the selected or non-selected state by applying a negative voltage
A first gate electrode that controls the the first gate insulating film provided between the thin film semiconductor and the first gate electrode, to face the second major surface of said first region Provided and selected
In this state, a voltage with the same polarity as the first gate electrode
Applied to the first gate electrode when in a non-selected state
With the opposite polarity voltage or the same potential as the source region potential
A semiconductor device having a second gate electrode to which such a voltage is applied, a second gate insulating film provided between the thin film semiconductor and the second gate electrode, and an insulator pattern , The insulator pattern has the same shape as the first gate electrode.
And the first region of the thin film semiconductor has a shape of the insulator pattern.
Of the second gate electrode
It has a base region that does not act, and from the source region via only the base region
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
The semiconductor device is larger than the separation, and the insulator pattern is made of a material different from that of the second insulating film.
ス領域と前記ドレイン領域との間に第１の領域を有する
薄膜半導体と、 前記薄膜半導体下に第１のゲイト絶縁膜を介して設けら
れ、正又は負の電圧を印加することにより選択状態、非
選択状態を制御する第１のゲイト電極と、 前記薄膜半導体上に設けられた第２のゲイト絶縁膜と、 前記第２のゲイト絶縁膜上に設けられた絶縁物パターン
と、 前記第２のゲイト絶縁膜及び前記絶縁物パターン上に設
けられ、選択状態のときに前記第１のゲイト電極と極性
が同じ電圧が印加され、非選択状態のときに前記第１の
ゲイト電極と極性が逆の電圧又は前記ソース領域の電位
と同じ電位となるような電圧が印加される第２のゲイト
電極とを有する半導体装置であって、前記絶縁物パターンは、前記第１のゲイト電極と同じ形
状を有し、 前記薄膜半導体の前記第１の領域は、前記絶縁物パター
ンが存在するため前記第２のゲイト電極による電気的な
作用が及ばないベース領域を有し、 前記ベース領域のみを経由して前記ソース領域から前記
ドレイン領域へ至る最短距離は、 前記第１の領域を経由
して前記ソース領域から前記ドレイン領域へ至る最短距
離よりも大きく、 前記絶縁物パターンは、前記第２のゲイト絶縁膜と異な
る材料でなることを特徴とする半導体装置。8. A thin film semiconductor having a source region, a drain region, and a first region between the source region and the drain region, and a positive gate insulating film provided below the thin film semiconductor , Or by applying a negative voltage, the selected state
A first gate electrode for controlling a selection state, a second gate insulating film provided on the thin film semiconductor, an insulator pattern provided on the second gate insulating film, It is provided on the second gate insulating film and the insulator pattern , and has a polarity with the first gate electrode in the selected state.
Are applied with the same voltage and are in the non-selected state, the first
A voltage whose polarity is opposite to that of the gate electrode or the potential of the source region
A semiconductor device having a second gate electrode voltage such that the same potential is applied between the insulator pattern, the same shape as the first gate electrode
And the first region of the thin film semiconductor has a shape of the insulator pattern.
Of the second gate electrode
It has a base region that does not act, and from the source region via only the base region
The shortest distance to the drain region is via the first region
And the shortest distance from the source region to the drain region
The semiconductor device is characterized in that it is larger than the separation and the insulator pattern is made of a material different from that of the second gate insulating film.
前記ベース領域の面積を当該ベース領域のみを経由して
前記ソース領域から前記ドレイン領域へ至る最短経路長
により除した値は、前記第１の領域の面積を前記ソース
領域から前記ドレイン領域へ至る最短経路長により除し
た値よりも小さいことを特徴とする半導体装置。9. In any one of claims 1 to 8,
The value obtained by dividing by the shortest path length extending the area of the base region from the source region by way of only the base region to the drain region, the shortest reaching the area of the first region from the source region to the drain region A semiconductor device characterized by being smaller than a value divided by a path length.
て、さらに、前記ソース領域又は前記ドレイン領域のい
ずれか一方に接続する配線を有し、前記配線は、前記第
２のゲイト電極と同じ被膜より形成されることを特徴と
する半導体装置。10. A any one of claims 1 to 9, further comprising a wiring connected to one of the source region or the drain region, the wiring is the same film as the second gate electrode A semiconductor device, which is formed by:
て、前記第２のゲイト電極は、前記ソース領域及び前記
ドレイン領域と重ならないように設けられていることを
特徴とする半導体装置。11. In any one of claims 1 to 10, wherein the second gate electrode, wherein a is provided so as not to overlap with the source region and the drain region.
て、前記薄膜半導体は絶縁表面を有する基板上に設けら
れていることを特徴とする半導体装置。12. The any one of claims 1 to 11, wherein the thin film semiconductor is a semiconductor device, characterized in that provided on a substrate having an insulating surface.
る前記半導体装置を用いたアクティブマトリクス型表示
装置。13. An active matrix display device using the semiconductor device in any one of claims 1 to 12.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08753196A JP3535307B2 (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
| US08/818,166 US5955765A (en) | 1996-03-15 | 1997-03-14 | Thin-film dual gate, common channel semiconductor device having a single first gate and a multi-gate second gate structure |
| KR1019970009143A KR100373940B1 (en) | 1996-03-15 | 1997-03-15 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08753196A JP3535307B2 (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09252140A JPH09252140A (en) | 1997-09-22 |
| JP3535307B2 true JP3535307B2 (en) | 2004-06-07 |
Family
ID=13917581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08753196A Expired - Fee Related JP3535307B2 (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5955765A (en) |
| JP (1) | JP3535307B2 (en) |
| KR (1) | KR100373940B1 (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11112002A (en) * | 1997-10-07 | 1999-04-23 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture therefor |
| JPH11274509A (en) | 1998-03-26 | 1999-10-08 | Sanyo Electric Co Ltd | Thin film transistor and liquid crystal display |
| JP3433101B2 (en) | 1998-06-03 | 2003-08-04 | 三洋電機株式会社 | Display device |
| JP3702096B2 (en) * | 1998-06-08 | 2005-10-05 | 三洋電機株式会社 | Thin film transistor and display device |
| JP2000258798A (en) * | 1999-03-05 | 2000-09-22 | Sanyo Electric Co Ltd | Display device |
| TW526355B (en) | 1999-07-14 | 2003-04-01 | Sanyo Electric Co | Reflection type liquid crystal display device |
| US6906344B2 (en) * | 2001-05-24 | 2005-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with plural channels and corresponding plural overlapping electrodes |
| JP4869497B2 (en) * | 2001-05-30 | 2012-02-08 | 株式会社半導体エネルギー研究所 | Display device |
| US6642133B2 (en) * | 2001-12-20 | 2003-11-04 | Intel Corporation | Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering |
| JP4024557B2 (en) | 2002-02-28 | 2007-12-19 | 株式会社半導体エネルギー研究所 | Light emitting device, electronic equipment |
| JP4641710B2 (en) | 2003-06-18 | 2011-03-02 | 株式会社半導体エネルギー研究所 | Display device |
| US7595775B2 (en) * | 2003-12-19 | 2009-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting display device with reverse biasing circuit |
| US7592975B2 (en) * | 2004-08-27 | 2009-09-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device and driving method thereof |
| US20100322006A1 (en) * | 2009-06-22 | 2010-12-23 | Ming Sang Kwan | Nand memory cell string having a stacked select gate structure and process for for forming same |
| US10038004B2 (en) | 2009-06-22 | 2018-07-31 | Cypress Semiconductor Corporation | NAND memory cell string having a stacked select gate structure and process for for forming same |
| KR20110037220A (en) * | 2009-10-06 | 2011-04-13 | 삼성모바일디스플레이주식회사 | Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor |
| KR101056229B1 (en) * | 2009-10-12 | 2011-08-11 | 삼성모바일디스플레이주식회사 | An organic light emitting display device comprising a thin film transistor, a method of manufacturing the same, and a thin film transistor |
| US8969928B2 (en) * | 2010-08-31 | 2015-03-03 | Micron Technology, Inc. | Transistors having a control gate and one or more conductive structures |
| US9735382B2 (en) * | 2012-11-08 | 2017-08-15 | Palo Alto Research Center Incorporated | Circuit layout for thin film transistors in series or parallel |
| GB2515750B (en) * | 2013-07-01 | 2017-11-15 | Flexenable Ltd | Supressing Leakage Currents in a Multi - TFT Device |
| KR102100927B1 (en) * | 2013-08-05 | 2020-05-15 | 삼성전자주식회사 | High electron mobility transistor, method of manufacturing the same and electronic device including transistor |
| KR102162909B1 (en) * | 2013-12-23 | 2020-10-07 | 엘지디스플레이 주식회사 | Array Substrate Including Thin Film Transistor And Method Manufacturing The Same |
| KR102159684B1 (en) | 2014-02-17 | 2020-09-25 | 삼성디스플레이 주식회사 | Thin film transistor |
| US9379164B2 (en) * | 2014-03-06 | 2016-06-28 | Kabushiki Kaisha Toshiba | Integrated circuit device |
| TWI563640B (en) * | 2014-08-22 | 2016-12-21 | Innolux Corp | Array substrate of display panel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446299A (en) * | 1994-04-29 | 1995-08-29 | International Business Machines Corporation | Semiconductor random access memory cell on silicon-on-insulator with dual control gates |
| US5497019A (en) * | 1994-09-22 | 1996-03-05 | The Aerospace Corporation | Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods |
-
1996
- 1996-03-15 JP JP08753196A patent/JP3535307B2/en not_active Expired - Fee Related
-
1997
- 1997-03-14 US US08/818,166 patent/US5955765A/en not_active Expired - Lifetime
- 1997-03-15 KR KR1019970009143A patent/KR100373940B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100373940B1 (en) | 2003-07-18 |
| JPH09252140A (en) | 1997-09-22 |
| US5955765A (en) | 1999-09-21 |
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