JPS58170065A - Manufacture of thin film field effect transistor - Google Patents
Manufacture of thin film field effect transistorInfo
- Publication number
- JPS58170065A JPS58170065A JP5142182A JP5142182A JPS58170065A JP S58170065 A JPS58170065 A JP S58170065A JP 5142182 A JP5142182 A JP 5142182A JP 5142182 A JP5142182 A JP 5142182A JP S58170065 A JPS58170065 A JP S58170065A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- gate electrode
- semiconductor thin
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000010408 film Substances 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000000354 decomposition reaction Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 229910052738 indium Inorganic materials 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 2
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical group [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 7
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 229910001887 tin oxide Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
、！Ｆ：発明は半導体薄膜を用いた電界効果トランジス
タの製造方法忙関する。[Detailed description of the invention] [Technical field to which the invention pertains] ,! F: The invention relates to a method of manufacturing a field effect transistor using a semiconductor thin film.
近年、多結晶又は非晶質半導体により形成された薄膜電
界効果トランジスタ（ＴＰＴ）が注目されている。特に
、上記半導体薄膜が低温で形成できる場合には、薄膜半
導体装置を構成するためＯ基板が特に限定されず、又，
従来の露光技術、エツチング技術等のパターン形成法も
そのまま使用できる場合が多いなどの利点を有するため
、目的に応じて、多種多様の構造の半導体装置が実現で
きも。In recent years, thin film field effect transistors (TPTs) formed from polycrystalline or amorphous semiconductors have attracted attention. In particular, when the semiconductor thin film can be formed at a low temperature, the O substrate is not particularly limited to constitute a thin film semiconductor device, and
It has the advantage that conventional pattern forming methods such as exposure technology and etching technology can often be used as is, so semiconductor devices with a wide variety of structures can be realized depending on the purpose.
これらの半導体薄膜を用いた半導体装置の機能を十分に
発揮するために、同一基板内にスイッチング素子や能動
回路素子として、と起生導体薄膜により形成されたＴＰ
Ｔを設けることが多い。In order to fully demonstrate the functions of semiconductor devices using these semiconductor thin films, TPs formed from conductive thin films are used as switching elements and active circuit elements on the same substrate.
T is often provided.
第１図および第２図は従来のＴＰＴの２つの基本−造を
概略的に示す図である。これらの図においてｌは基板、
２は多結晶あるいは非晶質半導体薄膜、３はゲート絶縁
膜、４はゲート電極、５，６はそれぞれソース、ドレイ
ン金属電極である。第１図のものは半導体薄膜２の同じ
面側にゲート電極４゜ソース電極５およびドレイン電極
６が設けられ、第２図のものは半導体薄膜２の下面側に
ゲート電極４、上面側にソース電極５およびドレイン電
極６が設けられている。これらのＴＰＴは結晶シリコン
を用い九いわゆるＭＯ８ＦＩＴと類似の電気的特性を示
すが、ＭＯ８ＦＩＴとの動作原還の根本的衣違いはトラ
ンジスタのチャンネルの連断条件が、ＭＯ８ＦＩＴでは
ＰＮ接合の逆方向特性を利用するのに対しＴＰＴでは半
導体薄膜２の高ｉ抗を利用する点であ’ ６ ｏ
ｆ ＋ ７４４゜ｌＡ＃１１ｔｉ＃Ｋ、ＩＥＷ＠＊Ｋ
ｘる半導体表面の反転あるいはキャリヤ蓄積を利用゛
する。従って、これらのＴＰＴを構成するためＫは半導
体薄膜２の非導通状態での抵抗がチャンネル形成、時の
抵抗に比べ十分高いことが必要である。1 and 2 are diagrams schematically showing two basic structures of a conventional TPT. In these figures, l is the substrate,
2 is a polycrystalline or amorphous semiconductor thin film, 3 is a gate insulating film, 4 is a gate electrode, and 5 and 6 are source and drain metal electrodes, respectively. The one in FIG. 1 has a gate electrode 4, a source electrode 5, and a drain electrode 6 on the same side of the semiconductor thin film 2, and the one in FIG. 2 has a gate electrode 4 on the bottom side of the semiconductor thin film 2 and a source on the top side. An electrode 5 and a drain electrode 6 are provided. These TPTs use crystalline silicon and exhibit electrical characteristics similar to those of the so-called MO8FIT, but the fundamental difference in operating principle from the MO8FIT is the connection condition of the transistor channel, whereas the MO8FIT has the reverse characteristics of the PN junction. In contrast, TPT utilizes the high i resistance of the semiconductor thin film 2.
f + 744゜lA#11ti#K, IEW@*K
This method utilizes the inversion or carrier accumulation of the semiconductor surface. Therefore, in order to construct these TPTs, it is necessary that the resistance of the semiconductor thin film 2 in the non-conducting state is sufficiently higher than the resistance during channel formation.
さて′、これらのＴＰＴは多結晶又は非晶質半導体薄膜
を用いるため結晶半導体に比べ、キャリヤとなる電子中
正孔の移動度が低くなる０特に非晶質半導体では顕著で
ある。このため、結晶半導体材料を用いたＭＯ８ＦＥＴ
に比べ、ＴＰＴの動作周波数の限界はかなり低くなって
しまう。また、このようなＴＰＴを基板上に複数個集積
化した場合には、その動作速度は、上記動作周波数の限
界よりも一般にかなり遅くなる。これは、主に配線やト
ランジスタ構造に基づく寄生容量のための時間遅れが原
因となる。ＴＰＴでは、絶縁体の基板を使用できるため
、配線と基板間の寄生容量をさけることは容量であるが
、第１図あるいは第２図の構造では、ソース・ゲート間
あるいはドレイン・ゲート間の電極の砿なりによる寄生
容量の影響が大きい。一般に、寄生容量を有するＴＰＴ
を含む回路の動作速度を上げる丸めには、ＴＰＴのＯＮ
状態における抵抗を下げればよいが、このためにはＴＰ
Ｔの電流路の幅（チャンネル幅）を大会くする必要があ
る。この場合従来構造のＴＰＴでは、寄生容量もチャン
ネル幅に比例して増えるため、本質的な動作速度の向上
とはならない。Now, since these TPTs use polycrystalline or amorphous semiconductor thin films, the mobility of holes in electrons serving as carriers is lower than in crystalline semiconductors, which is particularly noticeable in amorphous semiconductors. For this reason, MO8FET using crystalline semiconductor material
Compared to this, the operating frequency limit of TPT is considerably lower. Furthermore, when a plurality of such TPTs are integrated on a substrate, the operating speed thereof is generally much slower than the above-mentioned operating frequency limit. This is mainly caused by time delays due to parasitic capacitance based on wiring and transistor structures. In TPT, an insulating substrate can be used, so parasitic capacitance between the wiring and the substrate can be avoided using capacitance. The influence of parasitic capacitance due to the roundness of In general, TPT with parasitic capacitance
To increase the operating speed of circuits containing
It is only necessary to lower the resistance in the state, but for this purpose the TP
It is necessary to increase the width of the current path (channel width) of T. In this case, in the conventional TPT structure, the parasitic capacitance also increases in proportion to the channel width, so that the operating speed is not essentially improved.
本発明は上記の点に鑑み、ゲート電極とソースドレイン
電極とを自己整合させてＴＰＴ回路の動作速度の向上を
図り、素子の微細化と高集積化を可能とするＴＰＴの製
造方法を提供するものである。In view of the above points, the present invention provides a TPT manufacturing method that improves the operating speed of a TPT circuit by self-aligning a gate electrode and a source/drain electrode, and enables miniaturization and high integration of elements. It is something.
又、ソース・ドレイン電極のコンタクト抵抗を下げて特
性を向上させる事を第２の目的とする。A second purpose is to lower the contact resistance of the source/drain electrodes and improve the characteristics.
本発明においては、基板上にまず所定パターンのゲート
電極を形成し、この上にゲート絶縁膜を介してソース、
ドレイン電極を形成し、そのトに半導体薄膜を堆積する
。この場合、基板とゲート絶縁膜を透明材料とし、ゲー
ト電極を不透明材料として、ゲート絶縁膜上くソース・
ドレイ／電極となる不純物添加半導体薄膜を形成する。In the present invention, a gate electrode of a predetermined pattern is first formed on a substrate, and a source and a
A drain electrode is formed, and a semiconductor thin film is deposited on the drain electrode. In this case, the substrate and gate insulating film are made of transparent material, the gate electrode is made of opaque material, and the source and
An impurity-doped semiconductor thin film is formed to serve as a drain/electrode.
このソース、ドレイン電極を基板裏面からの露光を利用
□してゲート電極に自己整合させてパターニング
する０即ちその上にレジストを塗布してフオトエッチン
グエ楊により基板裏面からゲート電極をマスクとして露
光し、これを現像して、不純物添加半導体膜をゲート電
極に自己整合され九ソース、ドレイン電極としてパター
ニングスル。The source and drain electrodes are patterned using exposure from the back side of the substrate and self-aligned with the gate electrode. In other words, a resist is applied thereon and exposed from the back side of the substrate using the gate electrode as a mask. This is then developed and the impurity-doped semiconductor film is self-aligned to the gate electrode and patterned as nine source and drain electrodes.
本発明によれば、ゲート電極とソース、ドレイン電極と
の間の寄生容量が小さく、高速動作が可能となるだけで
なく、ＴＰＴ回路の微細化、高集積化を図ることができ
、又、不純物添加半導体膜により良好なオーミックコン
タクトが取れる。According to the present invention, the parasitic capacitance between the gate electrode and the source and drain electrodes is small, and not only high-speed operation is possible, but also miniaturization and high integration of TPT circuits can be achieved. Good ohmic contact can be made with the added semiconductor film.
以下、本発明の実施例を＃Ｉ３図（ａ）〜（ｄ）を用い
て説明する。まず透明ガラス基板１１上に厚さ１００Ｏ
ＸのＭのスパッター、バターニングによりゲート電極１
２を形成し、次いで透明なゲート絶縁膜としてスパッタ
ーにより厚さ３０００＾の酸化シリコン膜１３を堆積さ
せ、更にスパッターで約１ＯｏｏＸのインジラム、スズ
酸化膜１４１を堆積させ、しかる後に８ ｉＨ４とＰＨ
ｓのグロー放電分解により、Ｐ（リン）を１０′９〜５
Ｘ １０” ／ｃｄ添加した厚さ３０〜ｔｏｏｏＸ例
えば約２００ Ｋの非晶質シリコン膜１４ｂを堆積させ
る。次にネガ形レジスト（東京応化ＯＭＲ−８３）１５
を約０．５岸ｍコートシ、基板１１の裏面よりゲート電
極１２をマスクとして紫外光で露光し、現像してレジス
トをパターニングする。次いで、Ｐを添加し九非晶シリ
コン膜及びインジウム、スズ酸化膜をエツチングして、
ゲート電極に自己整合されたソース１４、。Hereinafter, embodiments of the present invention will be described using #I3 figures (a) to (d). First, a layer with a thickness of 100O is placed on a transparent glass substrate 11.
Gate electrode 1 is formed by sputtering and buttering of M of X.
2 is formed, then a silicon oxide film 13 with a thickness of 3000^ is deposited by sputtering as a transparent gate insulating film, and an indilum and tin oxide film 141 of approximately 100X is deposited by sputtering, and then 8 iH4 and PH
By glow discharge decomposition of s, P (phosphorus) is reduced to 10'9~5
An amorphous silicon film 14b doped with X 10"/cd and having a thickness of 30~tooX, for example, about 200K is deposited.Next, a negative resist (Tokyo Ohka OMR-83) 15
The resist is exposed to ultraviolet light from the back surface of the substrate 11 using the gate electrode 12 as a mask, and developed to pattern the resist. Next, add P and etch the amorphous silicon film and the indium and tin oxide films.
a source 14, self-aligned to the gate electrode;
ドレイン１４２ 電極を形成する。次にＳｉＨ４のグロ
ー放電分解くより、ｌＸｌ０’〜１０１１Ω・１ 厚さ
５ｏｏｏＸの非晶質シリコン膜１６を堆積させ、これを
ＰｉｉＰ技術により所定のパターンに形成し、最後にソ
ースドレインの素子領域外の配線部を所望のパターンに
形成してＴＰＴを完成させる０
ここで１、良好なす−ンツクコンタクトを得る上では低
、１
１抵抗層は３０〜１ｏｏｏＸあれば良い。酸化シリコン
やインジウム、スズ酸化膜等の導電膜は透明体であるが
、上記非晶質シリコン膜も光分光を透過させ度域は４５
００Ｘ ＠度以下であるが、〜ｔｏｏｏＸの非晶質シリ
コンであれば充分コントラスト高くレジストを感光させ
る事が出来た。従ってソース、ドレイン電極を精度良く
形成す゛る事が出来る。A drain 142 electrode is formed. Next, by glow discharge decomposition of SiH4, an amorphous silicon film 16 of 1X10' to 1011Ω·1 and a thickness of 5oooX is deposited, this is formed into a predetermined pattern by PiiP technology, and finally outside the source/drain element region. The wiring portion is formed in a desired pattern to complete the TPT.0Here, 1. In order to obtain a good bond contact, the resistance layer should be 30 to 100X. Conductive films such as silicon oxide, indium, and tin oxide films are transparent, but the amorphous silicon film also transmits light spectroscopy and has a power range of 45 degrees.
Although it is less than 00X@ degree, if it is an amorphous silicon of ~tooX, it was possible to expose the resist with sufficiently high contrast. Therefore, source and drain electrodes can be formed with high precision.
以上説明し九事から明らかな様に、本発明によればソー
ス、ドレイ／電極とゲート電極間の重なり部分をほぼな
くすことができるため、これら電極間の寄生容量を最少
にし、ＴＰＴ回路の動作速度を著しく向トすることがで
きる。また、ソース、ドレイン電極はゲート電極をマス
クとする基板裏面からの露光により容易にゲート電極に
自己整合させることができる。従ってまたＴＰＴ回路の
素子の微細化、高集積化を図ることができる。As is clear from the above explanation and nine points, according to the present invention, the overlapping portion between the source, drain/electrode, and gate electrode can be almost eliminated, so that the parasitic capacitance between these electrodes can be minimized and the operation of the TPT circuit Speed can be significantly increased. In addition, the source and drain electrodes can be easily self-aligned to the gate electrode by exposure from the back surface of the substrate using the gate electrode as a mask. Therefore, the elements of the TPT circuit can be miniaturized and highly integrated.
更に、ソース、ドレイン電極をチャネル領域の半導体薄
膜と良好にオーミックコンタクトさせる事が出来る。し
かも不純物を添加した低抵抗半導体薄膜を形成してから
レジストを塗布するので歩留りも良い。例えば、レジス
トパターン形成後、ＣＶＤ法等で堆積した低抵抗半導体
薄膜をリフトオフさせる事も考えられるが、熱によって
、レジストが硬化したり半導体薄膜が汚染する等の問題
が予想される。又、半導体薄膜のＩＪラフトフに好適な
レジストの断面形状を裏面露光で精度良く形成するのも
難しいＯ
なお、本発明は上記実施例に限定されない。Furthermore, the source and drain electrodes can be brought into good ohmic contact with the semiconductor thin film in the channel region. Moreover, since the resist is applied after forming a low-resistance semiconductor thin film doped with impurities, the yield is also good. For example, it is conceivable to lift off a low-resistance semiconductor thin film deposited by CVD or the like after forming a resist pattern, but problems such as hardening of the resist and contamination of the semiconductor thin film are expected due to heat. Furthermore, it is difficult to accurately form a cross-sectional shape of a resist suitable for IJ rafting of a semiconductor thin film by backside exposure. Note that the present invention is not limited to the above embodiments.
例えば半導体薄膜は、これを通してレジストを露光で−
るものであれば曳い。例えば、非晶質半導体薄膜１４ｂ
１ｉＳｉに限らず、’：’ｅ ＋Ｇｅｘ８ ’ ｓ−８
，Ｓ ｌ ｘｃ ｔ ｘ等の化合物であってもよく、更
に高い比抵抗を有すルＣｄ８．Ｚｎ８ｅ、Ｚｎ８等の半
導体薄膜や、多結晶８ｉ等これらの多結晶半導体薄膜で
あってもよい０またソース、ドレイ／電極は必ずしも積
層構造である必１！Ｈないし、上記実施例を変形して例
えば第４図に示すようにＰドープ非晶質シリコン＠１４
ｂを主体としてＭｏ膜やインジウム、スズ酸化膜等の導
電性膜１４１を補助的に使う構造としてもよい。又、ゲ
ート絶縁膜はＳ ｉｏｚに限らず８４ｍＮ４やそれ以外
の透明絶縁膜体で４ｂよいし、ゲート電極は不透明な導
電材料であればなんでもよい０For example, a semiconductor thin film can be exposed to light through a resist.
If you can, pull it. For example, the amorphous semiconductor thin film 14b
Not limited to 1iSi, ':'e +Gex8' s-8
, S l xc t x and the like, and Cd8. It may be a semiconductor thin film such as Zn8e or Zn8, or a polycrystalline semiconductor thin film such as polycrystalline 8i. Also, the source, drain/electrode must have a laminated structure! H or by modifying the above embodiment, for example, as shown in FIG. 4, P-doped amorphous silicon@14
It is also possible to adopt a structure in which conductive film 141 such as Mo film, indium, tin oxide film, etc. is used as an auxiliary, with B as the main component. In addition, the gate insulating film is not limited to SIOZ, but may be 84mN4 or other transparent insulating film material, and the gate electrode may be made of any opaque conductive material.
第１図および第２図は従来構造のＴＰＴの断面図、第３
図（ａ）〜（ｄ）は本発明の一実施例のＴＰＴの製造工
程を示す断面図、第４図は他の実施例によるＴＰＴの断
面図である。
図に於いて、
１１・・・透明ガラス、１２・・・ゲート電極（ＡＪ）
。
１３・・・ゲート絶縁膜、１４Ｆ・・透明導電膜、１４
ｂ・・・不純物添加弗晶質シリコン膜、１４、・・ソー
ス電極、１４□・・・ドレイン電極、１５・・・レジス
ト膜、 １６・・・非晶質シリコン膜。
第１図
第２図
第３図Figures 1 and 2 are cross-sectional views of TPT with conventional structure;
Figures (a) to (d) are cross-sectional views showing the manufacturing process of a TPT according to one embodiment of the present invention, and FIG. 4 is a cross-sectional view of a TPT according to another embodiment. In the figure, 11...Transparent glass, 12...Gate electrode (AJ)
. 13... Gate insulating film, 14F... Transparent conductive film, 14
b... Impurity-doped fluoric silicon film, 14... Source electrode, 14□... Drain electrode, 15... Resist film, 16... Amorphous silicon film. Figure 1 Figure 2 Figure 3
Claims (3)
極を覆う様にゲート飴縁膜を形成する工程と、その上に
ソース・ドレイン電極となる不純物添加半導体薄膜及び
レジスト膜をこの願に積層形成する工程と、基板裏面か
ら露光するフォトエッチングエ８！により不純物添加半
導体薄膜をゲート電極に自整合してパターニングする１
楊と、この不純物添加半導体薄膜から成るソース・ドレ
イン電極と重なる様にゲート絶縁膜上に半導体薄膜を被
着する１鶏とを具備してなる事を特徴とする薄膜電界効
果トランジスタの製造方法。(1) The process of forming a gate electrode on a transparent substrate and forming a gate film to cover the gate electrode, and then forming an impurity-doped semiconductor thin film and a resist film that will become source/drain electrodes on top of the gate electrode. Step 8 of laminating layers and photo-etching to expose from the back side of the substrate! Patterning the impurity-doped semiconductor thin film in self-alignment with the gate electrode 1
A method for manufacturing a thin film field effect transistor, comprising: a layer and a layer for depositing a semiconductor thin film on a gate insulating film so as to overlap the source/drain electrodes made of the impurity-doped semiconductor thin film.
不純物添加半導体薄膜を形成する事を特徴とする特許 果トランジスタの製造方法◇(2) A patented method for manufacturing a transistor, which is characterized in that after forming a gate insulating film, a transparent conductive film is deposited, and then an impurity-doped semiconductor thin film is formed.
特徴とする前記特許請求の範囲＃Ｉｌ項記載の薄膜電界
効果トランジスタの製造方法。 ＋４） 膜Ｊｌ３０〜ｔｏｏｏＸの非晶質シリコンによ
り不純物添加半導体薄膜を形成する事を特徴とする前記
特許請求の範囲第１項記載の薄膜電界効果トランジスタ
の製造方法。(3) The method for manufacturing a thin film field effect transistor according to claim #Il, wherein the semiconductor thin film is an amorphous or polycrystalline semiconductor. +4) The method for manufacturing a thin film field effect transistor according to claim 1, characterized in that the impurity-doped semiconductor thin film is formed from amorphous silicon of films J130 to toooX.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5142182A JPS58170065A (en) | 1982-03-31 | 1982-03-31 | Manufacture of thin film field effect transistor |
| DE8282106781T DE3279239D1 (en) | 1981-07-27 | 1982-07-27 | Thin-film transistor and method of manufacture therefor |
| EP82106781A EP0071244B1 (en) | 1981-07-27 | 1982-07-27 | Thin-film transistor and method of manufacture therefor |
| US06/779,648 US4700458A (en) | 1981-07-27 | 1985-09-24 | Method of manufacture thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5142182A JPS58170065A (en) | 1982-03-31 | 1982-03-31 | Manufacture of thin film field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58170065A true JPS58170065A (en) | 1983-10-06 |
| JPH059941B2 JPH059941B2 (en) | 1993-02-08 |
Family
ID=12886454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5142182A Granted JPS58170065A (en) | 1981-07-27 | 1982-03-31 | Manufacture of thin film field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58170065A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60192368A (en) * | 1984-03-14 | 1985-09-30 | Toshiba Corp | Manufacture of amorphous silicon semiconductor device |
| JPS60195977A (en) * | 1984-03-16 | 1985-10-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS61145818A (en) * | 1984-12-20 | 1986-07-03 | Sony Corp | Heat processing method for semiconductor thin film |
| JPS6328070A (en) * | 1986-07-21 | 1988-02-05 | Matsushita Electric Ind Co Ltd | Thin-film field-effect transistor and its manufacture |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| JP2006049577A (en) * | 2004-08-04 | 2006-02-16 | Sony Corp | Field effect transistor |
| JP2006086502A (en) * | 2004-09-15 | 2006-03-30 | Lg Philips Lcd Co Ltd | Organic thin film transistor, substrates for liquid crystal display device, and method for manufacturing the same |
| US7872263B2 (en) | 2005-09-14 | 2011-01-18 | Industrial Technology Research Institute | Substrate structure for a thin film transistor |
| JP2011035411A (en) * | 2010-10-06 | 2011-02-17 | Sony Corp | Field effect transistor |
| WO2011129227A1 (en) * | 2010-04-14 | 2011-10-20 | シャープ株式会社 | Semiconductor device, process for production of semiconductor device, and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730881A (en) * | 1980-07-31 | 1982-02-19 | Suwa Seikosha Kk | Active matrix substrate |
-
1982
- 1982-03-31 JP JP5142182A patent/JPS58170065A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730881A (en) * | 1980-07-31 | 1982-02-19 | Suwa Seikosha Kk | Active matrix substrate |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60192368A (en) * | 1984-03-14 | 1985-09-30 | Toshiba Corp | Manufacture of amorphous silicon semiconductor device |
| JPS60195977A (en) * | 1984-03-16 | 1985-10-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS61145818A (en) * | 1984-12-20 | 1986-07-03 | Sony Corp | Heat processing method for semiconductor thin film |
| JPH07118444B2 (en) * | 1984-12-20 | 1995-12-18 | ソニー株式会社 | Heat treatment method for semiconductor thin film |
| JPS6328070A (en) * | 1986-07-21 | 1988-02-05 | Matsushita Electric Ind Co Ltd | Thin-film field-effect transistor and its manufacture |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| JP2006049577A (en) * | 2004-08-04 | 2006-02-16 | Sony Corp | Field effect transistor |
| JP2006086502A (en) * | 2004-09-15 | 2006-03-30 | Lg Philips Lcd Co Ltd | Organic thin film transistor, substrates for liquid crystal display device, and method for manufacturing the same |
| US7872263B2 (en) | 2005-09-14 | 2011-01-18 | Industrial Technology Research Institute | Substrate structure for a thin film transistor |
| WO2011129227A1 (en) * | 2010-04-14 | 2011-10-20 | シャープ株式会社 | Semiconductor device, process for production of semiconductor device, and display device |
| US9035295B2 (en) | 2010-04-14 | 2015-05-19 | Sharp Kabushiki Kaisha | Thin film transistor having an oxide semiconductor thin film formed on a multi-source drain electrode |
| JP2011035411A (en) * | 2010-10-06 | 2011-02-17 | Sony Corp | Field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH059941B2 (en) | 1993-02-08 |
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