JP2003043523A - Thin film transistor panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current of a static protective element to reduce power consumption in a thin film transistor panel in which static damage to a switching element composed of a thin film transistor is prevented by a static protective element consisting of two thin film transistors connected in parallel. SOLUTION: The length P in the direction of a channel length of an overlapping area of a source electrode S of each thin film transistor 40 and a channel forming semiconductor thin film 36 via a channel protective film 37 for configuring a static protective element is longer than the length R in the direction of a channel length of an overlapping area of a drain electrode D and the channel forming semiconductor film 36 via the channel protective film 37.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor panel, and more particularly to a thin film transistor panel in which electrostatic breakdown of a switching element made of a thin film transistor is prevented by an electrostatic protection element made of a thin film transistor.

[0002]

2. Description of the Related Art In a thin film transistor panel of a liquid crystal display device, electrostatic breakdown of a switching element composed of thin film transistors respectively connected to a plurality of pixel electrodes arranged in a matrix is formed by two thin film transistors connected in parallel. There is one that is protected by an electrostatic protection element.

FIG. 8 is a partial equivalent circuit plan view of an example of such a conventional thin film transistor panel. This thin film transistor panel includes a glass substrate 1.

On the glass substrate 1, a plurality of pixel electrodes 2 arranged in a matrix, a switching element 3 formed of thin film transistors connected to each of the pixel electrodes 2, and a switching element extending in the row direction. A plurality of scanning lines 4 for supplying a scanning signal to the switching element 3, a plurality of data lines 5 extending in the column direction for supplying a data signal to the switching element 3, and a plurality of the data lines 5 extending in the row direction 2 and a plurality of auxiliary capacitance lines 6 that form an auxiliary capacitance section Cs between them.

Further, on the glass substrate 1, the short-circuit ring 7 arranged around the plurality of pixel electrodes 2 and the short-circuit ring 7 are provided.
Of the short-circuit ring 7 and the scanning line 4 outside the left side portion and the right-side portion thereof, each of which is formed of two thin film transistors, and the short-circuit ring 7.
On the outer sides of the upper side portion and the lower side portion, there are provided the short circuit ring 7 and the data line 5 and the electrostatic protection elements 9 each including two thin film transistors connected in parallel.

One end of each scanning line 4 and one end of each data line 5 are connected to connection terminals 10 and 11. in this case,
One end of the anodic oxidation power supply line 12 is connected to the connection terminal 10 connected to one end of each scanning line 4. The other end of the anodic oxidation power supply line 12 extends to the edge of the glass substrate 1. The anodic oxidation power supply line 12 is for forming an anodic oxide film on the surface of the scanning line 4 or the like. Both ends of each auxiliary capacitance line 6 are connected to the short-circuit ring 7.

Next, the operation of the electrostatic protection elements 8 and 9 of this thin film transistor panel will be described. In this case, the operations of the electrostatic protection elements 8 and 9 are the same, so the operation of the electrostatic protection element 8 will be described with reference to FIG. 9.

In FIG. 9, the electrostatic protection element 8 is composed of two thin film transistors 13 and 14 connected in parallel. The gate electrode G and the drain electrode D of one thin film transistor 13 are connected to the scanning line 4, and the source electrode S is connected to the short-circuit ring 7. The gate electrode G and the drain electrode D of the other thin film transistor 14 are connected to the short-circuit ring 7, and the source electrode S is connected to the scanning line 4.

Now, it is assumed that one scanning line 4 shown in FIG. 9 has a high potential due to static electricity. Then, one thin film transistor 13 in which the drain electrode D and the gate electrode G are connected to the scanning line 4 is turned on, a current flows from the scanning line 4 to the short-circuit ring 7, and the short-circuit ring 7 has the same potential as the scanning line 4. Become. When the short-circuit ring 7 becomes the same potential as the scanning line 4 and becomes high potential, the other thin film transistor 1 in which the drain electrode D and the gate electrode G are connected to the short-circuit ring 7
4 is turned on.

In this case, the fact that the other thin film transistor 14 is turned on means that the other thin film transistors of all the remaining electrostatic protection elements 8 shown in FIG. This means that the thin film transistor is turned on. Then, current flows from the short-circuit ring 7 to all the remaining scan lines 4 and all the data lines 5. Further, current also flows from the short-circuit ring 7 to all the auxiliary capacitance lines 6.

In this way, when any one or a plurality of scanning lines 4 are set to a high potential due to static electricity,
A current flows from the scan line 4 having the high potential to the short-circuit ring 7, all the remaining scan lines 4, all the data lines 5 and all the auxiliary capacitance lines 6, and they have the same potential and have the low potential. As a result, the electrostatic breakdown of the switching element 3 formed of a thin film transistor connected to the scanning line 4 which has a high potential due to static electricity is prevented. The same is true when any one or a plurality of data lines 5 has a high potential due to static electricity.

Next, a specific structure of the thin film transistor which constitutes the electrostatic protection elements 8 and 9 of the thin film transistor panel will be described with reference to FIGS. 10 (A) and 10 (B). For example, a gate electrode G extending from the scanning line 4 is provided at a predetermined position on the upper surface of the glass substrate 1, and a gate insulating film 15 is provided on the entire upper surface thereof.

The gate insulating film 15 on the gate electrode G
A channel forming semiconductor thin film 16 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the.
A channel protective film 17 is provided on the upper surface of the channel forming semiconductor thin film 16 substantially in the center thereof. Channel protective film 1
Ohmic contact layers 18 and 19 made of n-type amorphous silicon are provided on the upper surface of the channel forming semiconductor thin film 16 on both sides of the upper surface of the channel 7 and on both sides thereof.

A source electrode S is provided at a predetermined position on the upper surface of one ohmic contact layer 18 and the upper surface of the gate insulating film 15 in the vicinity thereof. A drain electrode D is provided at a predetermined position on the upper surface of the other ohmic contact layer 19 and the upper surface of the gate insulating film 15 in the vicinity thereof.

Then, the gate electrode G and the gate insulating film 1
5, channel forming semiconductor thin film 16, ohmic contact layers 18, 19, source electrode S and drain electrode D
Thus, the thin film transistor 20 is configured.

This thin film transistor 20 is shown in FIG.
As shown in (A) and (B), they are bilaterally symmetric, and their dimensions are, for example, a channel width W of 140 μm.
m and the channel length L is 14 μm. In this case, the channel length L is the distance Q between both electrodes S and D, and the length in the channel length direction of the overlapping region between the source electrode S and the channel forming semiconductor thin film 16 via the channel protective film 17 (hereinafter, Source electrode overlap length P) and the length in the channel length direction (hereinafter, drain electrode overlap length) R of the overlap region of the drain electrode D and the channel forming semiconductor thin film 16 via the channel protection film 17. Although the total length is obtained, the interval Q between the electrodes S and D is 6 μm, and the source electrode overlap length P and the drain electrode overlap length R are each 4 μm.

Here, for the sake of convenience, the electrostatic protection elements 8 and 9 formed by connecting two thin film transistors 20 having such a structure in parallel are referred to as a conventional TFT-parallel type element.

[0018]

By the way, the above-mentioned conventional TFT-VG (gate voltage) -ID of the parallel type element is used.
The (drain current) characteristic is, for example, as shown by the dotted line in FIG. 5, and the leakage current in the low voltage region (for example, about 10 V) is relatively large at the level of 1 × 10 −5 A, which is disadvantageous in reducing power consumption. There was a problem. An object of the present invention is to reduce leakage current of an electrostatic protection element and reduce power consumption in a thin film transistor panel including an electrostatic protection element made of a thin film transistor.

[0019]

According to a first aspect of the present invention, there is provided an electrostatic protection element comprising a thin film transistor for electrostatic breakdown of a switching element comprising a thin film transistor connected to each of a plurality of pixel electrodes arranged in a matrix. In the thin film transistor panel configured to prevent the above, the overlap region between the source electrode and the channel forming semiconductor thin film of the thin film transistor that constitutes the electrostatic protection element is larger than the overlap region between the drain electrode and the channel forming semiconductor thin film. It is characterized by that. According to a second aspect of the invention, in the first aspect of the invention, the electrostatic protection element has a configuration in which two thin film transistors each having a drain electrode connected to a gate electrode are connected in parallel. It is a feature. According to a third aspect of the present invention, in the first aspect of the present invention, a channel protective film is formed on the channel forming semiconductor thin film, and the source electrode and the drain electrode respectively include the channel. The semiconductor thin film for channel formation is polymerized through a protective film. The invention according to claim 4 is the invention according to claim 3.
In the invention described in, the ohmic contact layer is interposed between the source electrode and the channel protective film, and between the drain electrode and the channel protective film, the source electrode and the drain electrode, respectively. ,
The semiconductor thin film for channel formation is polymerized through the ohmic contact layer and the channel protective film. According to a fifth aspect of the present invention, in a thin film transistor panel, an electrostatic protection element including a thin film transistor prevents electrostatic breakdown of a switching element including a thin film transistor connected to each of a plurality of pixel electrodes arranged in a matrix. An auxiliary source electrode is connected to a source electrode of a thin film transistor which constitutes the electrostatic protection element, and the auxiliary source electrode is polymerized with a semiconductor thin film for channel formation in a region which does not polymerize with the source electrode. Is. According to a sixth aspect of the present invention, in the invention according to the third aspect, the electrostatic protection element has a configuration in which two thin film transistors each having a drain electrode connected to a gate electrode are connected in parallel. It is a feature. The invention according to claim 7 is the invention according to claim 6, wherein the auxiliary source electrode is provided on an overcoat film provided so as to cover the electrostatic protection element and the switching element. It is characterized by. The invention according to claim 8 is the invention according to claim 7, characterized in that the auxiliary source electrode is formed of the same material as the pixel electrode provided on the overcoat film. It is a thing. Further, according to the present invention, a substantial overlapping region of the source electrode and the channel forming semiconductor thin film of the thin film transistor which constitutes the electrostatic protection element is made larger than an overlapping region of the drain electrode and the channel forming semiconductor thin film. Therefore, the leakage current of the electrostatic protection element can be reduced and the power consumption can be reduced as compared with the conventional case that is symmetrical.

[0020]

1 is a plan view of an equivalent circuit of a part of a thin film transistor panel according to a first embodiment of the present invention. The thin film transistor panel includes a glass substrate 21.

A plurality of pixel electrodes 22 arranged in a matrix on the glass substrate 21 and the pixel electrodes 22.
And a plurality of scanning lines 24 extending in the row direction for supplying a scanning signal to the switching elements 23.
A plurality of data lines 25 extending in the column direction for supplying a data signal to the switching element 23 and a plurality of data lines 25 extending in the row direction to form the auxiliary capacitance portion Cs between the pixel electrode 22 and the plurality of data lines 25. An auxiliary capacitance line 26 is provided.

Further, on the glass substrate 21, the short-circuit ring 27 arranged around the plurality of pixel electrodes 22, and the short-circuit ring 27 and the scanning line 24 outside the left side portion and the right side portion of the short-circuit ring 27, respectively. 2 each connected in parallel
Electrostatic protection element 28 consisting of individual thin film transistors
And an electrostatic protection element 29 composed of two thin film transistors each connected in parallel to the short circuit ring 27 and the data line 25 outside the upper side and the lower side of the short circuit ring 27.

One end of each scanning line 24 and each data line 25
One end of is connected to the connection terminals 30 and 31. In this case, one end of the anodic oxidation power supply line 32 is connected to the connection terminal 30 connected to one end of each scanning line 24. The other end of the anodic oxidation power supply line 32 extends to the edge of the glass substrate 21. The anodic oxidation power supply line 32 is for forming an anodic oxide film on the surface of the scanning line 24 and the like. Both ends of each auxiliary capacitance line 26 are connected to a short circuit ring 27.

Next, the operation of the electrostatic protection elements 28 and 29 of this thin film transistor panel will be described. In this case, the operations of the electrostatic protection elements 28 and 29 are the same,
The operation of the electrostatic protection element 28 will be described with reference to FIG.

In FIG. 2, the electrostatic protection element 28 is composed of two thin film transistors 33 and 34 connected in parallel. Gate electrode G of one thin film transistor 33
The drain electrode D is connected to the scanning line 24, and the source electrode S is connected to the short-circuit ring 27. The gate electrode G and the drain electrode D of the other thin film transistor 34
Is connected to the short circuit ring 27, and the source electrode S is connected to the scan line 2
4 is connected.

Now, it is assumed that one scanning line 24 shown in FIG. 2 has a high potential due to static electricity. Then, one thin film transistor 33 whose drain electrode D and gate electrode G are connected to the scanning line 4 is turned on, and the scanning line 24
Causes a current to flow in the short-circuit ring 27, and the short-circuit ring 27 has the same potential as the scanning line 24. The short-circuit ring 27 is the scanning line 24.
When the potential becomes the same as the above and becomes a high potential, the other thin film transistor 34 in which the drain electrode D and the gate electrode G are connected to the short-circuit ring 7 is turned on.

In this case, the fact that the other thin film transistor 34 is turned on means that the other thin film transistors of all the remaining electrostatic protection elements 8 and the other of all the other electrostatic protection elements 9 shown in FIG. This means that the thin film transistor is turned on. Then, current flows from the short-circuit ring 27 to all the remaining scan lines 24 and all the data lines 25. Further, current also flows from the short-circuit ring 27 to all the auxiliary capacitance lines 26.

In this way, when any one or a plurality of scanning lines 24 have a high potential due to static electricity, the short-circuit ring 2 is moved from this high potential scanning line 24.
7, all remaining scan lines 24, all data lines 25
And a current flows through all of the auxiliary capacitance lines 26, and they have the same potential and a low potential. As a result, electrostatic breakdown of the switching element 3 composed of a thin film transistor connected to the scanning line 24 which has been set to a high potential due to static electricity is prevented. The same is true when any one or a plurality of data lines 25 has a high potential due to static electricity.

Next, a specific structure of the thin film transistor which constitutes the electrostatic protection elements 28 and 29 of the thin film transistor panel will be described with reference to FIGS. 3 (A) and 3 (B). A gate electrode G extending from, for example, the scanning line 24 is provided at a predetermined position on the upper surface of the glass substrate 21, and a gate insulating film 35 is provided on the entire upper surface thereof.

The gate insulating film 35 on the gate electrode G
A channel forming semiconductor thin film 36 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the.
A channel protective film 37 is provided on a substantially central portion of the upper surface of the semiconductor thin film 36 for channel formation. Channel protective film 3
Ohmic contact layers 38 and 39 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel 7 and on the upper surface of the channel forming semiconductor thin film 36 on both sides thereof.

In this case, the gate electrode G, the channel forming semiconductor thin film 36 and the channel protective film 37 are formed as shown in FIG.
As shown in (A) and (B), it is symmetrical. However, the length P in the channel length direction of the region where one of the ohmic contact layers 38 overlaps with the channel protective film 37 is determined by the length P of the other ohmic contact layer 39.
It is longer than the length R of the overlapping region with the channel length direction. Therefore, both ohmic contact layers 38, 39
Is asymmetric.

A source electrode S is provided at a predetermined position on the upper surface of one ohmic contact layer 38 and the upper surface of the gate insulating film 35 in the vicinity thereof. A drain electrode D is provided at a predetermined position on the upper surface of the other ohmic contact layer 39 and the upper surface of the gate insulating film 35 in the vicinity thereof. Although not shown in FIGS. 3A and 3B, the drain electrode D is electrically connected to the gate electrode G by the wiring as described above.

In this case, since the ohmic contact layers 38 and 39 are asymmetrical to each other as described above, the source electrode S and the channel forming semiconductor thin film 36 are overlapped with each other through the channel protective film 37 in the channel length direction of the overlapping region. (Hereinafter, the source electrode polymerization length) P is the length in the channel length direction of the polymerization region of the drain electrode D and the channel forming semiconductor thin film 36 through the channel protective film 37 (hereinafter, the drain electrode polymerization length). Length) is longer than R.

Then, the gate electrode G and the gate insulating film 3
5, semiconductor thin film 36 for channel formation, ohmic contact layers 38, 39, source electrode S and drain electrode D
Thus, the thin film transistor 40 is configured.

This thin film transistor 40 is shown in FIG.
And as shown in (B), it is asymmetrical,
Its dimensions are: channel width W is 140 μm, channel length L
Is 14 μm, which is the same as the conventional type in this respect.

Here, the distance Q between the electrodes S and D is set to 6 μm, which is the same as in the conventional type, and the source electrode overlap length P and the drain electrode overlap length R are changed so that the drains of two thin film transistors connected in parallel. When 10 V was applied to the electrode D and 0 V was applied to each source electrode S, the relationship between the source electrode overlap length P and the drain current ID was examined, and the results shown in FIG. 4 were obtained.

FIG. 4 shows that the source electrode polymerization length P is 3.5 μm.
It shows the drain current ID (μA) in the case of changing from m to 5.0 μm (in this case, the drain electrode superposition length R changes from 4.5 μm to 3 μm), which is clear from the figure. Moreover, the drain current ID decreases as the source electrode overlap length P increases. For example, the drain current ID is 6 μA or more when the source electrode overlap length P is about 4 μm, while the source electrode overlap length P is 5 μA.
When it is about m, it is slightly less than 4 μA.

In the case of the conventional TFT-parallel type device shown in FIGS. 10A and 10B, the source electrode overlap length P is 4 .mu.m. As shown, low voltage region (for example, about 10V)
The leakage current in 1 is relatively large at 1 × 10 −5 A level, which is disadvantageous in reducing power consumption.

On the other hand, in the case of this embodiment shown in FIGS. 3A and 3B, the source electrode polymerization length P is 5
Since it is relatively long at μm, the leakage current in the low voltage region (for example, about 10 V) is in the order of 1 × 10 −6 A, which is smaller than that of the conventional TFT-parallel device shown by the dotted line in FIG. Power consumption can be reduced as compared to the case of a TFT-parallel type device.

In the case of this embodiment shown by the solid line in FIG. 5, the leakage current in the high voltage region (for example, about 40 V) is the conventional TF shown by the dotted line in FIG.
Although slightly smaller than the case of the T-parallel type element, it is sufficient as a countermeasure against static electricity.

Here, in the case of this embodiment shown in FIGS. 3A and 3B, compared with the case of the conventional TFT-parallel type device shown in FIGS. 10A and 10B. , Consider that leakage current can be reduced.

A back gate effect is generated in the semiconductor thin film 38 for channel formation by the source electrode S provided on the channel protective film 37. For example, when the gate voltage VG = drain voltage VD = 10V and the source voltage VS = 0V, the source electrode S acts in the direction of canceling the channel generated in the channel forming semiconductor thin film 38 with the gate electrode G of 10V and 0V. Therefore, when the source electrode superposition length P is made longer than the drain electrode superposition length R, the superposition region (area) of the source electrode S and the channel forming semiconductor thin film 36 becomes the drain electrode D and the channel forming semiconductor thin film 36.
The area becomes larger than the overlapping area (area) with the back gate effect, the back gate effect is increased, and the leak current is reduced.

Next, FIG. 6 shows a transparent plan view of a specific structure of a thin film transistor which constitutes an electrostatic protection element according to a second embodiment of the present invention, and FIG. 7 shows a sectional view taken along the line AA. It is shown. In these figures, FIG.
Those having the same names as those shown in (A) and (B) are designated by the same reference numerals, and the description thereof will be appropriately omitted.

The thin film transistor 40 of this embodiment is
It is a channel etch type, has no channel protective film, and has a recess 41 in the center of the upper surface of the channel forming semiconductor thin film 36.
Are formed. Further, in this embodiment, the overcoat film 42 made of silicon nitride is formed on the entire upper surface of the gate insulating film 35 including the thin film transistor 40 and the like.

Although not shown, the drain electrode D in this embodiment is also similar to the first embodiment.
And the gate electrode G are electrically connected by a wiring. However, in the first embodiment, the source electrode overlap length P is set longer than the drain electrode overlap length R.
In this embodiment, the source electrode overlap length P is the same as the drain electrode overlap length R. Instead, an auxiliary source electrode 43 is provided on the upper surface of the overcoat film 42 so as to be connected to the source electrode S via a contact hole 44 formed in the overcoat film 42.

The auxiliary source electrode 43 is formed in substantially the same area as the source electrode S in plan view, but the end portion on the side facing the drain electrode D is to some extent more than the end portion on the same side of the source electrode S. For example, the protrusion is about 1 to 2 μm. As a result, the auxiliary source electrode 43 becomes the source electrode S.
Semiconductor thin film 3 for forming a channel in a region that does not overlap with
It has been polymerized with 6.

In this case, since the auxiliary source electrode 43 is connected to the source electrode S, it is substantially the source electrode S.
Is the same as. Then, in the region of the auxiliary source electrode 43 that does not overlap with the source electrode S, the same region as that of the first embodiment can be obtained by the overlap region where the channel forming semiconductor thin film 36 overlaps.

By the way, the overcoat film 4 shown in FIG.
Although not shown, the pixel electrode 22 shown in FIG. 1 is formed of ITO at a predetermined position on the upper surface of 2. In this case, although not shown, the pixel electrode 22 is connected to the source electrode S through a contact hole formed in the overcoat film 42. Therefore, if the auxiliary source electrode 43 is formed of the same material (ITO) as the pixel electrode 22, the number of manufacturing steps can be prevented from increasing.

In the above embodiment, the case where the electrostatic protection elements 28 and 29 are provided outside the short-circuit ring 27 as shown in FIG. 1 has been described, but the present invention is not limited to this, and although not shown. The electrostatic protection elements 28 and 29 are connected to the short circuit ring 27.
It may be provided inside.

[0050]

As described above, according to the present invention, the substantial overlapping region of the source electrode and the channel forming semiconductor thin film of the thin film transistor which constitutes the electrostatic protection element is the drain electrode and the channel forming semiconductor thin film. Since the area is larger than the overlapping area with, the leakage current of the electrostatic protection element can be reduced and the power consumption can be reduced as compared with the conventional case which is symmetrical.

[Brief description of drawings]

FIG. 1 is an equivalent circuit plan view of a part of a thin film transistor panel according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit plan view for explaining the operation of the electrostatic protection element shown in FIG.

3A is a plan view of a specific structure of a thin film transistor that constitutes the electrostatic protection element shown in FIG. 1, and FIG. 3B is a sectional view taken along line BB thereof.

4 is a diagram of a source electrode and a channel forming semiconductor thin film of the thin film transistor shown in FIG.

5 is a diagram showing VG-ID characteristics of the thin film transistor shown in FIG.

FIG. 6 is a transparent plan view of a specific structure of a thin film transistor that constitutes an electrostatic protection element according to a second embodiment of the present invention.

7 is a sectional view taken along the line AA of FIG.

FIG. 8 is a partial equivalent circuit plan view of an example of a conventional thin film transistor panel.

9 is a plan view of an equivalent circuit shown for explaining the operation of the electrostatic protection element shown in FIG.

10A is a plan view of a specific structure of a thin film transistor that constitutes the electrostatic protection element shown in FIG. 9, and FIG. 10B is a sectional view taken along line BB thereof.

[Explanation of symbols]

21 glass substrate 22 Pixel electrode 23 Switching element 24 scan lines 25 data lines 26 Auxiliary capacitance line 27 short-circuit ring 28, 29 Electrostatic protection element 36 channel forming semiconductor thin film 40 thin film transistor G gate electrode S source electrode D drain electrode

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2H092 JB42 JB69 JB79 NA26                 5F110 AA06 AA09 AA22 BB01 CC07                       DD02 EE30 GG02 GG15 GG22                       GG28 GG29 GG35 GG60 HK09                       HK16 HL07 HM02 HM12 NN02                       NN12 NN24 NN73

Claims (8)

[Claims] 1. A thin film transistor panel in which an electrostatic protection element formed of a thin film transistor prevents electrostatic breakdown of a switching element formed of a thin film transistor connected to each of a plurality of pixel electrodes arranged in a matrix. A thin film transistor panel, wherein a region where a source electrode of a thin film transistor which constitutes a protection element and a semiconductor thin film for channel formation overlap is larger than a region where a drain electrode overlaps with the semiconductor thin film for channel formation. 2. The thin film transistor according to claim 1, wherein the electrostatic protection element has a configuration in which two thin film transistors each having a drain electrode connected to a gate electrode are connected in parallel. panel. 3. The invention according to claim 1, wherein a channel protective film is formed on the semiconductor thin film for channel formation, and the source electrode and the drain electrode are respectively provided with the channel protective film interposed therebetween. A thin film transistor panel characterized by being superposed on the channel forming semiconductor thin film. 4. The invention according to claim 3, wherein an ohmic contact layer is interposed between the source electrode and the channel protective film and between the drain electrode and the channel protective film, The thin film transistor panel, wherein the electrode and the drain electrode are polymerized on the channel forming semiconductor thin film through the ohmic contact layer and the channel protective film, respectively. 5. A thin film transistor panel in which an electrostatic protection element formed of a thin film transistor prevents electrostatic breakdown of a switching element formed of a thin film transistor connected to each of a plurality of pixel electrodes arranged in a matrix. A thin film transistor panel, wherein an auxiliary source electrode is connected to a source electrode of a thin film transistor which constitutes a protection element, and the auxiliary source electrode is polymerized with a channel forming semiconductor thin film in a region which does not overlap with the source electrode. 6. The thin film transistor according to claim 5, wherein the electrostatic protection element has a configuration in which two thin film transistors each having a drain electrode connected to a gate electrode are connected in parallel. panel. 7. The invention according to claim 6, wherein the auxiliary source electrode is provided on an overcoat film provided so as to cover the electrostatic protection element and the switching element. Thin film transistor panel. 8. The thin film transistor panel according to claim 7, wherein the auxiliary source electrode is formed of the same material as the pixel electrode provided on the overcoat film.