KR100701068B1 - Pixel structure of fringe field switching mode liquid crystal display - Google Patents

Abstract

The present invention forms a capacitance at a shield layer position to prevent light leakage due to data signal voltage while changing the shape of the barrier layer at a common electrode while preventing the aperture ratio from affecting the gate common short (GCS). The present invention relates to a pixel structure of an FPS mode liquid crystal display device capable of reducing the number of pixels, and includes a gate line, a common line, and first and second ITO electrodes. In the pixel structure, a common electrode formed at a center position of the pixel electrode and smaller than the width of the upper ITO electrode, a blocking layer formed close to the gate as a source / drain layer, and the common electrode and the pixel electrode protrude from each other. To increase the overlap area, and at the same time storage capacitors (Storage Ca) pacitor, which is formed by forming a pacitor. In the case of flat panel switching (InPlane Switching) of a TFT LCD, when the common electrode is located in the center of the pixel in the FFS structure, the decrease in the aperture ratio caused to form the storage capacitor is reduced, thereby reducing the decrease in luminance. There is.

Description

Pixel structure of fs mode liquid crystal display device {PIXEL STRUCTURE OF FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY}

1 is a plan view showing a pixel structure of a conventional fs mode liquid crystal display device.

Fig. 2 is a cross-sectional view showing a TFT and a pixel region of a fs mode liquid crystal display device.

3 is a plan view showing a pixel structure of a F-S mode liquid crystal display device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10 gate line 12 data line

50: hole 126: blocking layer

140: common line 142: common electrode

The present invention relates to a pixel structure of a F-S mode liquid crystal display device, and more particularly, to form a capacitance at a location of a blocking layer that does not affect the aperture ratio, and to change the shape of the blocking layer at a common electrode to obtain a gate common short (GCS). The present invention relates to a pixel structure of a fs mode liquid crystal display device which can be reduced.

The present invention can be applied to the field of LCD (Liquid Crystal Display), the method of positioning the common electrode in the center of the pixel to reduce the gate common short (GCS) in the FFS (Fringe Field Switch) structure has a problem that the luminance is caused.

FIG. 1 is a plan view showing a pixel structure of a conventional FPS mode liquid crystal display device. As shown in FIG. 1, a FFS (Fringe Field Switching) structure has a conventional same layer and a GCS due to a process defect when a gate and a common electrode are adjacent to each other. Since a lot (Gate Common Short) occurs, the common electrode 14 is positioned in the center of the pixel in order to improve it.

However, in this technology, since the common electrode 14 and the pixel electrode 24 overlap with each other in order to form a storage capacitor, the metal electrode and the pixel electrode in the pixel overlap and do not transmit light. There was a problem that there is an area that can not be reduced because the luminance is inevitable. In addition, since the shield bar 26 for preventing light leakage due to the data signal voltage is close to the gate electrode as in the conventional FFS structure, there is a high possibility of generating GCS due to gate retention. Have.

An object of the present invention is to solve the problems in the conventional liquid crystal display device as described above, by forming a capacitance at the position of the blocking layer does not affect the opening ratio and by changing the shape of the blocking layer in the common electrode GCS (Gate) In order to reduce the common short), the present invention provides a pixel structure of a F-S mode liquid crystal display device.

According to a preferred embodiment of the present invention for achieving the above object, the FPS mode or InPlane Switching mode of the liquid crystal display device including a gate line, a common line and the first and second ITO electrode In the pixel structure,

A common electrode formed at a center position of the pixel electrode and smaller than the width of the upper ITO electrode, a blocking layer formed close to the gate as a source / drain layer, and the common electrode and the pixel electrode are formed to protrude from each other to increase an overlap area; And a storage capacitor formed at both the left and right sides of the blocking layer at the same time, thereby providing a pixel structure of an FSF mode liquid crystal display device.

In addition, in the present invention, the common electrode is separated from the gate, the blocking layer is characterized in that formed in a wide pattern, e.

In addition, in the present invention, in order to reduce the capacitance value formed by overlapping the common electrode and the data line between the insulating film, the shape of the common electrode has a structure in which a hole is formed in the center of the box to reduce the area. .

The characteristics of the pixel structure of the FSF mode liquid crystal display device according to the present invention are enumerated. First, when the common capacitor is positioned in the pixel by changing the storage capacitor formation position, the aperture ratio is reduced, thereby affecting the aperture ratio in order to reduce the luminance decrease. Capacitance was formed at the gate shield bar positions that do not apply.

Second, the GCS was reduced by changing the shape of the blocking layer in the common electrode.

Third, because the gate bar is short, the barrier layer may not function as a blocking layer, and thus, a floating layer / drain metal is used to form a blocking layer for preventing light leakage.

Fourth, the capacitance value generated in the data line was reduced by reducing the overlap between the common electrode and the data line.

FIG. 2 is a cross-sectional view illustrating TFTs and pixel regions of the FSF mode liquid crystal display device. As shown therein, a gate metal 2 formed on the glass substrate 1 and a SiONx layer 3 serving as a first insulating layer are shown. And a SiNx layer 4 as a second insulating layer, an a-Si layer 5 and an n + a-Si layer 6, and a source / drain electrode layer 7 is formed. Reference numeral 8 denotes a passivation layer, in which a thin film transistor portion is formed. In addition, the common data line portion includes a first indium tin oxide (ITO) 22 formed on the glass substrate 1, a common gate line 14 formed thereon, and a SiONx layer 3 formed thereon, and then blocked. Layer 26 is formed and second ITO layer 24 is formed. This common data line portion is a portion related to the present invention.

FIG. 3 is a plan view illustrating a pixel structure of a F-S mode liquid crystal display device according to the present invention, and is similar to FIG. 1.

First, in the present invention, since the common electrode serves as a reference of the data voltage, the width of the common electrode 142 may be reduced because a DC bias is not applied and thus is not significantly affected by the resistance value. On the other hand, the small area leads to insufficient charging capacity. This is overlapped between the pixel electrode 24 and the common electrode line 140 at the location of the blocking layer 126 next to the data line 12 which is generally used to prevent light leakage in order to secure this to obtain a sufficiently large storage capacitor capacity. By increasing the area, a storage capacitor was formed to secure the reduction of the aperture ratio.

Secondly, the metal blocking layer formed during the formation of the gate thin film is generally formed in an H shape to prevent light leakage caused by driving liquid crystal present in adjacent pixel electrodes by data voltage. However, if the blocking layer is formed to be close to the gate as in the conventional technique, to reduce the possible light leakage, the probability of generating GCS increases even if the common electrode is placed in the center of the pixel. Therefore, in the present invention, the common metal blocking layer 126 is designed to be short, and instead of the H-shape having a thin pattern, a K-shape is formed to favor pattern defects, thereby reducing GCS that may be generated by photolithography or etching defects. In addition, instead of the common electrode, the source / drain metal may be used to form the blocking layer 126 close to the gate to effectively reduce light leakage.

Thirdly, a large overlap area between the common metal and the data line is not desirable because the capacitance value increases, resulting in a large RC delay of the signal. In addition, there is a disadvantage in that the data repair area is reduced and the data driving voltage is increased. In order to improve this, the hole 50 is formed in the center of the common line electrode overlapping the data line, thereby effectively reducing the overlap between the common electrode 140 and the data signal line 12, thereby reducing unwanted capacitance components.

In FIG. 3, the area of the common electrode for forming the storage capacitor is larger than that of the pixel electrode and the width of the data line 12 is reduced like the dotted line in an area where the width of the data line 12 overlaps with the common line (12-1).

Therefore, according to the pixel structure of the FPS mode liquid crystal display device according to the present invention, the aperture ratio caused to form the storage capacitor when the common electrode is located in the center of the pixel in the InPlane Switching, FFS structure of the TFT LCD There is an effect of reducing the decrease in the luminance decreases.

In addition, the storage capacitor may be formed in a position where the blocking layer is next to the data signal line rather than in the center of the pixel electrode, thereby forming a storage capacitor having a large capacity.

In addition, the GCS formed by attaching a blocking layer to a gate, such as a gate, can be reduced, so that an improvement in yield can be expected without the need for interlayer insulation or a special process.

In addition, to reduce light leakage, the floating metal is formed like a data line in a source / drain process to serve as a blocking layer. As a result, the source / drain blocking layer can be formed closely regardless of the gate line, thereby effectively reducing light leakage.

In addition, by forming a ㅁ, ㅇ, ㅍ with a large surface instead of the conventional H-shaped gate blocking layer, it can reduce the pattern defects that can be caused by photolithography and etching defects at the end of the thin pattern, thereby effectively reducing the GCS It can be effective.

In addition, by reducing the overlapping area between the common electrode and the data line, the parasitic capacitance value of the data line can be reduced to reduce the RC delay.

In addition, preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, modifications and the like are within the scope of the claims It should be seen as belonging.

Claims (3)

In the pixel structure of the FPS mode or InPlane Switching mode liquid crystal display device including a gate line, a common line and the first and second ITO electrodes, A common electrode formed at a center position of the pixel electrode and smaller than the width of the upper ITO electrode, a blocking layer formed close to the gate as a source / drain layer, and the common electrode and the pixel electrode are formed to protrude from each other to increase an overlap area; And a storage capacitor formed at both the left and right sides with the blocking layer at the same time. The pixel structure of an FSF mode liquid crystal display device according to claim 1, wherein the common electrode is spaced apart from the gate, and the blocking layer is formed in a wide pattern such as. The method of claim 1, wherein the common electrode has a structure in which a hole is formed in the center of the common electrode to reduce the capacitance value formed by overlapping the common electrode and the data line between the insulating layers, thereby reducing the area. Pixel Structure of FSF Mode Liquid Crystal Display Device.

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