CN110993696B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN110993696B
CN110993696B CN201911139682.3A CN201911139682A CN110993696B CN 110993696 B CN110993696 B CN 110993696B CN 201911139682 A CN201911139682 A CN 201911139682A CN 110993696 B CN110993696 B CN 110993696B
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bump
thickness
metal layer
semiconductor device
layer
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CN110993696A (en
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李文荣
赖君伟
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AU Optronics Corp
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AU Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Abstract

The invention discloses a semiconductor device, which comprises a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer and a second metal layer. The first metal layer is disposed on the substrate. The first bump is disposed on the substrate, and a first portion of the first metal layer partially covers an upper surface of the first bump. The insulation layer covers the first part of the first metal layer and the local upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is disposed on the semiconductor layer.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
Semiconductor devices are widely used in consumer electronics such as cell phones, notebook computers, digital cameras, and the like. The semiconductor devices are, for example, thin film transistors (thin film transistor, TFT) which can be disposed on display panels, such as liquid crystal displays (liquid crystal displays, LCD) and organic electroluminescent displays (Organic Electroluminesence Display, OELD or OLED), so that the display panels have advantages of light weight and low power consumption, and thus the thin film transistor display panels are becoming mainstream goods in the market.
In general, thin film transistors include top-gate thin film transistors (top-gate TFTs) and bottom-gate thin film transistors (bottom-gate TFTs). The thin film transistor includes a semiconductor layer as an active layer or a channel layer, and thus, when irradiated with an external light source (for example, a backlight), the semiconductor layer of the TFT is liable to cause a leakage current (photo-induced current leakage) due to light. In this case, the leakage current caused by light not only affects the performance of the thin film transistor device itself, but also causes a problem of crosstalk (cross-talk) during the display of the picture, which results in a decrease in the display quality of the display. In addition, after the light passes through the TFT substrate, a part of the light may be reflected by the upper substrate and absorbed by the semiconductor layer or may reach the semiconductor layer of the TFT through other paths, which needs to be improved.
Disclosure of Invention
The invention relates to a semiconductor device for improving the performance of the semiconductor device.
According to an aspect of the present invention, a semiconductor device is provided, which includes a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer, and a second metal layer. The first metal layer is disposed on the substrate. The first bump is disposed on the substrate, wherein a first portion of the first metal layer partially covers an upper surface of the first bump. The insulation layer covers the first part of the first metal layer and the local upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is disposed on the semiconductor layer.
For a better understanding of the above and other aspects of the invention, reference will now be made in detail to the following examples, examples of which are illustrated in the accompanying drawings:
drawings
FIG. 1A is a schematic plan view of a pixel structure according to an embodiment of the invention;
FIG. 1B is an enlarged schematic view of a semiconductor device according to an embodiment of the present invention in the pixel structure of FIG. 1A;
FIG. 1C is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the I-I section line of FIG. 1B;
FIG. 2A is a schematic plan view of a pixel structure according to an embodiment of the invention;
FIG. 2B is an enlarged schematic view of a semiconductor device according to an embodiment of the present invention in the pixel structure of FIG. 2A;
FIG. 2C is a schematic cross-sectional view of a semiconductor device along the I-I section line of FIG. 2B according to one embodiment of the present invention;
fig. 3A and 3B are an enlarged schematic view and a cross-sectional schematic view of a semiconductor device according to another embodiment of the invention;
fig. 4A and 4B are an enlarged schematic view and a cross-sectional schematic view of a semiconductor device according to another embodiment of the invention;
FIG. 5 is a schematic view showing the semiconductor layer blocked by the first metal layer after being raised to reduce the percentage improvement of the light absorption according to another embodiment of the present invention;
FIG. 6 is a schematic diagram showing the decrease of the light absorption of the semiconductor layer in FIG. 5 with the increase of the height of the first metal layer after the pad height.
Symbol description
T: thin film transistor
G: grid electrode
GI: gate insulating layer
AS: semiconductor layer
S: source electrode
D: drain electrode
100A, 100B: pixel structure
101: substrate board
102: scanning line
103: common line
104: data line
105: pixel electrode
110A, 110B, 110C, 110D: semiconductor device with a semiconductor device having a plurality of semiconductor chips
111: a first metal layer
111a: first part
111b: extension part
112: first bump
113: insulating layer
114: semiconductor layer
115: second metal layer
117: second bump
S1, S2 and S3: upper surface of
OA, OA1, OA2: open area
B: light ray
H1: first thickness of
H2: second thickness of
And H3: third thickness of
H4: fourth thickness of
L: length of
Detailed Description
The following examples are presented for illustrative purposes only and are not intended to limit the scope of the invention. The following description will be given with the same/similar symbols indicating the same/similar elements. The directional terms mentioned in the following embodiments are, for example: upper, lower, left, right, front or rear, etc., are merely references to the directions of the accompanying drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the invention.
According to an embodiment of the present invention, a semiconductor device is provided to avoid the problem of leakage current generated by the semiconductor layer due to light. As shown in fig. 1A and 2A, the semiconductor device is, for example, a thin film transistor T or an active/switching element, the thin film transistor T is disposed on a substrate 101, the substrate 101 is, for example, glass, quartz, an organic polymer, or other applicable materials, and the substrate 101 has light transmittance, so that the backlight source can pass through the substrate 101. In one embodiment, the thin film transistor T includes a gate electrode G, a gate insulating layer GI, a semiconductor layer AS, an ohmic contact layer, a source electrode S and a drain electrode D. The gate electrode G, the scan line 102, and the common line 103 may be formed on the substrate 101. The materials of the gate electrode G, the scan line 102, and the common line 103 may include a metal, a metal oxide, an organic conductive material, or a combination thereof. The scan line 102 is electrically connected to the gate electrode G, and the scan line 102 and the common line 103 are separated from each other. Next, a gate insulating layer GI is formed on the substrate 101, and the gate insulating layer GI is disposed on the gate electrode G, wherein a material of the gate insulating layer GI includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride), an organic material, or other suitable materials. Further, a semiconductor layer AS is formed on the gate insulating layer GI. The semiconductor layer AS may be a metal Oxide semiconductor, polysilicon, amorphous silicon, or other suitable semiconductor material, for example, indium-Gallium-Zinc Oxide (IGZO), zinc Oxide (ZnO), tin Oxide (SnO), indium-Zinc Oxide (IZO), gallium-Zinc Oxide (GZO), zinc-Tin Oxide (ZTO) or Indium-Tin Oxide (ITO), etc. Then, an ohmic contact layer is formed on the semiconductor layer AS, and the ohmic contact layer exposes a portion of the semiconductor layer AS. The ohmic contact layer may be a dopant-containing metal oxide semiconductor material, a dopant-containing polysilicon, a dopant-containing amorphous silicon, or other suitable dopant-containing semiconductor material. Next, the data line 104 is formed on the substrate 101, and the source S and the drain D are formed on the ohmic contact layer, so that the thin film transistor T can be formed in a pixel structure 100A of the display panel and electrically connected to the pixel electrode 105, as shown in fig. 1A and 2A.
Referring to fig. 1A and 2A, the scan line 102 and the data line 104 are respectively located at different layers, and an insulating layer (e.g., a gate insulating layer GI) is sandwiched between them, and the common line 103 and the data line 104 are respectively located at different layers, and an insulating layer (e.g., a gate insulating layer GI) is sandwiched between them. The extending direction of the scan line 102 is different from the extending direction of the data line 104, and preferably, the extending direction of the scan line 102 is perpendicular to the extending direction of the data line 104, but the invention is not limited thereto.
In this embodiment, in order to solve the problem of leakage current, the height of the gate G (hereinafter referred to AS the first metal layer 111) can be relatively higher than or equal to the height of the gate insulating layer GI (hereinafter referred to AS the insulating layer 113) covering the gate G through the bump for raising, so that the light incident from the side surface of the gate G at the predetermined angle is reflected by the raised gate G and is far away from the semiconductor layer AS above the gate insulating layer GI, and thus the problem of leakage current caused by the semiconductor layer AS (hereinafter referred to AS the semiconductor layer 114) being irradiated by light can be effectively solved.
Referring to fig. 1B and 1C, fig. 1B is an enlarged schematic view of a semiconductor device 110A in the pixel structure 100A of fig. 1A, and fig. 1C is a schematic cross-sectional view of the semiconductor device 110A along the section line I-I of fig. 1B. The semiconductor device 110A includes a substrate 101, a first metal layer 111, a first bump 112, an insulating layer 113, a semiconductor layer 114, and a second metal layer 115. The first metal layer 111 is disposed on the substrate 101. The first bump 112 is disposed on the substrate 101, wherein a first portion 111a of the first metal layer 111 partially covers the upper surface S1 of the first bump 112. The insulating layer covers the first portion 111a of the first metal layer 111 and the partial upper surface S1 of the first bump 112. The semiconductor layer 114 is disposed on the insulating layer 113. The second metal layer 115 is disposed on the semiconductor layer 114. The second metal layer 115 may include a source S and a drain D.
In an embodiment, the first metal layer 111 and the first bump 112 are disposed on the substrate 101, for example, the first bump 112 is formed on the substrate 101, and then the first metal layer 111 is formed on the substrate 101 and a portion of the first bump 112. Since the first metal layer 111 covers only a portion of the upper surface S1 of the first bump 112, the first portion 111a of the first metal layer 111 and a portion of the first bump 112 overlap each other, and the first metal layer 111 further has an extension portion 111b extending along the upper surface S2 of the substrate 101, a length L of the extension portion 111b is at least greater than a length of the first portion 111a overlapping the first bump 112, for example, the length L of the extension portion 111b is 3 times, 4 times, or more the length of the first portion 111 a.
In addition, since the first metal layer 111 covers only a portion of the upper surface S1 of the first bump 112, the first bump 112 extends out of one side of the first metal layer 111 opposite to the extension portion 111b, for example, the first bump 112 is located on the opening area OA of the substrate 101 (i.e. the opening area not covered by the first metal layer 111). When the first bump 112 is made of a light-transmissive material, the first bump 112 covers the opening area and does not affect the opening ratio of the substrate 101, so the first bump 112 is preferably made of a light-transmissive material, but the invention is not limited thereto.
In an embodiment, when the light B incident at a predetermined angle passes through the substrate 101 from the opening area OA of the substrate 101, the light B can pass through the first bump 112 and the insulating layer 113 or enter the first bump 112 and the insulating layer 113, but the light B is still blocked by the raised first metal layer 111 because the first bump 112 and the insulating layer 113 are made of light-transmissive materials. Therefore, after the first portion 111a of the first metal layer 111 is lifted by the first bump 112, a light blocking wall (i.e. a bump) is formed to block the light B entering the semiconductor device 110A through the insulating layer 113, and also block the light reflected into the semiconductor device 110A through the upper plate (e.g. a color filter), so as to reduce the leakage current. In another embodiment, if the first bump 112 made of opaque material is selected without considering the influence on the aperture ratio of the substrate 101, the light B can be blocked by the first bump 112.
In an embodiment, the first bump 112 has a first material, and the first metal layer 111 has a second material, and the first material is different from the second material. That is, the first bump 112 and the first metal layer 111 are not made of the same material. The first bump 112 may be made of a transparent material, a non-transparent material, a metal material, an organic dielectric material (e.g. a polymer material such as a resin), or an inorganic dielectric material (e.g. silicon oxide, silicon nitride, silicon oxynitride, etc.). The first metal layer 111 may be made of metal, metal oxide, organic conductive material or other suitable materials.
Referring to fig. 1C, the first bump 112 has a first thickness H1, the insulating layer 113 has a second thickness H2, the first portion 111a of the first metal layer 111 has a third thickness H3, and an extension portion 111b of the first metal layer 111 has a fourth thickness H4. The first thickness H1 refers to a vertical distance between the upper surface S1 of the first bump 112 and the upper surface S2 of the substrate 101, the second thickness H2 refers to a vertical distance between the upper surface of the insulating layer 113 and the upper surface of the extension portion 111b of the first metal layer 111, the third thickness H3 refers to a vertical distance between the upper surface of the first portion 111a of the first metal layer 111 and the upper surface S1 of the first bump 112, and the fourth thickness H4 refers to a vertical distance between the upper surface of the extension portion 111b of the first metal layer 111 and the upper surface S2 of the substrate 101.
Although the first metal layer 111 may be unevenly formed on the first bump 112 and on the substrate 101 due to the vapor deposition and the thickness of the first bump 112, particularly at the junction between the side of the first bump 112 and the substrate 101, the thickness of the first metal layer 111 may be affected by the deposition process and may have some error (e.g., less than 5%), the thickness of the first portion 111a of the first metal layer 111 may be substantially equal to the thickness of the extension portion 111b, e.g., equal to 5000 angstroms or within a predetermined error range, or the thickness of the first portion 111a of the first metal layer 111 may be slightly less than the thickness of the extension portion 111 b. That is, the third thickness H3 may be less than or equal to the fourth thickness H4, but the third thickness H3 may also be greater than the fourth thickness H4.
In addition, the first thickness H1 and the second thickness H2 may have a ratio, for example, between 1 and 4, that is, the first thickness H1 may be greater than or equal to the second thickness H2, but the invention is not limited thereto. The higher the ratio, the greater the thickness of the first bump 112 with respect to the thickness of the insulating layer 113, and thus the higher the height (sum of the first thickness H1 and the third thickness H3) of the light blocking wall; the smaller the ratio is, the smaller the thickness of the first bump 112 is with respect to the thickness of the insulating layer 113, and thus the lower the height (sum of the first thickness H1 and the third thickness H3) of the light blocking wall is.
In an embodiment, the first thickness H1 is between 5000 a and 15000 a, for example, but even if the first thickness H1 is smaller than 5000 a, for example 2000 a or 3000 a, the light B incident at a large angle (for example, the incident angle is larger than 45 degrees) can still be blocked by the raised first metal layer 111, so that the height of the first bump 112 (i.e., the first thickness H1) can be changed or modified according to the angle change of the incident light.
In addition, the second thickness H2, the third thickness H3 and the fourth thickness H4 may be between 4000 angstroms and 5000 angstroms, the second thickness H2 is 4000 angstroms, and the third thickness H3 and the fourth thickness H4 are 5000 angstroms, for example. In an embodiment, the sum of the first thickness H1 and the third thickness H3 is greater than or equal to the sum of the second thickness H2 and the fourth thickness H4, where the sum of the first thickness H1 and the third thickness H3 is the height of the light blocking wall, and the sum of the second thickness H2 and the fourth thickness H4 is the height of the location of the semiconductor layer 114. Therefore, as long as the height of the light blocking wall is greater than or equal to the height of the semiconductor layer 114, the light B incident laterally can be prevented from reaching the semiconductor layer 114 in the semiconductor device 110A via the insulating layer 113, thereby reducing the leakage current. Of course, the higher the light blocking wall, the less likely the light B reaches the semiconductor layer 114 in the semiconductor device 110A through the insulating layer, and more light B reflected into the semiconductor device 110A through the upper plate (e.g., color filter) is blocked, so the better the light blocking effect is.
Referring to fig. 2B and 2C, fig. 2B is an enlarged schematic view of a semiconductor device 110B in the pixel structure 100B of fig. 2A, and fig. 2C is a schematic cross-sectional view of the semiconductor device 110B along the section line I-I of fig. 2B. The semiconductor device 110B of the present embodiment is similar to the semiconductor device 110A of the above embodiment, and like elements are denoted by like reference numerals, and will not be described again. The semiconductor devices 110A, 110B of the above two embodiments may be applied in the pixel structures 100A, 100B having the multi-domain (multi-domain) pixel electrode 105, such as 8-domain, 4-domain or other number domain pixel electrodes. That is, a plurality of pixel electrodes 105 are formed in one pixel by area division (domain-division) to reduce the degree of gray inversion, thereby improving the viewing angle of the liquid crystal display panel. Of course, the semiconductor devices 110A and 110B of the above two embodiments are not limited to the pixel structures 100A and 110B having the multi-domain pixel electrode 105, but can be applied to liquid crystal structures of a wide-viewing film (wide-viewing film) display mode, a vertical alignment (vertical alignment) display mode and an In-plane switching (In-plane switching) display mode, which is not limited thereto.
Referring to fig. 3A and 3B, an enlarged schematic view and a cross-sectional schematic view of a semiconductor device 110C according to another embodiment of the invention are shown. This embodiment is similar to the two embodiments described above, with the difference that: the semiconductor device 110C of the present embodiment includes a first bump 112 and a second bump 117, wherein the first bump 112 and the second bump 117 are respectively located at two opposite sides of the first metal layer 111, a first portion 111a of the first metal layer 111 partially covers an upper surface S1 of the first bump 112, and a second portion 111C of the first metal layer 111 partially covers an upper surface S3 of the second bump 117. Therefore, the opposite sides of the first metal layer 111 are raised by the first bump 112 and the second bump 117, respectively, and the middle extension portion 111b forms a recess with respect to the raised portion (i.e. the first portion 111a and the second portion 111 c), so that the semiconductor layer 114 can be located in the recess, and the height (h2+h4) of the location of the semiconductor layer 114 is slightly lower than or equal to the height of the raised portion (i.e. the sum of the thickness of the first bump 112 and the thickness of the first metal layer 111, h1+h3/the sum of the thickness of the second bump 117 and the thickness of the first metal layer 111, h1+h3).
In an embodiment, the first bump 112 and the second bump 117 have the same height and may be formed by depositing a film layer of the same material, removing a portion of the film layer by patterning etching, and depositing the first metal layer 111 on the substrate 101, the first bump 112 and the second bump 117, so that the height of the bump of the first metal layer 111 is greater than the height of the recess.
Referring to fig. 4A and 4B, an enlarged schematic view and a cross-sectional schematic view of a semiconductor device 110D according to another embodiment of the invention are shown. The semiconductor device 110D of the present embodiment is similar to the semiconductor device 110C of the above embodiment, and like elements are denoted by like reference numerals, and will not be described again. In the semiconductor devices 110C and 110D of the two embodiments, light blocking walls (i.e., raised portions) are formed on opposite sides of the first metal layer 111, wherein the first bump 112 is located on one opening area OA1 of the substrate 101 (an opening area not covered by the first metal layer 111), and the second bump 117 is located on the other opening area OA2 of the substrate 101, so that when the light B passes through the substrate 101 from the two opening areas OA1 and OA2 of the substrate 101, the light B is blocked by the raised first metal layer 111, thereby reducing leakage current, and the light blocking effect is better than that of the first metal layer 111 with only one light blocking wall.
Referring to fig. 5 and 6, fig. 5 shows that the semiconductor layer 114 is blocked by the raised first metal layer 111 and the percentage of the absorbed light is reduced, and fig. 6 shows that the absorbed light of the semiconductor layer 114 is reduced with the increase of the height of the raised first metal layer 111. Taking the spectrum integration energy absorbed by the semiconductor layer 114 by the incident substrate 101 with the incident angle of 40 degrees (the wavelength range is between 400 and 700 nm) as an example, when the bump height is 0 angstrom, the absorption amount of the semiconductor layer 114 is 0.0095 energy unit (the higher the negative value, the higher the absorption amount); when the bump height is 5000 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0068 energy unit, and the light absorption percentage is reduced by 28% with respect to the light absorption amount of 0.0095 (the higher the negative value, the better the improvement effect is). When the bump height was 7000 a, the light absorption amount of the semiconductor layer 114 was 0.0042 energy units, the light absorption percentage was reduced by 55%, when the bump height was 10000 a, the light absorption amount of the semiconductor layer 114 was 0.0026 energy units, the light absorption percentage was reduced by 72%, when the bump height was 12500 a, the light absorption amount of the semiconductor layer 114 was 0.00036 energy units, the improvement percentage was reduced by 96%, when the bump height was 15000 a, the light absorption amount of the semiconductor layer 114 was 0.0032 energy units, and the light absorption percentage was reduced by 97%.
From the above data, it is understood that the light absorption amount of the semiconductor layer is smaller as the thickness of the bump is higher, whereas the light absorption amount of the semiconductor layer is larger as the thickness of the bump is lower. Therefore, it can be demonstrated that the smaller the light absorption amount of the semiconductor layer is, the more effectively light incident into the semiconductor device can be blocked by the first metal layer, and the higher the height of the bump is, the better the light blocking effect is.
In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that numerous modifications and variations can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be determined from the following claims.

Claims (14)

1. A semiconductor device, comprising:
a substrate;
the first metal layer is arranged on the substrate, wherein the first metal layer is a grid electrode;
the first bump is arranged on the substrate, wherein a first part of the first metal layer partially covers an upper surface of the first bump;
an insulating layer covering the first portion of the first metal layer and a portion of the upper surface of the first bump;
a semiconductor layer disposed on the insulating layer;
the second metal layer is arranged on the semiconductor layer, wherein the second metal layer comprises a source electrode and a drain electrode; and
a pixel electrode electrically connected to the drain electrode;
an opening area is arranged between the pixel electrode and the first metal layer, and the first bump is positioned in the opening area.
2. The semiconductor device of claim 1, wherein said first bump has a first material, said first metal layer has a second material, and said first material is different from said second material.
3. The semiconductor device of claim 2, wherein the first material is a light transmissive material.
4. The semiconductor device of claim 2, wherein the first material is an organic dielectric material or an inorganic dielectric material.
5. The semiconductor device of claim 2, wherein the first material is a non-transparent material.
6. The semiconductor device of claim 1, wherein said first bump has a first thickness, a portion of said insulating layer overlaps said semiconductor layer and has a second thickness, said first thickness being greater than or equal to said second thickness.
7. The semiconductor device of claim 6, wherein a first portion of the first metal layer has a third thickness, an extension of the first metal layer covers an upper surface of the substrate, and the extension has a fourth thickness, wherein the third thickness is less than or equal to the fourth thickness.
8. The semiconductor device of claim 7, wherein a sum of the first thickness and the third thickness is equal to or greater than a sum of the second thickness and the fourth thickness.
9. The semiconductor device of claim 7, wherein said first thickness is between 5000 and 15000 angstroms, and said second, third and fourth thicknesses are between 4000 and 5000 angstroms.
10. The semiconductor device of claim 7, further comprising a pixel structure having a pixel electrode electrically connected to said second metal layer.
11. The semiconductor device of claim 1, further comprising a second bump disposed on the substrate, wherein a second portion of the first metal layer partially covers an upper surface of the second bump, and the insulating layer partially covers the second portion of the first metal layer and the upper surface of the second bump.
12. The semiconductor device of claim 11, wherein the semiconductor layer is correspondingly located on the insulating layer between the first bump and the second bump.
13. The semiconductor device of claim 11, wherein a recess is formed between the first bump and the second bump, and the semiconductor layer is correspondingly located on the recess.
14. The semiconductor device of claim 11, wherein said second bump is located in said opening region.
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