CN110993696A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN110993696A
CN110993696A CN201911139682.3A CN201911139682A CN110993696A CN 110993696 A CN110993696 A CN 110993696A CN 201911139682 A CN201911139682 A CN 201911139682A CN 110993696 A CN110993696 A CN 110993696A
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China
Prior art keywords
bump
thickness
semiconductor device
metal layer
layer
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CN110993696B (en
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李文荣
赖君伟
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AU Optronics Corp
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AU Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a semiconductor device, which comprises a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer and a second metal layer. The first metal layer is arranged on the substrate. The first bump is disposed on the substrate, and a first portion of the first metal layer partially covers an upper surface of the first bump. The insulating layer covers the first part of the first metal layer and the partial upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is arranged on the semiconductor layer.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
Semiconductor devices are widely used in consumer electronics products such as cellular phones, notebook computers, digital cameras, and the like. The semiconductor device is, for example, a Thin Film Transistor (TFT), which can be disposed on a Display panel, such as a Liquid Crystal Display (LCD) and an organic electroluminescent Display (OELD or OLED), so that the Display panel has the advantages of being light and thin and having low power consumption.
Generally, the thin film transistor includes a top-gate type thin film transistor (top-gate TFT) and a bottom-gate type thin film transistor (bottom-gate TFT). Since the TFT includes a semiconductor layer as an active layer or a channel layer, the semiconductor layer of the TFT is easily exposed to light to induce a leakage current (photo-induced current leakage) when the TFT is illuminated by an external light source (e.g., a backlight). In addition, the leakage current caused by illumination not only affects the performance of the tft device itself, but also causes cross-talk (cross-talk) problem during the display of the image, resulting in the degradation of the display quality of the display. In addition, after the light passes through the TFT substrate, a portion of the light may be reflected by the upper substrate and absorbed by the semiconductor layer or reach the semiconductor layer of the TFT through another path, which needs to be improved.
Disclosure of Invention
The invention relates to a semiconductor device for improving the efficiency of the semiconductor device.
According to an aspect of the present invention, a semiconductor device is provided, which includes a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer, and a second metal layer. The first metal layer is arranged on the substrate. The first bump is disposed on the substrate, wherein a first portion of the first metal layer partially covers an upper surface of the first bump. The insulating layer covers the first part of the first metal layer and the partial upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is arranged on the semiconductor layer.
In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:
drawings
Fig. 1A is a schematic plan view of a pixel structure according to an embodiment of the invention;
FIG. 1B is an enlarged schematic view of a semiconductor device in the pixel structure of FIG. 1A according to an embodiment of the present invention;
FIG. 1C is a cross-sectional view of a semiconductor device of the present invention taken along line I-I of FIG. 1B;
FIG. 2A is a schematic plan view of a pixel structure according to an embodiment of the invention;
FIG. 2B is an enlarged schematic view of a semiconductor device in the pixel structure of FIG. 2A according to an embodiment of the present invention;
FIG. 2C is a cross-sectional view of the semiconductor device of FIG. 2B along line I-I according to one embodiment of the present invention;
fig. 3A and 3B are an enlarged schematic view and a cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention;
fig. 4A and 4B are an enlarged schematic view and a cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention;
FIG. 5 is a diagram illustrating the percentage of improvement in the light absorption reduction of a semiconductor layer blocked by a raised first metal layer according to another embodiment of the present invention;
fig. 6 is a schematic view illustrating that the light absorption amount of the semiconductor layer in fig. 5 decreases as the height of the first metal layer after being raised increases.
Description of the symbols
T: thin film transistor
G: grid electrode
GI: gate insulating layer
AS: semiconductor layer
S: source electrode
D: drain electrode
100A, 100B: pixel structure
101: substrate
102: scanning line
103: shared wire
104: data line
105: pixel electrode
110A, 110B, 110C, 110D: semiconductor device with a plurality of semiconductor chips
111: a first metal layer
111 a: the first part
111 b: extension part
112: first bump
113: insulating layer
114: semiconductor layer
115: second metal layer
117: second bump
S1, S2, S3: upper surface of
OA, OA1, OA 2: open area
B: light ray
H1: a first thickness
H2: second thickness
H3: third thickness
H4: a fourth thickness
L: length of
Detailed Description
The following embodiments are provided for illustrative purposes only and are not intended to limit the scope of the present invention. The following description will be given with the same/similar reference numerals as used for the same/similar elements. Directional terms as referred to in the following examples, for example: up, down, left, right, front or rear, etc., are directions with reference to the attached drawings only. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
According to an embodiment of the present invention, a semiconductor device is provided to avoid a leakage current problem of a semiconductor layer due to illumination. As shown in fig. 1A and fig. 2A, the semiconductor device is, for example, a thin film transistor T or an active/switching element, the thin film transistor T is disposed on a substrate 101, the substrate 101 is, for example, glass, quartz, organic polymer, or other applicable materials, and the substrate 101 has light transmittance such that the backlight can pass through the substrate 101. In one embodiment, the thin film transistor T includes a gate electrode G, a gate insulating layer GI, a semiconductor layer AS, an ohmic contact layer, a source electrode S and a drain electrode D. The gate electrode G, the scan line 102, and the common line 103 may be formed on the substrate 101. The materials of the gate electrode G, the scan line 102, and the common line 103 may include metals, metal oxides, organic conductive materials, or combinations thereof. The scan line 102 is electrically connected to the gate electrode G, and the scan line 102 and the common line 103 are separated from each other. Next, a gate insulating layer GI is formed on the substrate 101, and the gate insulating layer GI is disposed on the gate electrode G, wherein the material of the gate insulating layer GI includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride), an organic material, or other suitable materials. Further, a semiconductor layer AS is formed on the gate insulating layer GI. The semiconductor layer AS may be a metal Oxide semiconductor, polysilicon, amorphous silicon, or other suitable semiconductor material, such AS Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Tin Oxide (SnO), Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO), or Indium-Tin Oxide (ITO). Then, an ohmic contact layer is formed on the semiconductor layer AS, and a portion of the semiconductor layer AS is exposed by the ohmic contact layer. The ohmic contact layer may be a dopant (dopant) -containing metal oxide semiconductor material, dopant-containing polysilicon, dopant-containing amorphous silicon, or other suitable dopant-containing semiconductor material. Next, a data line 104 is formed on the substrate 101, and a source S and a drain D are formed on the ohmic contact layer, so that the tft T can be formed in a pixel structure 100A of the display panel and electrically connected to the pixel electrode 105, as shown in fig. 1A and fig. 2A.
Referring to fig. 1A and 2A, the scan line 102 and the data line 104 are respectively disposed on different layers with an insulating layer (e.g., a gate insulating layer GI) therebetween, and the common line 103 and the data line 104 are respectively disposed on different layers with an insulating layer (e.g., a gate insulating layer GI) therebetween. The extending direction of the scan line 102 is different from the extending direction of the data line 104, and preferably, the extending direction of the scan line 102 is perpendicular to the extending direction of the data line 104, but the invention is not limited thereto.
In the present embodiment, in order to solve the problem of the leakage current, the height of the gate G (hereinafter, referred to AS the first metal layer 111) may be relatively higher than or equal to the height of the gate insulating layer GI (hereinafter, referred to AS the insulating layer 113) covering the gate G through the bump for raising, so that the light incident from the side surface of the gate G at a predetermined angle is reflected by the raised gate G and is far away from the semiconductor layer AS above the gate insulating layer GI, thereby effectively solving the problem of the leakage current caused by the illumination of the semiconductor layer AS (hereinafter, referred to AS the semiconductor layer 114).
Referring to fig. 1B and 1C, fig. 1B is an enlarged view of a semiconductor device 110A in the pixel structure 100A of fig. 1A, and fig. 1C is a cross-sectional view of the semiconductor device 110A along a line I-I of fig. 1B. The semiconductor device 110A includes a substrate 101, a first metal layer 111, a first bump 112, an insulating layer 113, a semiconductor layer 114, and a second metal layer 115. The first metal layer 111 is disposed on the substrate 101. The first bump 112 is disposed on the substrate 101, wherein a first portion 111a of the first metal layer 111 partially covers an upper surface S1 of the first bump 112. The insulating layer covers the first portion 111a of the first metal layer 111 and the partial upper surface S1 of the first bump 112. The semiconductor layer 114 is provided on the insulating layer 113. The second metal layer 115 is disposed on the semiconductor layer 114. The second metal layer 115 may include a source S and a drain D.
In one embodiment, the first metal layer 111 and the first bump 112 are disposed on the substrate 101, for example, the first bump 112 is formed on the substrate 101, and then the first metal layer 111 is formed on the substrate 101 and a portion of the first bump 112. Since the first metal layer 111 covers only a portion of the upper surface S1 of the first bump 112, the first portion 111a of the first metal layer 111 and a portion of the first bump 112 overlap each other, and the first metal layer 111 further has an extension portion 111b extending along the upper surface S2 of the substrate 101, and a length L of the extension portion 111b is at least greater than a length of the first portion 111a overlapping the first bump 112, for example, the length L of the extension portion 111b is 3 times, 4 times or more of the length of the first portion 111 a.
In addition, since the first metal layer 111 covers only a portion of the upper surface S1 of the first bump 112, the first bump 112 extends out of one side of the first metal layer 111 opposite to the extending portion 111b, for example, the first bump 112 is located on the opening area OA (i.e., the opening area not covered by the first metal layer 111) of the substrate 101. When the first bump 112 is made of a light-permeable material, the first bump 112 covers the opening region without affecting the aperture ratio of the substrate 101, and therefore the first bump 112 is preferably made of a light-permeable material, but the invention is not limited thereto.
In an embodiment, when the light B incident at the predetermined angle passes through the substrate 101 from the opening area OA of the substrate 101, since the first bump 112 and the insulating layer 113 are made of a light-permeable material, the light B can pass through the first bump 112 and the insulating layer 113 or enter the first bump 112 and the insulating layer 113, but the light B is still blocked by the raised first metal layer 111. Therefore, the first portion 111a of the first metal layer 111 is raised by the first bump 112 to form a light-blocking wall (i.e., a raised portion) to block the light B entering the semiconductor device 110A through the insulating layer 113, and also to block the light reflected to the semiconductor device 110A through the upper plate (e.g., a color filter plate), thereby reducing the leakage current. In another embodiment, if the first bump 112 is made of opaque material without considering the influence on the aperture ratio of the substrate 101, the light B can be blocked by the first bump 112.
In one embodiment, the first bump 112 is made of a first material, and the first metal layer 111 is made of a second material, the first material being different from the second material. That is, the first bump 112 and the first metal layer 111 are not made of the same material. The first bump 112 may be a transparent material, a non-transparent material, a metal material, an organic dielectric material (e.g., a polymer material such as a resin), or an inorganic dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). The first metal layer 111 may be a metal material, a metal oxide, an organic conductive material, or other suitable materials.
Referring to fig. 1C, the first bump 112 has a first thickness H1, the insulating layer 113 has a second thickness H2, the first portion 111a of the first metal layer 111 has a third thickness H3, and an extended portion 111b of the first metal layer 111 has a fourth thickness H4. The first thickness H1 refers to a vertical distance between the upper surface S1 of the first bump 112 and the upper surface S2 of the substrate 101, the second thickness H2 refers to a vertical distance between the upper surface of the insulating layer 113 and the upper surface of the extension portion 111b of the first metal layer 111, the third thickness H3 refers to a vertical distance between the upper surface of the first portion 111a of the first metal layer 111 and the upper surface S1 of the first bump 112, and the fourth thickness H4 refers to a vertical distance between the upper surface of the extension portion 111b of the first metal layer 111 and the upper surface S2 of the substrate 101.
Although the first metal layer 111 may be formed non-uniformly on the first bump 112 and the substrate 101 due to the vapor deposition and the thickness of the first bump 112, particularly at the junction between the side of the first bump 112 and the substrate 101, the thickness of the first metal layer 111 may be affected by the deposition process to have a tolerance (e.g., a tolerance of less than 5%), the thickness of the first portion 111a of the first metal layer 111 and the thickness of the extension portion 111b are substantially equal to each other, e.g., equal to 5000 angstroms or within a predetermined tolerance range, or the thickness of the first portion 111a of the first metal layer 111 may be slightly smaller than the thickness of the extension portion 111 b. That is, the third thickness H3 may be less than or equal to the fourth thickness H4, but the third thickness H3 may also be greater than the fourth thickness H4.
In addition, the first thickness H1 and the second thickness H2 may have a ratio, for example, between 1 and 4, that is, the first thickness H1 may be greater than or equal to the second thickness H2, but the invention is not limited thereto. The higher the ratio, the larger the thickness of the first bump 112 relative to the thickness of the insulating layer 113, and thus the height of the light blocking wall (the sum of the first thickness H1 and the third thickness H3) is also higher; the smaller ratio means that the thickness of the first bump 112 is smaller relative to the thickness of the insulating layer 113, and thus the height of the light blocking wall (the sum of the first thickness H1 and the third thickness H3) is also lower.
In one embodiment, the first thickness H1 is, for example, between 5000 a and 15000 a, but even if the first thickness H1 is less than 5000 a, such as 2000 a or 3000 a, the light B incident at a large angle (e.g., incident angle greater than 45 degrees) can still be blocked by the elevated first metal layer 111, so that the height of the first bump 112 (i.e., the first thickness H1) can be changed or modified according to the angle change of the incident light.
In addition, the second thickness H2, the third thickness H3 and the fourth thickness H4 may be between 4000 angstroms and 5000 angstroms, the second thickness H2 is 4000 angstroms, and the third thickness H3 and the fourth thickness H4 are 5000 angstroms. In an embodiment, a sum of the first thickness H1 and the third thickness H3 is greater than or equal to a sum of the second thickness H2 and the fourth thickness H4, wherein the sum of the first thickness H1 and the third thickness H3 is a height of the light blocking wall, and the sum of the second thickness H2 and the fourth thickness H4 is a height of the position of the semiconductor layer 114. Therefore, as long as the height of the light blocking wall is greater than or equal to the height of the position of the semiconductor layer 114, the laterally incident light B can be prevented from reaching the semiconductor layer 114 in the semiconductor device 110A through the insulating layer 113, thereby reducing the leakage current. Of course, the higher the height of the light blocking wall, the less the light B will reach the semiconductor layer 114 in the semiconductor device 110A through the insulating layer, and the more the light B reflected to the semiconductor device 110A through the upper plate (e.g., the color filter plate) will be blocked, so the better the light blocking effect.
Referring to fig. 2B and 2C, fig. 2B is an enlarged schematic view of a semiconductor device 110B in the pixel structure 100B of fig. 2A, and fig. 2C is a cross-sectional view of the semiconductor device 110B along a section line I-I of fig. 2B. The semiconductor device 110B of the present embodiment is similar to the semiconductor device 110A of the previous embodiment, and like elements are denoted by like reference numerals and are not repeated herein. The semiconductor devices 110A, 110B of the above two embodiments can be applied to the pixel structures 100A, 100B having multi-domain (multi-domain) pixel electrodes 105, such as 8-domain, 4-domain or other domains of pixel electrodes. That is, a plurality of pixel electrodes 105 are divided into areas within one pixel to reduce the degree of gray inversion, thereby improving the viewing angle of the liquid crystal display panel. Of course, the semiconductor devices 110A and 110B of the above two embodiments are not limited to be used only In the pixel structures 100A and 110B having the multi-domain pixel electrode 105, but may also be applied to liquid crystal structures of wide-viewing angle (wide-viewing film) display mode, vertical alignment (vertical alignment) display mode, and In-plane switching (In-plane switching) display mode, and the invention is not limited thereto.
Referring to fig. 3A and 3B, an enlarged schematic view and a cross-sectional schematic view of a semiconductor device 110C according to another embodiment of the invention are shown. This embodiment is similar to the two embodiments, and the difference is: the semiconductor device 110C of the present embodiment includes a first bump 112 and a second bump 117, where the first bump 112 and the second bump 117 are respectively located at two opposite sides of the first metal layer 111, and a first portion 111a of the first metal layer 111 partially covers an upper surface S1 of the first bump 112, and a second portion 111C of the first metal layer 111 partially covers an upper surface S3 of the second bump 117. Therefore, the two opposite sides of the first metal layer 111 are respectively raised by the first bump 112 and the second bump 117, and the middle extension portion 111b forms a recess with respect to the raised portion (i.e., the first portion 111a and the second portion 111c), so that the semiconductor layer 114 can be located in the recess, and the height (H2+ H4) of the location of the semiconductor layer 114 is slightly lower than or equal to the height of the raised portion (i.e., the sum H1+ H3 of the thickness of the first bump 112 and the thickness of the first metal layer 111/the sum H1+ H3 of the thickness of the second bump 117 and the thickness of the first metal layer 111).
In an embodiment, the first bump 112 and the second bump 117 have the same height and may be formed by depositing a film of the same material, removing a portion of the film by patterned etching, and depositing the first metal layer 111 on the substrate 101, the first bump 112 and the second bump 117, such that the height of the bump of the first metal layer 111 is greater than the height of the recess.
Referring to fig. 4A and 4B, an enlarged schematic view and a cross-sectional schematic view of a semiconductor device 110D according to another embodiment of the invention are shown. The semiconductor device 110D of the present embodiment is similar to the semiconductor device 110C of the previous embodiment, and like elements are denoted by like reference numerals and are not repeated herein. In the semiconductor devices 110C and 110D of the above two embodiments, the light-blocking walls (i.e., the bumps) are formed on the two opposite sides of the first metal layer 111, wherein the first bump 112 is located on one opening area OA1 (the opening area not covered by the first metal layer 111) of the substrate 101, and the second bump 117 is located on the other opening area OA2 of the substrate 101, so that when the light ray B passes through the substrate 101 from the two opening areas OA1 and OA2 of the substrate 101, the light ray B is blocked by the raised first metal layer 111, thereby achieving the problem of reducing the leakage current, and the light-blocking effect is better than that of the first metal layer 111 having only one light-blocking wall on one side.
Referring to fig. 5 and fig. 6, fig. 5 illustrates a percentage of light absorption amount of the semiconductor layer 114 that is reduced by the blocking of the first metal layer 111 after the step-up, and fig. 6 illustrates a schematic view that the light absorption amount of the semiconductor layer 114 is reduced as the height of the first metal layer 111 after the step-up increases. Taking the spectrum integral energy absorbed by the semiconductor layer 114 when the light with an incident angle of 40 degrees (the wavelength range is between 400-700 nm) enters the substrate 101 as an example, when the height of the bump is 0 angstrom, the light absorption amount of the semiconductor layer 114 is 0.0095 energy unit (the higher the negative value is, the higher the light absorption amount is); when the height of the bump is 5000 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0068 energy unit, which is 28% less (higher negative value indicates better improvement effect) relative to the light absorption percentage of 0.0095. When the height of the bump is 7000 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0042 energy units and the light absorption percentage is reduced by 55%, when the height of the bump is 10000 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0026 energy units and the light absorption percentage is reduced by 72%, when the height of the bump is 12500 angstroms, the light absorption amount of the semiconductor layer 114 is 0.00036 energy units and the improvement percentage is reduced by 96%, and when the height of the bump is 15000 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0032 energy units and the light absorption percentage is reduced by 97%.
As can be seen from the above data, the light absorption amount of the semiconductor layer is smaller as the thickness of the bump is higher, whereas the light absorption amount of the semiconductor layer is larger as the thickness of the bump is lower. Therefore, it can be demonstrated that the smaller the light absorption amount of the semiconductor layer is, the more effectively the light incident into the semiconductor device can be blocked by the first metal layer, and the higher the height of the bump is, the better the light blocking effect is.
In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.

Claims (15)

1. A semiconductor device, comprising:
a substrate;
a first metal layer disposed on the substrate;
a first bump disposed on the substrate, wherein a first portion of the first metal layer partially covers an upper surface of the first bump;
an insulating layer covering the first portion of the first metal layer and a portion of the upper surface of the first bump;
a semiconductor layer disposed on the insulating layer; and
and the second metal layer is arranged on the semiconductor layer.
2. The semiconductor device of claim 1, wherein said first bump is of a first material and said first metal layer is of a second material, said first material being different from said second material.
3. The semiconductor device according to claim 2, wherein the first material is a light-transmissive material.
4. The semiconductor device of claim 2, wherein said first material is an organic dielectric material or an inorganic dielectric material.
5. The semiconductor device of claim 2, wherein said first material is a non-transparent material.
6. The semiconductor device of claim 1, wherein the first bump has a first thickness, a portion of the insulating layer overlaps the semiconductor layer and has a second thickness, and the first thickness is greater than or equal to the second thickness.
7. The semiconductor device of claim 6, wherein the first portion of the first metal layer has a third thickness, the extended portion of the first metal layer covers the upper surface of the substrate, and the extended portion has a fourth thickness, wherein the third thickness is less than or equal to the fourth thickness.
8. The semiconductor device of claim 7, wherein a sum of said first thickness and said third thickness is equal to or greater than a sum of said second thickness and said fourth thickness.
9. The semiconductor device according to claim 7, wherein the first thickness is between 5000 and 15000 angstroms, and the second thickness, the third thickness and the fourth thickness are between 4000 and 5000 angstroms.
10. The semiconductor device of claim 7, further comprising a pixel structure having a pixel electrode electrically connected to the second metal layer.
11. The semiconductor device of claim 1, further comprising a second bump disposed on the substrate, wherein a second portion of the first metal layer partially covers an upper surface of the second bump, and the insulating layer covers the second portion of the first metal layer and a portion of the upper surface of the second bump.
12. The semiconductor device of claim 11, wherein the semiconductor layer is disposed on the insulating layer between the first bump and the second bump.
13. The semiconductor device of claim 11, wherein a recess is formed between the first bump and the second bump, and the semiconductor layer is correspondingly disposed on the recess.
14. The semiconductor device of claim 1, wherein the first bump is located on an open area of the substrate.
15. The semiconductor device of claim 11, wherein the second bump is located on an open area of the substrate.
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