CN103299431B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN103299431B
CN103299431B CN201280005200.5A CN201280005200A CN103299431B CN 103299431 B CN103299431 B CN 103299431B CN 201280005200 A CN201280005200 A CN 201280005200A CN 103299431 B CN103299431 B CN 103299431B
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oxide semiconductor
semiconductor layer
contact area
substrate
source electrode
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CN103299431A (en
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川岛慎吾
中田幸伸
村井淳人
田中信也
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

The semiconductor device (100A) of the present invention includes: have the oxide semiconductor layer (4) of the first contact area (4a) and the second contact area (4b) and the channel region (4c) that is positioned between the first contact area (4a) and the second contact area (4b); The source electrode (5) formed in the way of contacting with the first contact area (4a) on oxide semiconductor layer (4); With the drain electrode (6) formed in the way of contacting with the second contact area (4b) on oxide semiconductor layer (4). All sides of oxide semiconductor layer (4) are positioned on gate electrode (2), the width of source electrode (5) is more than the width of oxide semiconductor layer (4), and the width of drain electrode (6) is more than the width of oxide semiconductor layer (4).

Description

Semiconductor device
Technical field
The present invention relates to the semiconductor device with the thin film transistor (TFT) (ThinFilmTransistor:TFT) being provided with oxide semiconductor layer.
Background technology
In recent years, the exploitation (such as patent documentation 1～4) of the TFT with the oxide semiconductor layer containing In (indium), Zn (zinc) or Ga (gallium) etc. is actively developed. The TFT (hereinafter referred to as oxide semiconductor TFT) with oxide semiconductor layer has high mobility and the characteristic of high make-to-break ratio (onoffratio).
Patent document 4 discloses that and be formed with photomask etc. so that the visible ray of short wavelength side will not be irradiated to containing In, Ga and Zn amorphous oxide semiconductor (a-IGZO) layer on semiconductor device. By forming photomask, it is prevented that the characteristic of oxide semiconductor TFT changes.
Prior art literature
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 2010-98305 publication
Patent documentation 2: Japanese Unexamined Patent Publication 2009-224354 publication
Patent documentation 3: Japanese Unexamined Patent Publication 2007-150157 publication
Patent documentation 4: Japanese Unexamined Patent Publication 2007-115902 publication
Summary of the invention
Invention to solve the technical problem that
But, there is the problem that the operation of formation photomask increases during fabrication in the semiconductor device disclosed in patent documentation 4. Additionally, in structure disclosed in patent documentation 4, photomask only forms the backlight side at TFT, therefore, utilizing this photomask cannot the light that inject oxide semiconductor TFT from observer side be blocked, the visible ray of short wavelength side is likely irradiated to oxide semiconductor TFT. If it addition, form photomask further in order to the light injecting oxide semiconductor TFT from observer side is blocked, then the quantity of manufacturing process will be increased further.
The present invention develops in view of above-mentioned technical problem, its object is to provide a kind of quantity not increasing manufacturing process just can manufacture and be not easy the semiconductor device because light causes the characteristic of TFT to change.
Solve the technical scheme of technical problem
The semiconductor device of embodiments of the present invention includes: substrate; Form the gate electrode on aforesaid substrate; Form the gate insulator on above-mentioned gate electrode; The oxide semiconductor layer of island, it is formed on above-mentioned gate insulator, and has the first contact area and the second contact area and the channel region between above-mentioned first contact area and above-mentioned second contact area; The source electrode formed in the way of contacting with above-mentioned first contact area on above-mentioned oxide semiconductor layer; With the drain electrode formed in the way of contacting with above-mentioned second contact area on above-mentioned oxide semiconductor layer, all sides of above-mentioned oxide semiconductor layer are positioned on above-mentioned gate electrode, it is being perpendicular to aforesaid substrate and the cross section along above-mentioned first contact area of channel width dimension crosscut, the width of above-mentioned source electrode is more than the width of above-mentioned oxide semiconductor layer, being perpendicular to aforesaid substrate and the cross section along above-mentioned second contact area of channel width dimension crosscut, the width of above-mentioned drain electrode is more than the width of above-mentioned oxide semiconductor layer.
In one embodiment, above-mentioned source electrode covers the side being positioned at channel width dimension of in the surface of above-mentioned oxide semiconductor layer, above-mentioned first contact area and above-mentioned first contact area, and above-mentioned drain electrode covers the side being positioned at channel width dimension of in the surface of above-mentioned oxide semiconductor layer, above-mentioned second contact area and above-mentioned second contact area.
In one embodiment, in the surface of above-mentioned oxide semiconductor layer, all upper surfaces and side except the upper surface of above-mentioned channel region and the side being positioned at channel width dimension of above-mentioned channel region are covered by above-mentioned source electrode or above-mentioned drain electrode.
In one embodiment, in the surface of above-mentioned oxide semiconductor layer, the upper surface of above-mentioned channel region and the side being positioned in channel width dimension of above-mentioned channel region are covered by the dielectric film containing aerobic, and contact with the above-mentioned dielectric film containing aerobic, when in terms of the normal direction of aforesaid substrate, the part not covered by above-mentioned source electrode and above-mentioned drain electrode in above-mentioned oxide semiconductor layer, has the first recess or the first notch part.
The semiconductor device of another embodiment of the invention includes: substrate, form the gate electrode on aforesaid substrate, form the gate insulator on above-mentioned gate electrode, the oxide semiconductor layer of island, it is formed on above-mentioned gate insulator and has the first contact area and the second contact area and the channel region between above-mentioned first contact area and above-mentioned second contact area, the source electrode formed in the way of contacting with above-mentioned first contact area on above-mentioned oxide semiconductor layer, with the drain electrode formed in the way of contacting with above-mentioned second contact area on above-mentioned oxide semiconductor layer, all sides of above-mentioned oxide semiconductor layer are positioned on above-mentioned gate electrode, region beyond the surface of the above-mentioned channel region of above-mentioned oxide semiconductor layer and side is covered by above-mentioned source electrode and above-mentioned drain electrode, the region not covered by above-mentioned source electrode and above-mentioned drain electrode in above-mentioned oxide semiconductor layer is covered by the dielectric film containing aerobic, and contact with the above-mentioned dielectric film containing aerobic, when in terms of the normal direction of aforesaid substrate, the part not covered by above-mentioned source electrode and above-mentioned drain electrode in above-mentioned oxide semiconductor layer has the first recess or the first notch part.
In one embodiment, from the normal direction of aforesaid substrate, when distance between the above-mentioned source electrode and above-mentioned drain electrode of the side by clipping above-mentioned channel region is set to L, the length of the orientation of above-mentioned first recess or above-mentioned first notch part and the length of channel width dimension are separately more than 0 and be below L/2.
In one embodiment, the above-mentioned dielectric film containing aerobic is by SiO2Formed.
In one embodiment, when in terms of the normal direction of aforesaid substrate, above-mentioned source electrode has recess, and above-mentioned drain electrode is positioned at above-mentioned recess.
In one embodiment, above-mentioned first contact area and above-mentioned second contact area have multiple.
In one embodiment, above-mentioned oxide semiconductor layer contains In, Ga and Zn.
Invention effect
According to the present invention, it is provided that a kind of quantity not increasing manufacturing process just can manufacture and be not easy the semiconductor device because light causes the characteristic of TFT to change.
Accompanying drawing explanation
Fig. 1 (a) is the schematic plan view of the semiconductor device 100A of embodiments of the present invention, and (b) is the schematic section of the semiconductor device 100A of the I-I ' line along (a).
Fig. 2 (a) indicates that the curve chart of grid voltage (Vg)-drain current (Id) characteristic of the oxide semiconductor TFT described in patent documentation 4, and (b) indicates that the curve chart of grid voltage (Vg)-drain current (Id) characteristic of TFT10A.
Fig. 3 (a) is the schematic plan view of the semiconductor device 100B of another embodiment of the invention, and (b) is the schematic plan view of semiconductor device 100B '.
Fig. 4 indicates that the curve chart of grid voltage (Vg)-drain current (Id) characteristic of TFT10B.
Fig. 5 (a) is the schematic plan view of the semiconductor device 100C of the further embodiment of the present invention, and (b) is the schematic section of the semiconductor device 100C of the II-II ' line along (a).
Fig. 6 indicates that the curve chart of grid voltage (Vg)-drain current (Id) characteristic of TFT10C.
Fig. 7 (a) is the schematic plan view of the semiconductor device 100D of the further embodiment of the present invention, and (b) is the schematic section of the semiconductor device 100D of the III-III ' line along (a).
Fig. 8 (a) is the schematic plan view of the gate terminal 90A that the semiconductor device of embodiments of the present invention has, b () is the schematic plan view of the source terminal 90B that the semiconductor device of embodiments of the present invention has, c () is the schematic section of the gate terminal 90A of the A1-A1 ' line along (a), (d) is the schematic section of the gate terminal 90B of the A2-A2 ' line along (b).
Detailed description of the invention
It is described with reference to the semiconductor device (TFT substrate) of embodiments of the present invention. The semiconductor device of present embodiment is such as the semiconductor device used in liquid crystal indicator. But the invention is not restricted to embodiment illustrated.
Fig. 1 (a) is the schematic plan view of the semiconductor device 100A of embodiments of the present invention, and Fig. 1 (b) is the schematic section of the semiconductor device 100A of the I-I ' line along Fig. 1 (a).
As shown in Fig. 1 (a) and Fig. 1 (b), semiconductor device 100A has the TFT10A formed on first substrate (such as glass substrate) 1 and forms the protective layer 7 on TFT10A. TFT10A is such as oxide semiconductor TFT. TFT10A is such as the TFT of pixel. TFT10A has gate electrode 2, form gate insulator 3 on gate electrode 2, the oxide semiconductor layer 4 of island that formed on gate insulator 3 and the source electrode 5 formed on oxide semiconductor layer 4 and drain electrode 6. Oxide semiconductor layer 4 has the first contact area 4a, the second contact area 4b and the channel region 4c between the first contact area 4a and the second contact area 4b. Source electrode 5 is formed in the way of contacting with the first contact area 4a, and drain electrode 6 is formed in the way of contacting with the second contact area 4b. All sides of oxide semiconductor layer 4 are positioned on gate electrode 2. It is being perpendicular to first substrate 1 and along on the cross section of channel width dimension (direction being perpendicular to I-I ' line in Fig. 1 (a)) crosscut the first contact area 4a, the width w2 of source electrode 5 is more than the width w1 of oxide semiconductor layer 4. Equally, it is being perpendicular to first substrate 1 and along on the cross section of channel width dimension crosscut the second contact area 4b, the width w4 of drain electrode 6 is more than the width w3 of oxide semiconductor layer 4. It addition, in the surface of source electrode 5 capping oxide semiconductor layer 4, the side being positioned at channel width dimension of the first contact area 4a and the first contact area 4a. The side being positioned at channel width dimension in the surface of drain electrode 6 capping oxide semiconductor layer 4, the second contact area 4b and the second contact area 4b. It addition, in the surface of oxide semiconductor 4, all upper surfaces except the upper surface of channel region 4c and the side being positioned at channel width dimension of channel region 4c and side, all covered by source electrode 5 or drain electrode 6.In the surface of oxide semiconductor layer 4, the upper surface of channel region 4c and the side being positioned at channel width dimension of channel region 4c are covered by the dielectric film (such as protecting film 7) containing aerobic, and contact with the dielectric film containing aerobic.
So, if all sides of oxide semiconductor layer 4 are positioned on gate electrode 2, then it is formed without the photomask disclosed in patent documentation 4, it becomes possible to the light that the side contrary with TFT10A side from first substrate 1 is incident is blocked, so that this light is not easy to be irradiated to oxide semiconductor layer 4. It addition, the region beyond the surface of channel region 4c and side is covered by source electrode 5 or drain electrode 6, therefore, even if light such as liquid crystal panel in the diffuse-reflectance incident from the TFT10A side of first substrate 1, also it is not easy to be irradiated to oxide semiconductor layer 4. It addition, semiconductor device 100A forms photomask without the semiconductor device as described in patent documentation 4, the quantity therefore not increasing manufacturing process just can manufacture.
Fig. 2 (a) indicates that the curve chart of grid voltage (Vg)-drain current (Id) curve with the TFT described in patent documentation 4 with mutually isostructural oxide semiconductor TFT (hereinafter referred to as TFT50), and Fig. 2 (b) indicates that the curve chart of grid voltage (Vg)-drain current (Id) curve of TFT10A. In the curve chart of Fig. 2 (a) and Fig. 2 (b), grid voltage (Vg) when curve C1 is to drive each TFT under dark situation-drain current (Id) curve, grid voltage (Vg)-drain current (Id) curve when curve C2 is that (halogen light illumination: 4klx) drives each TFT under bright ring border.
As shown in Fig. 2 (a), when TFT50, when driving TFT under bright ring border, compared with under dark situation during driving TFT, cut-off current increases, and threshold voltage moves to low voltage side. On the other hand, from Fig. 2 (b) it can be seen that when TFT10A, even if driving TFT under bright ring border, cut-off current also increases without than TFT50, and threshold voltage also less moves to low voltage side. It is to say, TFT10A has the structure that light is not easy to be irradiated to the oxide semiconductor layer 4 of TFT10A, therefore, the characteristic of TFT is not easy change.
So, semiconductor device 100A has light and is not easy to be irradiated to the structure of oxide semiconductor layer 4, and therefore, the situation that cut-off current increases because of light is suppressed, and the situation that threshold voltage moves to low voltage side is also affected by suppressing. It addition, in semiconductor device 100A, utilize gate electrode 2, source electrode 5 and drain electrode 6 that oxide semiconductor layer 4 is carried out shading, therefore, without separately setting photomask as the semiconductor device disclosed in patent documentation 4, therefore, manufacturing cost is without increase.
Gate electrode 2, source electrode 5 and drain electrode 6 have such as with upper strata for Al (aluminum) layer, stepped construction with lower floor for Ti (titanium) layer. Replacing Al layer, upper strata can also be Cu (copper) layer. It addition, gate electrode 2, source electrode 5 and drain electrode 6 can also have the single layer structure formed by Ti, Mo (molybdenum), Ta (tantalum) or Cr (chromium) layer. The thickness of gate electrode 2, source electrode 5 and drain electrode 6 is such as more than 100nm below 300nm.
Gate insulator 3 and protective layer 7 are preferably formed by the dielectric film containing aerobic. When gate insulator 3 and protective layer 7 are formed by the dielectric film containing aerobic, it is possible to oxide semiconductor layer 4 for oxygen supply, it is prevented that the oxygen defect of oxide semiconductor layer 4.Gate insulator 3 and protective layer 7 are such as by SiO2(silicon dioxide) is formed. It addition, gate insulator 3 and protective layer 7 can also by SiNx(silicon nitride) is formed. It addition, gate insulator 3 and protective layer 7 can also be formed by SiON (silicon oxynitride). It addition, gate insulator 3 and protective layer 7 can also have containing SiO2、SiNxOr the stepped construction of SiON. It addition, on protective layer 7, it is also possible to form photosensitive organic insulating film. The thickness of gate insulator 3 is such as more than 300nm below 400nm. The thickness of protective layer 7 is such as more than 200nm below 300nm. It addition, on oxide semiconductor layer 4, it is also possible to form the etching barrier layer with contact hole source electrode 5 and drain electrode 6 electrically connected with oxide semiconductor layer 4. Now, etching barrier layer is such as by SiO2Formed.
Oxide semiconductor layer 4 is such as the amorphous oxide semiconductor layer (a-IGZO layer) containing In (indium), Ga (gallium) and Zn (zinc). Oxide semiconductor layer 4 can also be such as amorphous oxide semiconductor (a-IZO) layer having In and Zn and not having Ga, or have Zn and do not have amorphous oxide semiconductor (a-ZnO) layer of In and Ga. The thickness of oxide semiconductor layer 4 is such as more than 40nm below 60nm.
Then, semiconductor device 100B and 100C with semiconductor device 100A with other embodiment of the present invention of same effect is described. To the structure member identical with semiconductor device 100A, mark identical reference accompanying drawing labelling, it is to avoid repeat specification.
Fig. 3 (a) is the schematic plan view of the semiconductor device 100B TFT10B having. Fig. 3 (b) is the schematic plan view of the semiconductor device 100B ' of the variation as the semiconductor device 100B TFT10B ' having. Wherein, in Fig. 3 (a) and Fig. 3 (b), identical with the sectional view shown in Fig. 1 (b) along the sectional view of I-I ' line.
As shown in Fig. 3 (a), when the oxide semiconductor layer 4 of TFT10B has in terms of the normal direction from first substrate 1 (not shown), the side in the direction (direction being perpendicular to I-I ' line in Fig. 1 (a)) that the channel direction with oxide semiconductor layer 4 of the part not covered by source electrode 5 and drain electrode 6 in the oxide semiconductor layer 4 of TFT10A is orthogonal is formed with the structure of recess 9a and 9b. TFT10B is such as the TFT of pixel. Recess 9a and 9b can also only form any of which. It addition, in the manufacture process of semiconductor device 100B, accidentally (not being purposely) forms recess 9a and 9b sometimes.
It addition, as shown in Fig. 3 (b), it is also possible to form notch part 9a ' and 9b ', replace forming above-mentioned recess 9a and 9b. Specifically, when the oxide semiconductor layer 4 of TFT10B ' has in terms of the normal direction from first substrate 1 (not shown), the side in the direction (direction being perpendicular to I-I ' line in Fig. 1 (a)) that the channel direction with oxide semiconductor layer 4 of the part not covered by source electrode 5 and drain electrode 6 in the oxide semiconductor layer 4 of TFT10A is orthogonal is formed with the structure of notch part 9a ' and 9b '. In other words, when the oxide semiconductor layer 4 of TFT10B ' is in terms of the normal direction from first substrate 1 (not shown), the side in the direction (being perpendicular to the direction of I-I ' line) that the channel direction with oxide semiconductor layer 4 of the part not covered by source electrode 5 and drain electrode 6 in the oxide semiconductor layer 4 of TFT10A is orthogonal has protuberance 9a " and 9b ".Wherein, notch part 9a ' and 9b ' is respectively formed at protuberance 9a " and 9b " and source electrode 5 and drain electrode 6 between. Notch part 9a ' and 9b ' can also only form any of which. It addition, in Fig. 3 (b), notch part 9a ' and 9b ' is respectively formed with two, but notch part 9a ' can also be one, and notch part 9b ' can also be one.
Time in terms of the normal direction from first substrate 1 (not shown), if the distance between the source electrode 5 of the side clipping channel region 4c and drain electrode 6 is set to L, then length Y1, the Y1 ' of the channel width dimension (direction being perpendicular to I-I ' line in Fig. 3 (a), (b)) of length X1, the X1 ' of the orientation (direction being parallel to I-I ' line in Fig. 3 (a), (b)) of recess 9a and 9b or notch part 9a ' and 9b ' and recess 9a and 9b or notch part 9a ' and 9b ' is separately preferably greater than 0 and for below L/2.
When so forming recess 9a and 9b or notch part 9a ' and 9b ', it is possible to reduce TFT10B or the TFT10B ' side from first substrate 1 (not shown) and inject and the area that is irradiated to the light of oxide semiconductor layer 4. As a result of which it is, compared with TFT10A, be more not easy to produce because of the change of photogenic TFT characteristic. And, oxide semiconductor layer 4 becomes big with the contact area of protective layer 7, increases it is thus possible, for instance supply the quantity delivered of the oxygen to oxide semiconductor layer 4 from the protective layer 7 containing aerobic such that it is able to prevent the oxygen defect of oxide semiconductor layer 4. It addition, above-mentioned recess 9a and 9b and the respective length X1 of notch part 9a ' and 9b ', X1 ', Y1, Y1 ' if the characteristic more than L/2, TFT is possible to be deteriorated.
Fig. 4 indicates that the curve chart of grid voltage (Vg)-drain current (Id) curve of TFT10B. In the curve chart of Fig. 4, grid voltage (Vg)-drain current (Id) curve when curve C1 is to drive TFT10B under dark situation, grid voltage (Vg)-drain current (Id) curve when curve C2 is that (halogen light illumination: 4klx) drives TFT10B under bright ring border.
As can be seen from Figure 4, TFT10B is also the same with TFT10A, even if driving TFT under bright ring border, cut-off current also increases unlike TFT50 (with reference to Fig. 2 (a)), and threshold voltage also less moves to low voltage side. It addition, TFT10B and the TFT10A (with reference to Fig. 2 (b)) being formed with recess 9a and 9b compares, the increase of cut-off current is less, and threshold voltage is also less to the movement of low voltage side.
Then, the semiconductor device 100C of the further embodiment of the present invention is described with reference to Fig. 5.
Fig. 5 (a) is the schematic plan view of semiconductor device 100C. Fig. 5 (b) is the schematic section of the semiconductor device 100C of the II-II ' line along Fig. 5 (a).
As shown in Fig. 5 (a) and Fig. 5 (b), semiconductor device 100C has the TFT10C formed on first substrate (such as glass substrate) 1 and forms the protective layer 7 on TFT10C. TFT10C is such as oxide semiconductor TFT. TFT10C is such as the TFT of pixel. TFT10C has gate electrode 2, form gate insulator 3 on gate electrode 2, the oxide semiconductor layer 4 of island that formed on gate insulator 3 and the source electrode 5 formed on oxide semiconductor layer 4 and drain electrode 6. All sides of oxide semiconductor layer 4 are positioned on gate electrode 2. Oxide semiconductor layer 4 has the first contact area 4a, the second contact area 4b and the channel region 4c between the first contact area 4a and the second contact area 4b.It addition, in terms of the normal direction from first substrate 1 time, source electrode 5 has recess 5a. A part for drain electrode 6 is positioned at recess 5a. The recess 5a of source electrode 5 is formed in the way of contacting with the first contact area 4a, and drain electrode 6 is formed in the way of contacting with the second contact area 4b. When source electrode 5 has recess 5a, it is possible to increase channel width. Region beyond the surface of the channel region 4c of oxide semiconductor layer 4 and side is covered by source electrode 5 and drain electrode 6. Have a structure in which, it becomes possible to reduce the area in the region being irradiated by light of oxide semiconductor layer 4.
The side of the oxide semiconductor layer 4 in the region not covered by the recess 5a of source electrode 5 and drain electrode 6 in oxide semiconductor layer 4, is formed with recess 9c and 9d. Recess 9c and 9d can also only form any of which. It addition, in the manufacture process of semiconductor device 100C, accidentally (not being purposely) forms recess 9c and 9d sometimes.
Time in terms of the normal direction from first substrate 1 (not shown), if the distance between the source electrode 5 of the side clipping channel region 4c and drain electrode 6 is set to L, then the length Y2 of the channel width dimension (being perpendicular to the direction of II-II ' line) of the length X2 and recess 9c and 9d of the orientation (being parallel to the direction of II-II ' line) of recess 9c and 9d is separately more than 0 and for below L/2.
If so forming recess 9c and 9d, it becomes possible to reduce light and be irradiated to the region of oxide semiconductor layer 4 from the TFT10C side incidence of first substrate 1 (not shown). As a result of which it is, compared with the oxide semiconductor TFT not forming recess 9c and 9d, be more not easy the change of the TFT characteristic that generation causes because of light. And, oxide semiconductor layer 4 becomes big with the contact area of protective layer 7, increases it is thus possible, for instance supply the quantity delivered of the oxygen to oxide semiconductor layer 4 from the protective layer 7 containing aerobic such that it is able to prevent the oxygen defect of oxide semiconductor layer 4. If it addition, the above-mentioned respective length X2 of recess 9c and 9d, the Y2 characteristic more than L/2, TFT are possible to be deteriorated.
Fig. 6 indicates that the curve chart of grid voltage (Vg)-drain current (Id) curve of TFT10C. In the curve chart of Fig. 6, grid voltage (Vg)-drain current (Id) curve when curve C1 is to drive TFT10C under dark situation, grid voltage (Vg)-drain current (Id) curve when curve C2 is that (halogen light illumination: 4klx) drives TFT10C under bright ring border.
As can be seen from Figure 6, TFT10C is also the same with TFT10A, even if driving TFT under bright ring border, cut-off current also increases unlike TFT50, and threshold voltage also less moves to low voltage side. It addition, the TFT10C being formed with recess 9c and 9d is also the same with TFT10B (with reference to Fig. 4), the increase of cut-off current is few, and threshold voltage is also little to the movement of low voltage side.
Then, the semiconductor device 100D of the further embodiment of the present invention is described with reference to Fig. 7.
Fig. 7 (a) is the schematic plan view of semiconductor device 100D. Fig. 7 (b) is the schematic section of the semiconductor device 100D of the III-III ' line along Fig. 7 (a).
As shown in Fig. 7 (a) and Fig. 7 (b), semiconductor device 100D has first substrate 1 (such as glass substrate), forms TFT10D on the first substrate and form the protective layer 7 on TFT10D. TFT10D is such as oxide semiconductor TFT. TFT10D is the TFT checking distribution carrying out using when the electric-examination of semiconductor device 100D is looked into.Specifically, for instance at the peripheral part configuration inspection distribution of semiconductor device 100D, utilizing high voltage and high electric current, carry out the ON/OFF for the galvanoscopic signal of telecommunication, the electric-examination carrying out semiconductor device 100D is looked into. Utilize TFT10D, carry out the open/close switching of this signal of telecommunication. Above-mentioned TFT10A～10C is formed in viewing area, checks that the TFT10D of distribution is then such as formed at the neighboring area of the periphery of viewing area. TFT10D has gate electrode 2, form gate insulator 3 on gate electrode 2, the oxide semiconductor layer 4 of island that formed on gate insulator 3 and the source electrode 5 formed on oxide semiconductor layer 4 and drain electrode 6. Oxide semiconductor layer 4 has the first contact area 4a, the second contact area 4b and the channel region 4c between the first contact area 4a and the second contact area 4b. First contact area 4a and the second contact area 4b has multiple. Source electrode 5 and drain electrode 6 have comb teeth-shaped structure. Source electrode 5 is formed in the way of contacting with the first contact area 4a, and drain electrode 6 is formed in the way of contacting with the second contact area 4b. All sides of oxide semiconductor layer 4 are positioned on gate electrode 2. So, if all sides of oxide semiconductor layer 4 are positioned on gate electrode 2, then it is formed without the photomask disclosed in patent documentation 4, it becomes possible to the light that the side contrary with TFT10D side from first substrate 1 is incident is blocked, so that this light will not be irradiated to oxide semiconductor layer 4.
It is being perpendicular to first substrate 1 and along on the cross section of channel width dimension (direction being perpendicular to III-III ' line in Fig. 7 (a)) crosscut the first contact area 4a, the width w6 of source electrode 5 is more than the width w5 of oxide semiconductor layer 4. Equally, it is being perpendicular to first substrate 1 and along on the cross section of channel width dimension crosscut the second contact area 4b, the width w7 of drain electrode 6 is more than the width w5 of oxide semiconductor layer 4. It addition, in the surface of source electrode 5 capping oxide semiconductor layer 4, the side being positioned at channel width dimension of the first contact area 4a and the first contact area 4a. The side being positioned at channel width dimension in the surface of drain electrode 6 capping oxide semiconductor layer 4, the second contact area 4b and the second contact area 4b. It addition, in the surface of oxide semiconductor 4, all upper surfaces except the upper surface of channel region 4c and the side being positioned at channel width dimension of channel region 4c and side, covered by source electrode 5 or drain electrode 6. The side being positioned at channel width dimension of upper surface in the surface of oxide semiconductor layer 4, channel region 4c and channel region 4c, is covered by the dielectric film (such as protecting film 7) containing aerobic, and contacts with the dielectric film containing aerobic.
Time in terms of the normal direction from first substrate 1, the side in the direction (direction being perpendicular to III-III ' line in Fig. 7 (a)) that the channel direction with oxide semiconductor layer 4 of part in oxide semiconductor layer 4, that do not covered by source electrode 5 and drain electrode 6 is orthogonal, is formed with recess 9e and 9f. Recess 9e and 9f can also only form any of which. It addition, in the manufacture process of semiconductor device 100D, accidentally (not being purposely) forms recess 9e and 9f sometimes.
Time in terms of the normal direction from first substrate 1, if the distance between the source electrode 5 of the side clipping channel region 4c and drain electrode 6 is set to L, then the length Y3 of the length X3 of the orientation (direction being parallel to III-III ' line in Fig. 7 (a)) of recess 9e and 9f and channel width dimension (direction being perpendicular to III-III ' line in Fig. 7 (a)) is separately more than 0 and for below L/2.
When so forming recess 9e and 9f, it is possible to reduce the area being irradiated to the light of oxide semiconductor layer 4 from the TFT10D side incidence of first substrate 1. As a result of which it is, be not easy the change of the TFT characteristic that generation causes because of light. And, oxide semiconductor layer 4 becomes big with the contact area of protective layer 7, increases it is thus possible, for instance supply the quantity delivered of the oxygen to oxide semiconductor layer 4 from the protective layer 7 containing aerobic such that it is able to prevent the oxygen defect of oxide semiconductor layer 4. If it addition, the above-mentioned respective length X3 of recess 9e and 9f, Y3 are more than L/2, then the characteristic of TFT is possible to be deteriorated.
Then, with reference to Fig. 8, semiconductor device 100A～100D terminal 90A and 90B having is described.
Fig. 8 (a) is the schematic plan view of terminal 90A, and Fig. 8 (b) is the schematic plan view of terminal 90B. Fig. 8 (c) is the schematic section of terminal 90A, and Fig. 8 (d) is the schematic section of terminal 90B. Terminal 90A and 90B is the terminal of circuit and the semiconductor device 100A～100D such as connecting outside.
As shown in Fig. 8 (a) and Fig. 8 (c), terminal 90A is formed on first substrate 1. Terminal 90A has: the gate terminal portion 92 being formed from the same material with gate electrode 2, the gate insulator 3 formed in gate terminal portion 92, the oxide semiconductor layer 4 of island formed on gate insulator 3 and form the pixel electrode portion 98 on oxide semiconductor layer 4. Oxide semiconductor layer 4 contacts with pixel electrode portion 98. Pixel electrode portion 98 electrically connects with gate terminal portion 92 in the contact hole being formed at gate insulator 3.
As shown in Fig. 8 (b) and Fig. 8 (d), terminal 90B is formed on first substrate 1. Terminal 90B has the source terminal portion 95 being formed from the same material with source electrode 5 and forms the pixel electrode portion 98 in source terminal portion 95. Source terminal portion 95 electrically connects with pixel electrode portion 98. Pixel electrode portion 98 is such as formed by ITO (IndiumTinOxide: indium tin oxide).
Above, according to the embodiment of the present invention, it is possible to provide a kind of quantity not increasing manufacturing process just can manufacture and be not easy the semiconductor device causing the characteristic of TFT to change because of light.
Industrial applicability
The scope of application of the present invention is extremely wide, it is possible to be applicable to have the semiconductor device of TFT or have the electronic equipment of all spectra of this semiconductor device. Such as can be used in active array type LCD and organic EL display. Such display device such as can be used in the display screen etc. of the display picture of portable phone or portable game machine, digital camera. Thus, the present invention can be applicable to be provided with all electronic equipments of liquid crystal indicator or organic EL display.
The explanation of accompanying drawing labelling
1 substrate
2 gate electrodes
3 gate insulators
4 oxide semiconductor layers
4a the first contact area
4b the second contact area
4c channel region
5 source electrodes
6 drain electrodes
7 protective layers
10ATFT
100A semiconductor device
W1～w4 width

Claims (9)

1. a semiconductor device, it is characterised in that including:
Substrate;
Form gate electrode on the substrate;
Form the gate insulator on described gate electrode;
The oxide semiconductor layer of island, it is formed on described gate insulator, and has the first contact area and the second contact area and the channel region between described first contact area and described second contact area;
The source electrode formed in the way of contacting with described first contact area on described oxide semiconductor layer; With
The drain electrode formed in the way of contacting with described second contact area on described oxide semiconductor layer,
All sides of described oxide semiconductor layer are positioned on described gate electrode,
Be perpendicular to described substrate and along the cross section of the first contact area described in channel width dimension crosscut, the width of described source electrode more than the width of described oxide semiconductor layer,
Be perpendicular to described substrate and along the cross section of the second contact area described in channel width dimension crosscut, the width of described drain electrode more than the width of described oxide semiconductor layer,
In the surface of described oxide semiconductor layer, the upper surface of described channel region and the side being positioned at channel width dimension of described channel region are covered by the dielectric film containing aerobic, and contact with the described dielectric film containing aerobic,
Time in terms of the normal direction from described substrate, the part not covered by described source electrode and described drain electrode in described oxide semiconductor layer, there is the first recess or the first notch part,
Time in terms of the normal direction from described substrate, the width along channel width dimension of the part not covered by described source electrode and described drain electrode in described oxide semiconductor layer, less than being perpendicular to described substrate and along the width of the described source electrode in the cross section of the first contact area described in channel width dimension crosscut be perpendicular to described substrate and the width along the described drain electrode in the cross section of the second contact area described in channel width dimension crosscut.
2. semiconductor device as claimed in claim 1, it is characterised in that:
Described source electrode covers the side being positioned at channel width dimension of in the surface of described oxide semiconductor layer, described first contact area and described first contact area,
Described drain electrode covers the side being positioned at channel width dimension of in the surface of described oxide semiconductor layer, described second contact area and described second contact area.
3. semiconductor device as claimed in claim 1 or 2, it is characterised in that:
In the surface of described oxide semiconductor layer, all upper surfaces and side except the upper surface of described channel region and the side being positioned at channel width dimension of described channel region are covered by described source electrode or described drain electrode.
4. a semiconductor device, it is characterised in that including:
Substrate;
Form gate electrode on the substrate;
Form the gate insulator on described gate electrode;
The oxide semiconductor layer of island, it is formed on described gate insulator and has the first contact area and the second contact area and the channel region between described first contact area and described second contact area;
The source electrode formed in the way of contacting with described first contact area on described oxide semiconductor layer; With
The drain electrode formed in the way of contacting with described second contact area on described oxide semiconductor layer,
All sides of described oxide semiconductor layer are positioned on described gate electrode,
Region beyond the surface of the described channel region of described oxide semiconductor layer and side is covered by described source electrode and described drain electrode,
The region not covered by described source electrode and described drain electrode in described oxide semiconductor layer is covered by the dielectric film containing aerobic, and contacts with the described dielectric film containing aerobic,
Time in terms of the normal direction from described substrate, the part not covered by described source electrode and described drain electrode in described oxide semiconductor layer, there is the first recess or the first notch part,
Time in terms of the normal direction from described substrate, the width along channel width dimension of the part not covered by described source electrode and described drain electrode in described oxide semiconductor layer, less than being perpendicular to described substrate and along the width of the described source electrode in the cross section of the first contact area described in channel width dimension crosscut be perpendicular to described substrate and the width along the described drain electrode in the cross section of the second contact area described in channel width dimension crosscut.
5. the semiconductor device as described in claim 1 or 4, it is characterised in that:
Normal direction from described substrate, when distance between the described source electrode and described drain electrode of the side by clipping described channel region is set to L, the length of the orientation of described first recess or described first notch part and the length of channel width dimension are separately more than 0 and be below L/2.
6. the semiconductor device as described in claim 1 or 4, it is characterised in that:
The described dielectric film containing aerobic is by SiO2Formed.
7. the semiconductor device as described in claim 1 or 4, it is characterised in that:
Time in terms of the normal direction from described substrate, described source electrode has recess, and described drain electrode is positioned at described recess.
8. the semiconductor device as described in claim 1 or 4, it is characterised in that:
Described first contact area and described second contact area have multiple.
9. the semiconductor device as described in claim 1 or 4, it is characterised in that:
Described oxide semiconductor layer contains In, Ga and Zn.
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