TWI542016B - Thin film transistor and display panel - Google Patents

Description

Thin film transistor and display panel

The present invention relates to a thin film transistor and a display panel, and more particularly to a thin film transistor and display panel having electrostatic discharge protection.

During the manufacturing process of the display panel, when the operator (operator, machine or test instrument) such as an operator, machine or test instrument touches the display panel, the internal components of the display panel and the circuit may be subjected to electrostatic discharge (ESD). )damage. Therefore, an electrostatic protection circuit is generally designed in a non-display area of the display panel. Taking an active matrix display panel as an example, a static electricity protection circuit is usually formed on a substrate during the process of manufacturing a pixel array, and a pixel array is electrically connected to the static electricity protection circuit. In this way, when the display panel is subjected to an electrostatic discharge shock, the static electricity protection circuit can disperse and weaken the static electricity to prevent static electricity from directly impacting internal components and circuits in the display area.

However, when operating the display panel, the oxide semiconductor of its internal components may be affected by illumination, plasma processing, moisture, oxygen, etc., resulting in a critical operating voltage drift of the component. At this point, the pixel array active component (such as thin film transistor (thin film) Transistor, TFT)) can be used for circuit voltage design for threshold voltage compensation. Conversely, ESD protection circuit components (such as thin film transistors) generally do not have a compensation circuit for threshold voltage compensation. At this time, if the component threshold voltage drifts, the current may flow out through the static electricity protection circuit element during the operation of the display panel to cause a leakage current problem, thereby affecting the normal display of the display panel.

The present invention provides a thin film transistor that can improve leakage current problems.

The invention provides a display panel, wherein the static electricity protection circuit has the above-mentioned thin film transistor, so that when the threshold voltage of the active device drifts, the leakage current phenomenon can be reduced to maintain the display quality of the panel.

The present invention provides a thin film transistor comprising a gate, a source, a drain, and a channel layer. The channel layer is located between the gate and the source and drain. The channel layer has opposite first and second sidewalls. The gate overlaps the first sidewall and the gate does not overlap the second sidewall. The current flow length of the channel layer is X, the overlap length of the gate and the channel layer is X1, the non-overlapping length of the gate and the channel layer is X2, and X=X1+X2, where X1≧1/2X, and 0≦ X2≦1/2X.

The present invention provides another thin film transistor comprising a gate, a source, a drain, and a channel layer. The channel layer is located between the gate and the source and the drain, and the size of the gate is smaller than the size of the channel layer. The current flow length of the channel layer is X, the overlap length of the gate and the channel layer is X1, and the non-overlapping lengths of the gate and the channel layer on both sides of the gate are X2 and X3, respectively, and X=X1+X2+X3, Among them, X1≧1/3X, 0≦X2≦1/3X, and 0≦X3≦1/3X.

The present invention provides a display panel having a display area and a non-display area. The display panel includes a pixel array and an electrostatic protection circuit. The pixel array is located in the display area. The pixel array includes a plurality of pixel structures, and each of the pixel structures includes an active element and a pixel electrode electrically connected to the active element. The ESD protection circuit is located in the non-display area. The static electricity protection circuit includes at least one thin film transistor, wherein the thin film transistor is any of the above.

Based on the above, in the display panel of the present invention, the active elements of the pixel array and the thin film transistors of the electrostatic protection circuit have different structural designs. In this way, when the display panel is operated, if the threshold voltage of the active component of the pixel array drifts, the probability of current flowing out through the thin film transistor of the electrostatic protection circuit of different structures can be reduced, thereby improving the leakage current problem and maintaining the display quality of the panel. .

The above described features and advantages of the invention will be apparent from the following description.

100, 100a, 200, 200a, 300, 300a, 400, 400a‧‧‧ film transistor

120a‧‧‧first side wall

120b‧‧‧second side wall

190‧‧‧Protective layer

1000, 1000a, 2000, 2000a, 3000, 3000a, 4000, 4000a‧‧‧ display panels

1100‧‧‧Substrate

1200‧‧‧ pixel array

1220‧‧‧ pixel structure

1300‧‧‧First wire

1400‧‧‧second wire

1500‧‧‧Electrostatic protection circuit

1600‧‧‧gate driver

1700‧‧‧Source Driver

A‧‧‧ display area

B‧‧‧Non-display area

A-A’, B-B’‧‧‧ line

CH1, CH2, CH3, CH4, 120‧‧‧ channel layer

D, D1, D2, D3, D4‧‧‧ bungee

ES1, 140‧‧‧etch stop layer

G, G1, G2, G3, G4‧‧‧ gate

GI1, GI‧‧‧ gate insulation

L1, L2, L3, L4, X, X1, X2, X3, Y, Y1, Y2, Y3, Z, Z1, Z2, Z3‧‧‧ length

PE‧‧‧ pixel electrode

PV‧‧‧Insulation

S, S1, S2, S3, S4‧‧‧ source

T1, T2, T3, T4‧‧‧ active components

W, W1, W2, 162, 164‧‧ ‧ contact window opening

1 is a top plan view of a display panel in accordance with an embodiment of the present invention.

2 is a schematic cross-sectional view of a display panel in accordance with a first embodiment of the present invention.

3 is a cross-sectional view of another display panel in accordance with a first embodiment of the present invention.

4 is a cross-sectional view of a display panel in accordance with a second embodiment of the present invention.

Figure 5 is a cross-sectional view showing another display panel in accordance with a second embodiment of the present invention.

Figure 6 is a cross-sectional view showing a display panel in accordance with a third embodiment of the present invention.

Figure 7 is a cross-sectional view showing another display panel in accordance with a third embodiment of the present invention.

Figure 8 is a cross-sectional view showing a display panel in accordance with a fourth embodiment of the present invention.

Figure 9 is a cross-sectional view showing another display panel in accordance with a fourth embodiment of the present invention.

1 is a top plan view of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 1, the display panel 1000 has a display area A and a non-display area B. The non-display area B is located outside the display area A, and is also called a peripheral line area. The display panel 1000 includes a substrate 1100, a pixel array 1200, a plurality of first wires 1300, a plurality of second wires 1400, a plurality of static electricity protection circuits 1500, a plurality of gate drivers 1600, and a plurality of source drivers 1700. The display panel 1000 may be a liquid crystal display panel or an organic light-emitting call display panel, but the invention is not limited thereto.

In terms of optical characteristics, the substrate 1100 can be a light transmissive substrate or an opaque/reflective substrate. The material of the light transmissive substrate may be selected from the group consisting of glass, quartz, organic polymers, other suitable materials, or a combination thereof. The material of the opaque/reflective substrate may be selected from conductive materials, metals, wafers, ceramics, other suitable materials, or combinations thereof. It should be noted that, when a conductive material is selected for the substrate 1100, before the substrate 1100 is mounted with the thin film transistor. An insulating layer (not shown) is formed on the substrate 1100 to avoid the problem of short circuit between the substrate 1100 and the members of the thin film transistor.

The pixel array 1200 is located in the display area A. The pixel array 1200 includes a plurality of pixel structures 1220. The array of pixel structures 1220 is arranged on the substrate 1100. Each pixel structure 1220 can include at least one active component T1 and at least one pixel electrode PE, wherein the pixel electrode PE is electrically connected to the active component T1. The gate driver 1600 and the source driver 1700 respectively generate a scan signal and a data signal to drive the display panel 1000, thereby causing the display panel 1000 to display an image frame.

As shown in FIG. 1 , a plurality of first wires 1300 are disposed on the substrate 1100 and located in the display area A. The first wires 1300 are electrically connected to the pixel structure 1220 and extend to the non-display area B, wherein the first wires are 1300 is, for example, a signal line, and the signal line can be a scan line or a data line. A plurality of second wires 1400 are disposed on the substrate 1100 and located in the non-display area B, wherein the second wires 1400 are, for example, short-circuit bars. In detail, the second wire 1400 may span the first wires 1300, and the second wires 1400 are separated from the first wires 1300 and are not connected to each other.

In addition, a plurality of static electricity protection circuits 1500 are disposed on the substrate 1100 and located in the non-display area B. The static electricity protection circuit 1500 is electrically connected to the first wire 1300 and the second wire 1400. For example, each static electricity protection circuit 1500 is located between each of the first wires 1300 and each of the second wires 1400. Electrostatic protection circuit 1500 can include at least one thin film transistor in accordance with some embodiments of the present invention. In this embodiment, the static electricity protection circuit 1500 includes at least one thin film transistor 100, but the present invention Not limited to this. Each embodiment of the thin film transistor that can be included in the static electricity protection circuit 1500 will be described in detail below with reference to the drawings.

2 is a schematic cross-sectional view of a display panel in accordance with a first embodiment of the present invention. Referring to FIG. 1 and FIG. 2 simultaneously, the portion defined by the line AA' of FIG. 2 represents the cross section of the pixel structure 1220 in the display panel 1000 of FIG. 1, and the portion defined by the line BB' of FIG. 2 represents the FIG. The static electricity protection circuit 1500 in the display panel 1000 is cross-sectioned. In the present embodiment, the active device T1 of the pixel structure 1220 can be fabricated simultaneously with the thin film transistor 100 of the static electricity protection circuit 1500, but the invention is not limited thereto.

Referring first to the portion defined by line A-A' in Fig. 2, the active device T1 of the pixel structure 1220 includes a gate G1, a channel layer CH1, an etch stop layer ES1, a source S1, and a drain D1.

The gate G1 is located on the substrate 1100. The gate G1 is generally a metal material, but the invention is not limited thereto. In other embodiments, the gate G1 may also use other conductive materials (such as alloys, metal nitrides, metal oxides, metal oxynitrides, etc.) or a stacked layer of metal and other conductive materials.

A gate insulating layer GI1 can be formed on the gate G1. The material of the gate insulating layer GI1 may be selected from inorganic materials (such as yttria, tantalum nitride, ytterbium oxynitride, other suitable materials or stacked layers of at least two of the above materials), organic materials (for example: photoresist, benzocyclobutene) A benzocyclobutene (BCB) polymer, a polyimide (PI) or other suitable material or a stacked layer of at least two of the above materials) or a combination of the above. In the present embodiment, the gate insulating layer GI1 can comprehensively cover the gate G1 and the substrate 1100, but the present invention is not limited thereto.

The channel layer CH1 is formed on the gate insulating layer GI and is located between the gate G and the source S and the drain D. The channel layer CH1 may be a single layer or a multilayer structure, and its material may be selected from amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium, metal oxide semiconductor materials, other suitable materials, or a combination thereof. In this embodiment, the material of the channel layer CH1 is preferably a metal oxide semiconductor material, which is selected, for example, from Indium-Gallium-Zinc Oxide (IGZO), zinc oxide (ZnO), and tin oxide (SnO). Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO), Indium-Tin Oxide (ITO) or the above The combination of the invention is not limited thereto.

An etch stop layer ES1 is formed on the channel layer CH1. The etch stop layer ES1 is located above the channel layer CH1 and below the source S1 and the drain D1. The size of the etch stop layer ES1 is smaller than the size of the channel layer CH1 to expose a portion of the channel layer CH1. The source S1 and the drain D1 are located on the etch stop layer ES1 and are in direct contact with the exposed channel layer CH1.

The protective layer 190 is formed on the substrate 1100 and covers the source S1 and the drain D1. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material. The pixel electrode PE is formed over the protective layer 190, and the pixel electrode PE is directly connected to the drain D1 through the contact opening W.

The size of the gate G1 of the active device T1 is larger than the size of the channel layer CH1. In addition, the overlap length L1 of the gate G1 of the active device T1 and the channel layer CH1 is substantially the same as the current flow length of the channel layer CH1 of the active device T1.

Next, please refer to the portion defined by line B-B' in Fig. 2, the electrostatic protection circuit The thin film transistor 100 of 1500 includes a gate G, a source S, a drain D, and a channel layer 120. Similar components of the thin film transistor 100 and the active element T1 are denoted by like symbols.

The gate G is located on the substrate 1100. The gate G is generally a metal material, but the invention is not limited thereto. In other embodiments, the gate G may also use other conductive materials (such as alloys, metal nitrides, metal oxides, metal oxynitrides, etc.) or a stacked layer of metal and other conductive materials.

A gate insulating layer GI can be formed on the gate G. The material of the gate insulating layer GI may be selected from inorganic materials (for example, tantalum oxide, tantalum nitride, niobium oxynitride, other suitable materials or stacked layers of at least two materials mentioned above), organic materials (for example: photoresist, benzocyclobutene) A benzocyclobutene (BCB) polymer, a polyimide (PI) or other suitable material or a stacked layer of at least two of the above materials) or a combination of the above. In the present embodiment, the gate insulating layer GI can cover the gate G and the substrate 1100 in a comprehensive manner, but the present invention is not limited thereto.

The channel layer 120 is formed on the gate insulating layer GI and is located between the gate G and the source S and the drain D. The channel layer 120 may be a single layer or a multilayer structure, and its material may be selected from amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium, metal oxide semiconductor materials, other suitable materials, or a combination thereof. In this embodiment, the material of the channel layer 120 is preferably a metal oxide semiconductor material, which is selected, for example, from indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), and indium zinc oxide (IZO). , gallium zinc oxide (GZO), zinc tin oxide (ZTO), indium tin oxide (ITO) or a combination thereof, but the invention is not limited thereto.

It is worth mentioning that the channel layer 120 has a first sidewall 120a and a second sidewall 120b disposed opposite each other, as shown in the cross-sectional view of FIG. In the present embodiment, the gate G overlaps with the first sidewall 120a, and the gate G does not overlap the second sidewall 120b. Compared with the active device T1, the current flowing length of the channel layer 120 is X, the overlapping length of the gate G and the channel layer 120 is X1, and the non-overlapping length of the gate G and the channel layer 120 is X2, and X=X1+ X2. From the viewpoint of the threshold voltage drift tolerance of the active element T1, X1 ≧ 1/2X, and 0 ≦ X2 ≦ 1/2X, more preferably X2 is less than 2 μm, but the present invention is not limited thereto.

As shown in FIG. 2, the thin film transistor 100 further includes an etch stop layer 140. The etch stop layer 140 is located above the channel layer 120 and below the source S and the drain D. The size of the etch stop layer 140 is smaller than the size of the channel layer 120 to expose portions of the channel layer 120. The source S and the drain D are located on the etch stop layer 140 and are in contact with the exposed via layer 120. The material of the etch stop layer 140 may be selected from the materials described in the gate insulating layer GI. Therefore, when the voltage/current is to flow through the channel layer 120, since the etch stop layer 140 is not a conductor or a semiconductor material, the direct contact between the source S and the drain D and the channel layer 120 is a starting point. The width of the etch stop layer 140 can be regarded as the current flow length X.

The protective layer 190 is formed on the substrate 1100 and covers the source S and the drain D. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material.

In this embodiment, the active device T1 of the pixel structure 1220 is a metal oxide thin film transistor, and the thin film transistor 100 of the static electricity protection circuit 1500 is another metal oxide thin film transistor, which have different structural designs. . herein In the embodiment, the thin film transistor 100 of the static electricity protection circuit 1500 does not have a pixel electrode, and no pixel electrode is directly connected to the drain D through the contact window. However, the active element T1 of the pixel structure 1220 has the pixel electrode PE present, and the pixel electrode PE is directly connected to the drain D1 via the contact window W, wherein the other two are different as described above. Again, rumors. In this way, when the display panel 1000 is operated, if the threshold voltage of the active component T1 of the pixel structure 1220 is drifted, the thin film transistor 100 of the static electricity protection circuit 1500 can reduce the probability of current flowing out through the static electricity protection circuit 1500, thereby improving the leakage current problem. In order to maintain the display quality of the display panel 1000.

3 is a cross-sectional view of another display panel in accordance with a first embodiment of the present invention. The portion defined by the line AA' of FIG. 3 represents a cross section of the pixel structure (for example, the pixel structure 1220 in the display panel 1000 of FIG. 1) in the display panel 1000a, and the portion indicated by the line BB' of FIG. The electrostatic protection circuit profile in the display panel 1000a (for example, the static electricity protection circuit 1500 in the display panel 1000 of FIG. 1). In the present embodiment, the active element T1 of the pixel structure can be fabricated simultaneously with the thin film transistor 100a of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 1000a is similar to the display panel 1000 of FIG. 2, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. The difference between the display panel 1000a and the display panel 1000 lies in the structure of the thin film transistor 100a of the static electricity protection circuit.

As shown in FIG. 3, the thin film transistor 100a includes a gate G, a source S, a drain D, and a channel layer 120. Similarly, the channel layer 120 is located between the gate insulating layer GI above the gate G and the source S and the drain D. The etch stop layer 140 is located on the channel layer Above 120 is below source S and drain D. The size of the etch stop layer 140 is smaller than the size of the channel layer 120 to expose portions of the channel layer 120. The source S and the drain D are located on the etch stop layer 140 and are in direct contact with the exposed channel layer 120. The size of the gate G of the thin film transistor 100a is smaller than the size of the channel layer 120 compared to the active element T1. The current flow length of the channel layer 120 is X, the overlap length of the gate G and the channel layer 120 is X1, and the non-overlapping lengths of the gate G and the channel layer 120 on both sides of the gate G are X2 and X3, respectively, and X= X1+X2+X3. From the viewpoint of the threshold voltage drift tolerance of the active element T1, X1 ≧ 1/3X, 0 ≦ X2 ≦ 1/3X, and 0 ≦ X3 ≦ 1/3X. More preferably, X2 is less than 2 microns, and X3 is less than 2 microns, although the invention is not limited thereto. X2 and X3 can be the same or different.

The protective layer 190 is formed on the substrate 1100 and covers the source S and the drain D. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material.

Similarly, in this embodiment, the active element T1 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 100a of the electrostatic protection circuit is another metal oxide thin film transistor, which have different structures. design. In this way, when the display panel 1000a is operated, if the threshold voltage of the active component T1 of the pixel structure drifts, the thin film transistor 100a of the electrostatic protection circuit can reduce the probability of current flowing out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain The display quality of the display panel 1000a.

4 is a cross-sectional view of a display panel in accordance with a second embodiment of the present invention. The portion defined by the line A-A' of Fig. 4 represents a cross section of the pixel structure (e.g., the pixel structure 1220 in the display panel 1000 of Fig. 1) in the display panel 2000, and the line of Fig. 4 The portion defined by B-B' represents a cross section of the static electricity protection circuit in the display panel 2000 (for example, the static electricity protection circuit 1500 in the display panel 1000 of Fig. 1). In the present embodiment, the active element T2 of the pixel structure can be fabricated simultaneously with the thin film transistor 200 of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 2000 is similar to the display panel 1000 of FIG. 2, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.

Referring first to the portion defined by line A-A' in Fig. 4, the active element T2 of the pixel structure includes a gate G2, a channel layer CH2, an insulating layer PV, a source S2, and a drain D2. The active element T2 is similar to the active element T1, and therefore the same or similar elements are denoted by the same or similar symbols, and the description is not repeated. The difference between the active device T2 and the active device T1 is that an insulating layer PV is formed on the channel layer CH2 of the active device T2. The insulating layer PV is located above the channel layer CH2 and below the source S2 and the drain D2. The insulating layer PV has a plurality of contact window openings W1, W2 to expose the channel layer CH2. The source S2 and the drain D2 are located on the insulating layer PV, and the source S2 and the drain D2 pass through the contact window openings W1, W2 to be in direct contact with the channel layer CH2, respectively.

The protective layer 190 is formed on the substrate 1100 and covers the source S2 and the drain D2. The pixel electrode PE is formed over the protective layer 190. The pixel electrode PE is in direct contact with the drain D2 through the contact opening W.

The size of the gate G2 of the active device T2 is larger than the size of the channel layer CH2. In addition, the overlap length L2 of the gate G2 of the active device T2 and the channel layer CH2 is the same as the current flow length of the channel layer CH2 of the active device T2, that is, the width of the channel layer CH2, as shown in FIG.

Next, referring to the portion defined by line B-B' in Fig. 4, the thin film transistor 200 of the static electricity protection circuit includes a gate G, a source S, a drain D, and a channel layer 120. Similarly, the channel layer 120 is located between the gate G and the source S and the drain D. The channel layer 120 has a first sidewall 120a and a second sidewall 120b disposed opposite each other, as shown in FIG. In the present embodiment, the gate G overlaps with the first sidewall 120a, and the gate G does not overlap the second sidewall 120b. Compared with the active device T2, the current flowing length of the channel layer 120 is X, the overlapping length of the gate G and the channel layer 120 is X1, and the non-overlapping length of the gate G and the channel layer 120 is X2, X=X1+X2. From the viewpoint of the threshold voltage drift tolerance of the active element T2, X1 ≧ 1/2X, and 0 ≦ X2 ≦ 1/2X, more preferably X2 is less than 2 μm, but the present invention is not limited thereto.

As shown in FIG. 4, the thin film transistor 200 further includes an insulating layer 160. The insulating layer 160 is located above the channel layer 120 and below the source S and the drain D. More specifically, the channel layer 120 is above the gate G and the insulating layer 160 is above the channel layer 120. The insulating layer 160 has a plurality of contact openings 162, 164 to expose the channel layer 120. The source S and the drain D are located on the insulating layer 160, and the source S and the drain D pass through the contact openings 162, 164 to be in direct contact with the channel layer 120.

In this embodiment, the active element T2 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 200 of the electrostatic protection circuit is another metal oxide thin film transistor, which have different structural designs. In this embodiment, the thin film transistor 200 of the static electricity protection circuit 1500 does not have a pixel electrode, and no pixel electrode is directly connected to the drain D through the contact window. However, the active element T2 of the pixel structure 1220 has the pixel electrode PE present, and the pixel electrode PE is in contact The window W is directly connected to the drain D2 as an example, wherein the other two are different as described above, and it is no longer ambiguous. In this way, when the display panel 2000 is operated, if the threshold voltage of the active component T2 of the pixel structure drifts, the thin film transistor 200 of the electrostatic protection circuit can reduce the probability of current flowing out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain The display quality of the display panel 2000.

Figure 5 is a cross-sectional view showing another display panel in accordance with a second embodiment of the present invention. A portion defined by a line A-A' of FIG. 5 indicates a cross section of a pixel structure (for example, a pixel structure 1220 in the display panel 1000 of FIG. 1) in the display panel 2000a, and a portion indicated by a line BB' of FIG. The electrostatic protection circuit profile in the display panel 2000a (for example, the static electricity protection circuit 1500 in the display panel 1000 of FIG. 1). In the present embodiment, the active element T2 of the pixel structure can be fabricated simultaneously with the thin film transistor 200a of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 2000a is similar to the display panel 2000 of FIG. 4, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.

As shown in FIG. 5, the difference between the active element T2 of the pixel structure and the active element T1 of the first embodiment is that an insulating layer PV is formed on the channel layer CH2 of the active element T2. The insulating layer PV is located above the channel layer CH2 and below the source S2 and the drain D2. The insulating layer PV has a plurality of contact window openings W1, W2 to expose the channel layer CH2. The source S2 and the drain D2 are located on the insulating layer PV, and the source S2 and the drain D2 pass through the contact window openings W1, W2 to be in direct contact with the channel layer CH2, respectively. Similarly, the size of the gate G2 of the active device T2 is larger than the size of the channel layer CH2. In addition, the overlap length L2 of the gate G2 of the active device T2 and the channel layer CH2 is opposite to the main The current flowing through the channel layer CH2 of the moving element T2 has the same length.

As shown in FIG. 5, the thin film transistor 200a of the static electricity protection circuit includes a gate G, a source S, a drain D, and a channel layer 120. Similarly, the channel layer 120 is located between the gate G and the source S and the drain D. The size of the gate G of the thin film transistor 200a is smaller than the size of the channel layer 120 compared to the active element T2. The current flow length of the channel layer 120 is X, the overlap length of the gate G and the channel layer 120 is X1, and the non-overlapping lengths of the gate G and the channel layer 120 on both sides of the gate G are X2 and X3, respectively, and X= X1+X2+X3. From the viewpoint of the threshold voltage drift tolerance of the active element T2, X1 ≧ 1/3X, 0 ≦ X2 ≦ 1/3X, and 0 ≦ X3 ≦ 1/3X. More preferably, X2 is less than 2 microns, and X3 is less than 2 microns, although the invention is not limited thereto. X2 and X3 can be the same or different.

The protective layer 190 is formed on the substrate 1100 and covers the source S and the drain D. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material.

Similarly, in this embodiment, the active element T2 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 200a of the static protection circuit is another metal oxide thin film transistor, which have different structures. design. In this way, when the display panel 2000a is operated, if the threshold voltage of the active component T2 of the pixel structure drifts, the thin film transistor 200a of the electrostatic protection circuit can reduce the probability of current flowing out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain The display quality of the display panel 2000a.

Figure 6 is a cross-sectional view showing a display panel in accordance with a third embodiment of the present invention. The portion defined by the line A-A' of Fig. 6 indicates the pixel structure in the display panel 3000 (example) As shown in the cross section of the pixel structure 1220 in the display panel 1000 of FIG. 1, the portion defined by the line BB' of FIG. 6 represents the electrostatic protection circuit profile in the display panel 3000 (for example, the static electricity in the display panel 1000 of FIG. Protection circuit 1500). In the present embodiment, the active element T3 of the pixel structure can be fabricated simultaneously with the thin film transistor 300 of the static electricity protection circuit, but the invention is not limited thereto. The display panel 3000 is similar to the display panel 1000 of FIG. 2, and therefore the same or similar elements are denoted by the same or similar symbols, and the description is not repeated.

Referring first to the portion defined by line A-A' in Fig. 6, the active element T3 of the pixel structure includes a gate G3, a channel layer CH3, a source S3, and a drain D3. The active component T3 is similar to the active component T1 of FIG. 4, and therefore the same or similar components are denoted by the same or similar symbols, and the description thereof will not be repeated. The difference between the active device T3 and the active device T1 is that there is no other film layer between the channel layer CH3 of the active device T3 and the source S3 and the drain D3. In other words, the source S3 and the drain D3 do not need to pass through the opening and directly contact the channel layer CH3.

The protective layer 190 is formed on the substrate 1100 and covers the source S3 and the drain D3. The pixel electrode PE is formed over the protective layer 190. The pixel electrode PE is electrically connected to the drain D3 through the contact window opening W.

The size of the gate G3 of the active device T3 is larger than the size of the channel layer CH3. In addition, the overlap length L3 of the gate G3 of the active device T3 and the channel layer CH3 is the same as the current flow length of the channel layer CH3 of the active device T3.

Next, referring to the portion defined by line B-B' in Fig. 6, the thin film transistor 300 of the static electricity protection circuit includes a gate G, a source S, a drain D, and a channel layer 120. The difference between the thin film transistor 300 and the thin film transistor 100 is that the channel layer 120 of the thin film transistor 300 is located between the gate G and the source S and the drain D, and the channel layer 120 and the source S and the drain D There are no other film layers (such as etch stop layers or insulating layers, etc.) between them. In other words, the source S and the drain D do not directly pass through the opening and are in direct contact with the channel layer 120. The channel layer 120 has a first sidewall 120a and a second sidewall 120b disposed opposite each other, as shown in FIG. In the present embodiment, the gate G overlaps with the first sidewall 120a, and the gate G does not overlap the second sidewall 120b. It is worth mentioning that the current flowing length of the channel layer 120 is Y, the overlapping length of the gate G and the channel layer 120 is Y1, and the non-overlapping length of the gate G and the channel layer 120 is Y2, Y=Y1+Y2. From the viewpoint of the threshold voltage drift tolerance of the active element T3, Y1 ≧ 1/2Y, and 0 ≦ Y2 ≦ 1/2Y, more preferably Y2 is less than 2 μm, but the present invention is not limited thereto.

In this embodiment, the active element T3 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 300 of the static electricity protection circuit is another metal oxide thin film transistor, which have different structural designs. In this way, when the display panel 3000 is operated, if the threshold voltage of the active component T3 of the pixel structure drifts, the thin film transistor 300 of the static electricity protection circuit can reduce the probability of current flowing out through the static electricity protection circuit, thereby improving the leakage current problem to maintain The display quality of the display panel 3000.

Figure 7 is a cross-sectional view showing another display panel in accordance with a third embodiment of the present invention. The portion defined by the line A-A' of Fig. 7 represents a cross-sectional view of the pixel structure (e.g., the pixel structure 1220 in the display panel 1000 of Fig. 1) in the display panel 3000a, Fig. 7 The portion defined by the line B-B' represents a cross section of the static electricity protection circuit in the display panel 3000a (for example, the static electricity protection circuit 1500 in the display panel 1000 of Fig. 1). In the present embodiment, the active element T3 of the pixel structure can be fabricated simultaneously with the thin film transistor 300a of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 3000a is similar to the display panel 3000 of FIG. 6, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. The difference between the display panel 3000a and the display panel 3000 lies in the structure of the thin film transistor 300a of the static electricity protection circuit.

As shown in FIG. 7, the thin film transistor 300a of the pixel structure includes a gate G, a source S, a drain D, and a channel layer 120. Similarly, the channel layer 120 is located between the gate G and the source S and the drain D. The size of the gate G of the thin film transistor 300a is smaller than the size of the channel layer 120 compared to the active element T3. The current flowing length of the channel layer 120 is Y, the overlapping length of the gate G and the channel layer 120 is Y1, and the non-overlapping lengths of the gate G and the channel layer 120 on both sides of the gate G are Y2 and Y3, respectively, and Y= Y1+Y2+Y3. From the viewpoint of the threshold voltage drift tolerance of the active element T3, Y1 ≧ 1/3Y, 0 ≦ Y2 ≦ 1/3Y, and 0 ≦ Y3 ≦ 1/3Y. More preferably, Y2 is less than 2 microns, and Y3 is less than 2 microns, although the invention is not limited thereto. Y2 and Y3 may be the same or different.

The protective layer 190 is formed on the substrate 1100 and covers the source S and the drain D. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material.

Similarly, in this embodiment, the active element T3 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 300a of the electrostatic protection circuit is another metal oxide thin film transistor, which have different structures. design. Such a When the display panel 3000a is operated, if the threshold voltage of the active component T3 of the pixel structure is drifted, the thin film transistor 300a of the electrostatic protection circuit can reduce the probability that the current flows out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain the display panel. 3000a display quality.

Figure 8 is a cross-sectional view showing a display panel in accordance with a fourth embodiment of the present invention. The portion defined by the line AA' of FIG. 8 represents a cross section of the pixel structure (for example, the pixel structure 1220 in the display panel 1000 of FIG. 1) in the display panel 4000, and the portion indicated by the line BB' of FIG. The electrostatic protection circuit profile in the display panel 4000 (for example, the static electricity protection circuit 1500 in the display panel 1000 of FIG. 1). In the present embodiment, the active element T4 of the pixel structure can be fabricated simultaneously with the thin film transistor 400 of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 4000 is similar to the display panel 1000 of FIG. 2, and therefore the same or similar elements are denoted by the same or similar symbols, and the description is not repeated.

Referring first to the portion defined by line A-A' in Fig. 8, the active element T4 of the pixel structure includes a gate G4, a channel layer CH4, a source S4, and a drain D4. The active element T4 is similar to the active element T1 of FIG. 4, and therefore the same or similar elements are denoted by the same or similar symbols, and the description is not repeated. The difference between the active device T4 and the active device T1 is that the source S4 and the drain D4 of the active device T4 are located above the gate G4, and the channel layer CH4 covers the source S4 and the drain D4 so that the source S4 and the gate The pole D4 is in direct contact with the channel layer CH4.

The protective layer 190 is formed on the substrate 1100 and covers the source S2 and the drain D2. The pixel electrode PE is formed over the protective layer 190. Pixel electrode PE through contact The window opening W is electrically connected to the drain D2.

The size of the gate G4 of the active device T4 is larger than the size of the channel layer CH4. In addition, the overlap length L4 of the gate G4 of the active device T3 and the channel layer CH4 is the same as the current flow length of the channel layer CH4 of the active device T4.

Next, referring to the portion defined by line B-B' in Fig. 8, the thin film transistor 400 of the static electricity protection circuit includes a gate G, a source S, a drain D, and a channel layer 120. The difference between the thin film transistor 400 and the thin film transistor 100 is that the source S and the drain D of the thin film transistor 400 are located above the gate G, and the channel layer 120 covers the source S and the drain D to make the source S and drain D are in direct contact with channel layer 120. Similarly, the channel layer 120 has a first sidewall 120a and a second sidewall 120b disposed opposite each other. In the present embodiment, the gate G overlaps with the first sidewall 120a, and the gate G does not overlap the second sidewall 120b. Compared with the active device T4, the current flowing length of the channel layer 120 is Z, the overlapping length of the gate G and the channel layer 120 is Z1, and the non-overlapping length of the gate G and the channel layer 120 is Z2, Z=Z1+Z2. From the viewpoint of the threshold voltage drift tolerance of the active element T, Z1 ≧ 1/2Z, and 0 ≦ Z2 ≦ 1/2Z, more preferably Z2 is less than 2 μm, but the present invention is not limited thereto.

In this embodiment, the active element T4 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 400 of the static electricity protection circuit is another metal oxide thin film transistor, which have different structural designs. In this way, when the display panel 4000 is operated, if the threshold voltage of the active component T4 of the pixel structure drifts, the thin film transistor 400 of the electrostatic protection circuit can reduce the probability of current flowing out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain Display panel 4000 display quality.

Figure 9 is a cross-sectional view showing another display panel in accordance with a fourth embodiment of the present invention. The portion defined by the line AA' of FIG. 9 represents a cross-sectional view of the pixel structure (for example, the pixel structure 1220 in the display panel 1000 of FIG. 1) in the display panel 4000a, and the portion indicated by the line BB' of FIG. The electrostatic protection circuit profile in the display panel 4000a (for example, the static electricity protection circuit 1500 in the display panel 1000 of FIG. 1). In the present embodiment, the active element T4 of the pixel structure can be fabricated simultaneously with the thin film transistor 400a of the electrostatic protection circuit, but the invention is not limited thereto. The display panel 4000a is similar to the display panel 4000 of FIG. 8, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. The difference between the display panel 4000a and the display panel 4000 lies in the structure of the thin film transistor 400a of the static electricity protection circuit.

As shown in FIG. 9, the thin film transistor 400a of the static electricity protection circuit includes a gate G, a source S, a drain D, and a channel layer 120. Similarly, the source S and the drain D are located above the gate insulating layer GI on both sides of the gate G, and the channel layer 120 covers the source S and the drain D so that the source S and the drain D and the channel layer 120 are directly contact. The size of the gate G of the thin film transistor 400a is smaller than the size of the channel layer 120 compared to the active element T4. The current flowing length of the channel layer 120 is Z, the overlapping length of the gate G and the channel layer 120 is Z1, and the non-overlapping lengths of the gate G and the channel layer 120 on both sides of the gate G are respectively Z2 and Z3, and Z= Z1+Z2+Z3. From the viewpoint of the threshold voltage drift tolerance of the active element T, Z1 ≧ 1/3Z, 0 ≦ Z2 ≦ 1/3Z, and 0 ≦ Z3 ≦ 1/3Z. More preferably, Z2 is less than 2 microns, and Z3 is less than 2 microns, although the invention is not limited thereto. Z2 and Z3 can be the same or different.

The protective layer 190 is formed on the substrate 1100 and covers the source S and the drain D. The invention does not limit the material of the protective layer 190, which may be any suitable insulating material.

Similarly, in this embodiment, the active element T4 of the pixel structure is a metal oxide thin film transistor, and the thin film transistor 400a of the electrostatic protection circuit is another metal oxide thin film transistor, which have different structures. design. In this way, when the display panel 4000 is operated, if the threshold voltage of the active component T4 of the pixel structure drifts, the thin film transistor 400a of the electrostatic protection circuit can reduce the probability of current flowing out through the electrostatic protection circuit, thereby improving the leakage current problem to maintain The display quality of the display panel 4000.

In summary, in the display panel of the present invention, the active elements of the pixel array and the thin film transistors of the electrostatic protection circuit have different structural designs. In this way, when the display panel is operated, if the threshold voltage of the active component of the pixel array drifts, the probability of current flowing through the thin film transistor of the electrostatic protection circuit with different structures can be reduced, thereby improving the leakage current problem and maintaining the panel. Display quality. In addition, the display panel of the present invention can design the active elements of the thin film transistor and the pixel array of the above-mentioned electrostatic protection circuit with different structures without changing the process steps.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧film transistor

120a‧‧‧first side wall

120b‧‧‧second side wall

190‧‧‧Protective layer

1000‧‧‧ display panel

1100‧‧‧Substrate

A-A’, B-B’‧‧‧ line

CH1, 120‧‧‧ channel layer

D, D1‧‧‧ bungee

ES1, 140‧‧‧etch stop layer

G, G1‧‧‧ gate

GI, GI1‧‧‧ gate insulation

L1, X, X1, X2‧‧‧ length

PE‧‧‧ pixel electrode

S, S1‧‧‧ source

T1‧‧‧ active components

W‧‧‧Contact window opening

Claims (10)

A thin film transistor comprising: a gate; a source and a drain, wherein the source and the drain are not in contact with the gate; and a channel layer at the gate and the source and the gate Between the poles, the channel layer has a first sidewall and a second sidewall disposed opposite to each other, the gate overlaps the first sidewall, and the gate does not overlap with the second sidewall, wherein one of the channel layers The current flow length is X, the gate overlaps with one of the channel layers by a length X1, and the gate does not overlap with one of the channel layers by a length of X2, and X=X1+X2, where X1≧1/2X, And 0≦X2≦1/2X. The thin film transistor of claim 1, wherein X2 is less than 2 microns. The thin film transistor of claim 1, further comprising an etch stop layer, wherein: the channel layer is above the gate, the etch stop layer is above the channel layer, and the length of the etch stop layer The channel layer is less than the length of the channel layer to expose a portion of the channel layer, and the source and the drain are on the etch stop layer and are in contact with the exposed channel layer. The thin film transistor according to claim 1, further comprising an insulation a layer, wherein: the channel layer is above the gate, the insulating layer is above the channel layer, and the insulating layer has a plurality of contact openings to expose the channel layer, and the source and the drain are located On the insulating layer, the source and the drain pass through the contact openings to contact the channel layer. The thin film transistor of claim 1, wherein the channel layer is above the gate, and the source and the drain cover the channel layer to contact the channel layer. The thin film transistor of claim 1, wherein the source and the drain are located above the gate, and the channel layer covers the source and the drain to contact the channel layer. A thin film transistor comprising: a gate; a source and a drain; a channel layer between the gate and the source and the drain, and the length of the gate is less than the length of the channel layer The current flowing through the length of one of the channel layers is X, the length of the gate overlaps with one of the channel layers is X1, and the length of the gate and the channel layer on both sides of the gate are respectively X2 and X3, and X = X1 + X2 + X3, wherein X1 ≧ 1/3X, 0 < X2 ≦ 1/3X, and 0 ≦ X3 ≦ 1/3X, and the overlap length is a continuous uninterrupted length. The thin film transistor of claim 7, further comprising an etch stop layer, wherein: the channel layer is above the gate, the etch stop layer is above the channel layer, and the length of the etch stop layer The channel layer is less than the length of the channel layer to expose a portion of the channel layer, and the source and the drain are on the etch stop layer and are in contact with the exposed channel layer. The thin film transistor of claim 7, further comprising an insulating layer, wherein: the channel layer is above the gate, the insulating layer is above the channel layer, and the insulating layer has a plurality of contact windows An opening is formed to expose the channel layer, and the source and the drain are located on the insulating layer, and the source and the drain pass through the contact opening to contact the channel layer. A display panel has a display area and a non-display area, the display panel includes: a pixel array, the pixel array includes a plurality of pixel structures, and each pixel structure includes an active a component and a pixel electrode electrically connected to the active component; and a static electricity protection circuit disposed in the non-display area, the static electricity protection circuit comprising at least one thin film transistor, wherein the thin film transistor is as claimed in claim 1 Or as described in item 7.