JP6262477B2 - THIN FILM TRANSISTOR, ELECTRODE SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Google Patents

Description

  The present invention relates to a thin film transistor (TFT) using a transparent amorphous oxide semiconductor (TAOS), a display device electrode substrate using the thin film transistor (TFT), and a method for manufacturing the same.

  In recent years, a TFT using a transparent amorphous oxide semiconductor (TAOS) as a semiconductor layer has been proposed (for example, see Patent Document 1). Here, when TAOS is used for a TFT, development is proceeding in consideration of replacing the semiconductor layer with TAOS from the conventional amorphous silicon (a-Si: amorphous silicon).

JP 2000-150900 A

However, the prior art has the following problems.
FIG. 2 is a cross-sectional view showing the structure of a general i / s type TFT. In FIG. 2, when the channel length of the TFT is L and the channel width is W, the electrical performance of the TFT is represented by W / L. The parasitic capacitance of the TFT is determined by the area of the channel region and the crossing area of the gate electrode 51 and the source electrode 52 or the drain electrode 53.

  Here, in an active matrix display device such as a liquid crystal display device or an organic EL display device to which an electrode substrate for a display device using TFT is applied, one of the root causes of screen luminance non-uniformity is TFT parasitic capacitance. It exists. That is, in order to improve the aperture ratio and image quality of the display device, it is required to reduce the parasitic capacitance of the TFT.

  Therefore, if the TFT parasitic capacitance region is made the same as the channel region and the channel length L can be set to the minimum processing dimension, the TFT parasitic capacitance is reduced with respect to the TFT size (channel length L and channel width W). An ideal minimum value can be achieved.

However, in actuality, the size of the TFT parasitic capacitance region needs to be set to a minimum processing dimension in the process at a portion where the electrode interval is the smallest. In the case of a general i / s type TFT, i / s The gap width between the source electrode 52 and the drain electrode 53 located on the layer 54 (corresponding to the channel protective layer 54) is the minimum processing dimension.

  Therefore, the source / drain gap width determines the size of the TFT parasitic capacitance region, the channel length L becomes longer than the minimum processing dimension, and the TFT parasitic capacitance becomes larger than the ideal minimum value.

  At this time, in order to reduce the TFT parasitic capacitance to an ideal minimum value in the i / s type TFT, it is necessary to set the gate electrode width to the minimum processing dimension. This means that it must be wider than the gate electrode width. That is, the connection region between the source electrode 52 or the drain electrode 53 and the semiconductor layer 55 is located outside the gate electrode 51.

  In order to realize this, it is necessary to form a low-resistance conductive layer that connects between the source electrode end or the drain electrode end and the i / s layer end with the single-layer semiconductor layer 55. That is, the region between the source or drain electrode end and the channel region end covered with the i / s layer 54 is a semiconductor single layer.

  Further, in order to electrically connect the channel region and the source electrode 52 or the drain electrode 53 in this semiconductor single layer region and to obtain good TFT characteristics, the resistance of this semiconductor single layer region is set to the on-resistance of the channel. It is necessary to suppress to a sufficiently small value as compared with. This means that the specific resistance of the semiconductor layer 55 is reduced to the specific resistance of the conductor region, which is impossible with the conventional TFT manufacturing technology.

  For this reason, in a general i / s TFT manufacturing method, the resistance of the semiconductor layer 55 cannot be sufficiently reduced locally. Therefore, in the i / s TFT structure, the source / drain gap width is reduced to the minimum. Must be set to dimensions.

  Here, in a liquid crystal display device, an organic EL display device, and the like, as a method of reducing the parasitic capacitance of the TFT in order to improve the aperture ratio and the image quality, i / s type self-alignment using back exposure with ultraviolet rays (self There is an introduction of a matching) TFT structure.

  In the case where TAOS, which is being developed as a semiconductor material to replace conventional a-Si, is used for the semiconductor layer 55, IGZO (In, Ga, and Zn-containing oxides) that is expected to be commercialized among the TAOS materials ) Has low resistance to plasma damage in the manufacturing process and low chemical resistance to acids and alkalis.

  On the other hand, since the i / s layer 54 in the i / s structure has a function of protecting the channel region of the semiconductor layer 55 from these process damages, it is an optimum TFT structure for a TFT using TAOS (TAOS TFT). It is attracting attention as.

  However, for future large-scale and high-definition displays, even with i / s type self-aligned TFTs, it is expected that image quality degradation due to TFT parasitic capacitance will be significant. It is necessary to reduce the parasitic capacitance toward an ideal minimum value.

  Further, in order to manufacture an i / s type self-aligned TFT, the source / drain gap width must be set to the minimum processing dimension, and therefore the TFT parasitic capacitance is necessarily larger than the ideal minimum value. There is also a problem.

  The present invention has been made to solve the above-described problems. A TAOS TFT having a small element size and a small parasitic capacitance, an electrode substrate for a display device using the TAOS TFT, and a method of manufacturing the same are provided. The purpose is to obtain.

A thin film transistor according to the present invention includes a gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, a transparent amorphous oxide semiconductor layer formed on the gate insulating film, a gate insulating film, and a transparent A source electrode and a drain electrode formed on the amorphous oxide semiconductor layer so as not to overlap with the gate electrode, respectively, and formed on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask. A transparent amorphous oxide semiconductor layer by performing reduction treatment with a reducing gas on the transparent amorphous oxide semiconductor layer using the source electrode, the drain electrode, and the channel protective layer. , Between the end of the channel protective layer and the end of each of the source and drain electrodes Resistance value of the region, the channel protective layer, in which is lower than the resistance value of the region of overlap with the source electrode and the drain electrode.

A method of manufacturing a thin film transistor according to the present invention includes a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and a step of forming a transparent amorphous oxide semiconductor layer on the gate insulating film, Forming a source electrode and a drain electrode on the gate insulating film and the transparent amorphous oxide semiconductor layer so as not to overlap the gate electrode, and a substrate side using the gate electrode as a mask on the transparent amorphous oxide semiconductor layer A step of forming a channel protective layer by exposure from and a step of performing a reduction treatment with a reducing gas on the surface of the transparent amorphous oxide semiconductor layer using the channel protective layer , the source electrode and the drain electrode as a mask, It is provided.

According to the thin film transistor of the present invention, the channel protective layer is formed on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask, and does not overlap the channel protective layer of the transparent amorphous oxide semiconductor layer. The resistance value of the region is lower than the resistance value of the region overlapping the channel protective layer due to the reduction treatment with the reducing gas.
According to the thin film transistor manufacturing method of the present invention, after forming the channel protective layer on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask, the transparent amorphous oxide semiconductor layer By performing reduction treatment with a reducing gas on the surface using the channel protective layer as a mask, a region of the transparent amorphous oxide semiconductor layer that is not masked by the channel protective layer is reduced in resistance.
Therefore, it is possible to obtain a TAOS TFT having a small element size and a small parasitic capacitance, a display device electrode substrate using the TAOS TFT, and a manufacturing method thereof.

It is sectional drawing which shows the structure of TAOS TFT concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of a general i / s type TFT.

  Hereinafter, preferred embodiments of a TFT and an electrode substrate for a display device according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a configuration of a TAOS TFT 10 according to Embodiment 1 of the present invention. In FIG. 1, a TAOS TFT 10 includes a glass substrate 11, a gate electrode 12, a gate insulating film 13, a TAOS layer 14 (transparent amorphous oxide semiconductor layer), a TAOS reduction layer 15, a source electrode 16, and a drain electrode. 17, an i / s layer 18 (corresponding to the channel protective layer 18), and a resin insulating film 19.

  The gate electrode 12 is formed on the glass substrate 11. In addition, a board | substrate is not limited to the glass substrate 11, What is necessary is just to be transparent and to have insulation. The gate insulating film 13 is formed on the gate electrode 12. The TAOS layer 14 is formed on the gate insulating film 13.

  Here, the TAOS layer 14 uses IGZO, which is an oxide containing In, Ga, and Zn described above, as a material. The TAOS reduction layer 15 is a layer in which the surface of the TAOS layer 14 is made into a conductor by a reduction process described later.

  The source electrode 16 and the drain electrode 17 are respectively formed on the TAOS layer 14 so as not to overlap the gate electrode 12. The i / s layer 18 is an insulating layer formed on the TAOS layer 14 by exposure (backside exposure) from the glass substrate 11 side using the gate electrode 12 as a mask. The resin insulating film 19 is formed on the TAOS layer 14, the source electrode 16 and the drain electrode 17.

  In addition to the TAOS TFT 10, the electrode substrate for a display device using the TAOS TFT 10 passes through a plurality of scanning signal lines (not shown) formed on the glass substrate 11 and an insulating film (not shown). A plurality of display signal lines (not shown) formed so as to intersect with the plurality of scanning signal lines, and a plurality of display signal lines formed in the intersecting regions of the plurality of scanning signal lines and the plurality of display signal lines. A plurality of display pixel electrodes (not shown) electrically connected to the TAOS TFT 10 are further provided.

  In this display device electrode substrate, the gate electrode 12 is constituted by a part or extension of the scanning signal line, and the source electrode 16 and the drain electrode 17 are formed in the same process as the display signal line.

Subsequently, a manufacturing method of the TAOS TFT 10 will be described along a procedure.
First, the gate electrode 12 is formed on the glass substrate 11. Here, the gate electrode 12 is formed by patterning a metal layer formed by sputtering, for example. Subsequently, a gate insulating film 13 is formed on the gate electrode 12. Here, the gate insulating film 13 is formed by, for example, CVD.

Next, a TAOS layer 14 is formed on the gate insulating film 13. Here, the TAOS layer 14 is formed by sputtering using a mixed gas containing at least Ar and O ₂ .

  Subsequently, a source electrode 16 and a drain electrode 17 are formed on the gate insulating film 13 and the TAOS layer 14 so as not to overlap the gate electrode 12. Here, the source electrode 16 and the drain electrode 17 are formed by patterning a metal layer formed by sputtering, for example.

  Next, the i / s layer 18 is formed on the TAOS layer 14 by exposure (backside exposure) from the glass substrate 11 side using the gate electrode 12 as a mask. Here, as the material of the i / s layer 18, a resin material, silicon oxide-based or silicon nitride-based SiNx, SiOx, or SiOxNy can be considered.

  Subsequently, reduction treatment with a reducing gas such as hydrogen radical is performed on the surface of the TAOS layer 14 using the i / s layer 18 as a mask. Here, due to the reduction treatment, oxygen atoms in the TAOS layer 14 (IGZO) in the region not covered with the i / s layer 18 undergo a reduction reaction, oxygen vacancies increase, and the properties approach the conductor side. The reducing gas includes at least one of hydrogen radicals, ammonia radicals, and hydrogen gas.

As a result, the resistance of the surface of the TAOS layer 14 is reduced to become the TAOS reduction layer 15, which has a conductivity that can be used as an electrode. Subsequently, a resin insulating film 19 is formed from a resin material on the TAOS reduction layer 15, the source electrode 16, the drain electrode 17, and the i / s layer 18.

  In addition, the manufacturing method of the electrode substrate for display apparatuses using TAOS TFT10 has the following procedures in addition to the manufacturing method of TAOS TFT10. That is, a procedure for forming a plurality of scanning signal lines (not shown) on the glass substrate 11 and a plurality of display signals so as to cross the plurality of scanning signal lines via an insulating film (not shown). A plurality of display pixel electrodes so as to be electrically connected to a plurality of TAOS TFTs 10 formed in respective intersection regions of the plurality of scanning signal lines and the plurality of display signal lines. (Not shown) are further included.

  In this method of manufacturing an electrode substrate for a display device, the gate electrode 12 is formed simultaneously in the procedure of forming a plurality of scanning signal lines, and the source electrode 16 and the drain electrode 17 form a plurality of display signal lines. Are simultaneously formed in the procedure.

  As a result, in the region outside the gate electrode 12, the TAOS reduction layer 15, which is a conductorized TAOS layer 14, can be electrically connected to the source electrode 16 and the drain electrode 17.

  Further, since the TAOS layer 14 in the region not covered with the i / s layer 18 is made into a conductor, the surface is formed between the channel region end covered with the i / s layer 18 and the source electrode end or the drain electrode end. Electrical connection can be achieved by a single-layered TAOS reduction layer 15 made into a conductor.

  Therefore, since the gate electrode width can be set to the minimum processing dimension, the channel width L can be shortened and the TFT parasitic capacitance compared with the i / s type TFT in which the source / drain gap width is set to the minimum processing dimension. Can be reduced to an ideal minimum value. In addition, in the i / s type self-aligned TFT, it is not necessary to consider the alignment accuracy between the i / s layer 18 and the source electrode 16 and the drain electrode 17, so that the TFT parasitic capacitance can be reduced.

  Further, since the TAOS layer 14 in the region connected to the source electrode 16 and the drain electrode 17 is made conductive (TAOS reduction layer 15), the material of the source electrode 16 and the drain electrode 17 that can be ohmic-connected to the TAOS reduction layer 15 You can expand your options.

As described above, according to Embodiment 1, the i / s layer is formed on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask. The resistance value in the region that does not overlap with the / s layer is lower than the resistance value in the region that overlaps with the i / s layer due to the reduction treatment with the reducing gas.
In addition, according to the method for manufacturing a thin film transistor according to the present invention, after forming an i / s layer on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask, the transparent amorphous oxide semiconductor layer is formed. By performing a reduction treatment with a reducing gas with the i / s layer as a mask, the area of the transparent amorphous oxide semiconductor layer that is not masked by the i / s layer is reduced in resistance.
Therefore, it is possible to obtain a TAOS TFT having a small element size and a small parasitic capacitance, a display device electrode substrate using the TAOS TFT, and a manufacturing method thereof.

  11 glass substrate, 12 gate electrode, 13 gate insulating film, 14 TAOS layer, 15 TAOS reducing layer, 16 source electrode, 17 drain electrode, 18 i / s layer, 19 resin insulating film.

Claims (6)

A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A transparent amorphous oxide semiconductor layer formed on the gate insulating film;
A source electrode and a drain electrode respectively formed on the gate insulating film and the transparent amorphous oxide semiconductor layer so as not to overlap the gate electrode;
A channel protection layer formed on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask, and
Using the source electrode, the drain electrode, and the channel protective layer, the transparent amorphous oxide semiconductor layer is subjected to reduction treatment with a reducing gas, so that in the transparent amorphous oxide semiconductor layer, resistance of the region between the respective end portions of the the end of the channel protective layer source electrode and the drain electrode, the channel protective layer, than the resistance value of the region of overlap with the source electrode and the drain electrode Thin film transistors that are even lower. The thin film transistor according to claim 1, wherein the reducing gas includes at least one of hydrogen radicals, ammonia radicals, and hydrogen gas. An electrode substrate for a display device using the thin film transistor according to claim 1 or 2,
A plurality of scanning signal lines formed on the transparent insulating substrate;
A plurality of display signal lines formed so as to intersect the plurality of scanning signal lines via an insulating film;
Further comprising a plurality of the thin film transistor and electrically connected to the plurality of display pixel electrodes formed in each intersection region between said plurality of said plurality of display signal lines and the scanning signal lines,
The gate electrode is composed of a part or extension part of the scanning signal line,
The source electrode and the drain electrode are formed in the same process as the display signal line. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a transparent amorphous oxide semiconductor layer on the gate insulating film;
Forming a source electrode and a drain electrode on the gate insulating film and the transparent amorphous oxide semiconductor layer so as not to overlap the gate electrode,
Forming a channel protective layer on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask;
Performing a reduction treatment with a reducing gas on the surface of the transparent amorphous oxide semiconductor layer using the channel protective layer , the source electrode and the drain electrode as a mask;
The manufacturing method of the thin-film transistor provided with. The method of manufacturing a thin film transistor according to claim 4, wherein the reducing gas includes at least one of hydrogen radicals, ammonia radicals, and hydrogen gas. A method for manufacturing an electrode substrate for a display device using the method for manufacturing a thin film transistor according to claim 4 or 5,
Forming a plurality of scanning signal lines on the transparent insulating substrate;
Forming a plurality of display signal lines so as to intersect the plurality of scanning signal lines via an insulating film;
Forming a plurality of display pixel electrodes to be more of the thin film transistor electrically connected formed in each intersection region between said plurality of said plurality of display signal lines and the scanning signal lines, a further Prepared,
The step of forming the gate electrode and the step of forming the plurality of scanning signal lines are the same step,
The step of forming the source electrode and the drain electrode and the step of forming the plurality of display signal lines are the same step.

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