JP2019071431A - Light-emitting device - Google Patents

Abstract

To provide a light-emitting device arranged so as to be able to reduce the variation in TFT characteristics, even the variation in OLED which is not involved in the variation in TFT characteristics, and to reduce the variation in brightness, and to provide a light-emitting device having a pixel structure that increase an opening rate in a pixel section.SOLUTION: A light-emitting device comprises a light-emitting element having a negative electrode 344, an organic compound layer in contact with the negative electrode, and a positive electrode 334 in contact with the organic compound layer. The channel length L of TFT connected to the light-emitting element is 100 μm or more.SELECTED DRAWING: Figure 7

Description

In particular, the present invention relates to an organic light emitting element (OLE) formed on a substrate having an insulating surface.
The present invention relates to a light emitting device having D (Organic Light Emitting Device). The present invention also relates to an OLED module in which an IC or the like including a controller is mounted on the OLED panel. In the present specification, both the OLED panel and the OLED module are collectively referred to as a light emitting device. The present invention further relates to an electronic device using the light emitting device.

Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and all of a light-emitting device, an electro-optical device, a semiconductor circuit, and an electronic device are semiconductor devices.

In recent years, a technology for forming a TFT (thin film transistor) on a substrate has been greatly advanced, and application development to an active matrix display device has been advanced. In particular, a TFT using a polysilicon film has higher field effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and therefore can operate at high speed.
Therefore, development for controlling each pixel by actively providing a drive circuit including a TFT using a polysilicon film on the same substrate as the pixel has been actively conducted. An active matrix display in which pixels and a driver circuit are integrated on the same substrate is expected to provide various advantages such as reduction in manufacturing cost, miniaturization of display, increase in yield, and reduction in throughput.

In addition, an active matrix light emitting device (hereinafter referred to
Research on light emitting devices) is becoming active. The light emitting device is an organic light emitting device (OELD: Or
ganic EL Display) or organic light emitting diode (OLED: Organic Ligh)
It is also called t Emitting Diode).

An OLED emits light by itself and has high visibility. A backlight necessary for a liquid crystal display (LCD) is not required, which is suitable for thinning, and there is no limitation on the viewing angle. Therefore, a light emitting device using an OLED is attracting attention as a display device to replace a CRT or an LCD.

As one form of a light emitting device using an OLED, an active matrix driving method is known in which a plurality of TFTs are provided for each pixel and a video signal is sequentially written to display an image. The TFT is an essential element in realizing the active matrix driving method.

In addition, to realize the active matrix drive method, in the light emitting device using OLED, in order to control the current flowed to the OLED by the TFT, it is possible to realize the TFT using amorphous silicon with low field effect mobility. It is difficult, and it is desirable to adopt a TFT that connects a semiconductor film having a crystal structure, typically, polysilicon, to an OLED.

By forming a TFT with a semiconductor film having a crystalline structure, typically a polysilicon film, and incorporating a pixel and a driver circuit on the same substrate, the number of connection terminals is drastically reduced, and a frame region (a peripheral portion of a pixel portion Area can also be reduced.

However, even if polysilicon is used to form a TFT, its electrical characteristics are not at all comparable to the characteristics of a MOS transistor formed on a single crystal silicon substrate. For example, the field effect mobility of the conventional TFT is 1/10 or less of that of single crystal silicon. In addition, TFTs using polysilicon have the problem that their characteristics tend to vary due to defects formed in grain boundaries.

Generally, a light emitting device comprises at least a TFT functioning as a switching element, and an OLED
And a TFT for supplying a current to each pixel. While a low off current (I _off ) is required for a TFT functioning as a switching element, a TFT for supplying a current to an OLED is prevented from deterioration due to a high drivability (on current, I _on ) and a hot carrier effect. There is a need to improve reliability.
In addition, it is also required that the TFTs of the data line side drive circuit be prevented from deterioration due to high drive capability (on current, I _on ) and the hot carrier effect and to improve reliability.

In addition, regardless of the driving method of the screen display, for example, a driving method such as a point sequential driving method, a line sequential driving method, or a surface sequential driving method, the TFT electrically connected to the OLED and supplying current to the OLED Since the luminance of the pixel is determined by the on current (I _on ), there is a problem that when the entire white display is performed, the luminance is uneven if the on current is not constant. For example, in the case of adjusting the luminance by the light emission time, in the case of displaying 64 gradations, the ON current of the TFT electrically connected to the OLED and supplying current to the OLED is 1.56% from a reference value
(= 1/64) When it varies, it will shift by one gradation.

In addition, when an OLED is formed, variations in the inside of the substrate may occur due to misalignment of patterning of the EL layer or nonuniformity of the film thickness of the EL layer, and slight variations in luminance occur.

The present invention has been made in view of the above problems, and reduces the characteristic variation of each TFT,
It is an issue to reduce variations in luminance. In addition, it is also an object to reduce the variation of the luminance and to reduce the variation of the OLED which is not related to the characteristic variation of the TFT.

Further, in the conventional active matrix light emitting device, when it is intended to improve the resolution, the aperture ratio is limited by the arrangement of the electrode for the storage capacitor and the wiring for the storage capacitor, the TFT, and various wirings in the pixel portion. The problem of that had arisen.
Another object of the present invention is to provide a pixel configuration that improves the aperture ratio in the pixel portion.

In the TFT characteristics, a VI characteristic graph is known as a representative index. This V
-The current value changes most where steep rise in the I characteristic graph (also referred to as a rise point). Therefore, when the current supplied to the OLED is controlled by the TFT, if the rising point is dispersed, the current value of the TFT for supplying the current to the OLED is largely changed.

The voltage value at the rising point is called a threshold (Vth) and is a voltage value at which the TFT is switched to the on state. In general, it is said that the closer to zero the closer Vth is, the better. If the value of Vth is large, the drive voltage is increased and the power consumption is increased.

There are two types of variation in the current value of the TFT, and specifically, a simple variation 3σ of the current value and a median value (average value) of the current values in a set of a certain number of TFTs
(This variation is also referred to as standardized variation in this specification).

The inventor found that the latter variation tends to be strongly dependent on the gate voltage value (Vg). As shown in FIG. 3, various channel lengths (5 μm, 10 μm, 20 μm, 50 μm, 100)
The relationship between Vg and the standardized variation in a p-channel TFT (channel width W = 8 μm) of μm, 200 μm, and 400 μm is shown. Further, FIG. 4 shows the relationship between Vg and standardized variation in n channel type TFTs (channel width W = 8 μm) of various channel lengths.

The present invention will be described in detail below using measured data of TFTs.

As the channel length of the TFT for supplying current to the OLED becomes longer, the current value decreases and the simple variation 3σ decreases. In FIG. 11, Vd is set to -7 V, Vg is set to -3.25 V, and the channel width is fixed to 8 μm, and the channel lengths are 50 μm, 100 μm, 200 μm, and 4 respectively.
It is the graph which produced the TFT set to 00 micrometers and measured the variation and the standardized variation of ON current about each TFT.
However, as shown in FIG. 11, merely increasing the channel length reduces the current value,
The variation (normalized variation) with respect to the central value of the current value in a set of a certain number of TFTs does not change.

Therefore, in the present invention, the channel length is made 10 times or more or several hundreds times the conventional one, the TFT is designed to be turned on at a much higher gate voltage value, and the gate voltage input from the outside is set. The variation is reduced by driving.

Here, Vd was set to -7 V, the channel width was fixed to 8 μm, and the channel length was set to 50 μm, and the Vg was set to -3 V, and the on-current variation and the standardized variation were measured. Thereafter, similarly, in the TFT having a channel length of 100 μm, Vg is −3.
The measurement was made at 75 V, and the TFT having a channel length of 200 μm was measured at a Vg of −3.75 V, and the TFT having a channel length of 400 μm was measured at a Vg of −5.75 V. The measurement results are shown in FIG.

As shown in FIG. 2, as the gate voltage value (Vg) is increased as the TFT having a long channel length remarkably, it is possible to reduce not only the simple on current variation but also the standardized variation. . Here, a TFT with a long channel length is used to increase Vg, but there is no particular limitation. For example, the channel width W may be shortened within the design tolerance to increase Vg. The source region or the drain region may have a high resistance, or the contact resistance may have a high resistance.

In addition, the present invention uses a TFT having a much longer channel length than the conventional one, specifically, a channel length several tens to several hundreds times longer than the conventional one, and turns on at a gate voltage value much higher than the conventional one. It is driven as a state to provide a TFT with a low channel conductance gd. Figure 1 shows
And the corresponding data, and is a graph showing the channel conductance gd of each TFT under the same conditions (Vg, channel width, channel length, etc.) as the data of FIG.

In the present invention, the channel conductance gd is 0 to 1 × in a range where the sum of the voltage Vd between the source and the drain and the threshold voltage Vth is larger than the gate voltage Vg, that is, Vg <(Vd + Vth). 10 ⁻⁸ S, preferably 5 × 10 ⁻⁹ S or less,
More preferably, by setting the TFT to 2 × 10 ⁻⁹ S or less, the variation of the current value flowing to the TFT is reduced, and a certain current value flows to the OLED.

In addition, by reducing the channel conductance gd, it is possible to reduce variations in the OLED itself caused by area contraction of the EL layer due to patterning or heat treatment. Further, by reducing the channel conductance gd, even if the OLED is deteriorated for some reason, the current flowing to the OLED can be kept constant, and a constant luminance can be maintained. FIG. 12 shows the Id-Vd curve and the load curve of the OLED. The channel conductance gd indicates the slope of the Id-Vd curve, and the smaller the channel conductance gd, the smaller the slope of the Id-Vd curve and the current value becomes substantially constant. In FIG. 12, the load curve of the OLED is Vg = −3.3 V, and when the p-channel TFT connected to the OLED is driven in the saturation region, the current value and V applied to the OLED
It is a curve which shows a relation with d. For example, when -Vd is -17 V, the voltage applied to the OLED is 0 V because the voltage on the cathode side is -17 V. Therefore, the current value applied to the OLED is also zero. Also, the current value at the intersection of the Id-Vd curve and the load curve of the OLED corresponds to the luminance. In FIG. 12, when gd is small, there is a cross point when -Vd is -7 V, and the current value applied to the OLED at that time is 1 × 10 ^-6 [A], and the luminance according to this current value Light emission is obtained. When gd is small, even if the load curve of the OLED shifts to the left or right, the current value hardly changes, so that uniform luminance can be obtained. Also, if the individual OLEDs themselves vary, the load curve of the OLEDs shifts to the right or to the left.
Also, when the OLED is degraded, the load curve of the OLED shifts to the left. When gd is large, the load curve of the OLED shifts to the left due to deterioration, and becomes a curve shown by a dotted line.
The point of intersection with the load curve of the ED changes, and the current value becomes different before and after deterioration. On the other hand, when gd is small, even if the load curve of the OLED is shifted to the left due to deterioration, the current value hardly changes, so that the variation in brightness is reduced and uniform brightness can be obtained.

Here, in order to lower the channel conductance gd, the channel length is made longer and the on state is driven with a gate voltage value much higher than before, but even if the channel conductance gd is further reduced by other means Good. For example, as another means for reducing the channel conductance gd, the TFT may have an LDD structure, or the channel formation region may be divided into a plurality.

Conventionally, the n-channel TFT size of the pixel used in the liquid crystal panel has a channel length L
× Channel width W = 12 μm × 4 μm, L × W = 12 μm × 6 μm, etc. were used. Generally, in order to improve the aperture ratio, the smaller the area occupied by the TFT of the pixel, that is, the smaller the occupied area, the better. Therefore, it was impossible to make the channel length 100 μm or more. Further, as shown in FIG. 4, when the channel length is 5 μm or 10 μm, the variation is minimized when Vg is 8 V to 10 V, and when 10 V or more, the variation tends to increase. Therefore, when the channel length is set to 100 μm or more, it can not be expected that the variation decreases as Vg increases.

In addition, when the channel length is 100 μm or more, various shapes can be considered as the shape of the semiconductor layer. As a typical example, the shape obtained by meandering the semiconductor layer 102 in the X direction as shown in FIG. In the specification, the semiconductor layer 1 is referred to as “type A” or as shown in FIG.
A shape (in this specification, referred to as a B type) which meanders 102 in the Y direction and a rectangular shape (semiconductor layer 1202) as shown in FIG. 13B are shown.

In addition, when the irradiation process of the laser light is performed as one of the steps of forming the TFT by increasing the channel length, variation in the laser light can also be reduced. The TFT size and the semiconductor layer shape are respectively L × W = 87 μm × 7 μm (rectangular shape), L × W = 16.
5 μm × 7 μm (rectangular shape), L × W = 88 μm × 4 μm (rectangular shape), L × W = 165
μm × 4 μm (rectangular shape), L × W = 500 μm × 4 μm (A type), L × W = 50
0 μm × 4 μm (B type), and the scanning speed of the laser light is 1 mm / sec.
The TFTs were manufactured under the conditions of 5 mm / sec, and the TFT size and the semiconductor layer shape,
An experiment was conducted to determine the relationship with the variation (3σ) of the on current of the TFT. Here, the crystallinity of polysilicon is enhanced by laser light irradiation. In FIG. 18, the gate voltage Vg = -5V,
The experimental results when Vd = -6 V are shown in FIG. 19, and the gate voltage Vg = -10 V, Vd =-is shown in FIG.
The experimental result at the time of setting it as 6V is shown. In FIG. 18 and FIG.
A) is also shown. Furthermore, the TFT size and semiconductor layer shape, and the threshold value (Vth) of the TFT
The relationship with the variation (3σ) of is determined as shown in FIG.

It can be read from FIGS. 18 and 19 that the longer the channel length L, the smaller the variation in the on current. Laser scanning speed is 0.5m more than 1mm / sec
The variation in laser light is reduced when m / sec is set, and as the channel length L is increased, the difference in variation between different laser scanning speeds is reduced. That is, it can be said that the dispersion of the laser light is reduced as the channel length L is increased. Also, it can be read that L × W = 500 μm × 4 μm is the one with the smallest variation, and furthermore, the variation in the on current is smaller in the A type than in the B type.

From the above, it can be said from FIG. 18 and FIG. 19 that the variation in luminance of the light emitting device can be reduced as a driving method of operating the TFT for supplying current to the OLED in a voltage range up to the saturation region.

In addition, when the current value flowing through the TFT is compared to be constant, it is preferable that the channel width W be smaller. FIG. 21 shows a graph showing the variation when the current value is constant (Id = 0.5 μA). From FIG. 21, it can be said that the variation in luminance of the light emitting device can be reduced as a driving method of operating the TFT for supplying current to the OLED in the saturation region. Similarly, it can be read that L × W = 500 μm × 4 μm is the one with the largest variation reduction, and furthermore, the variation in the on current is smaller in the A type than in the B type.

Also in FIG. 20, the longer the channel length L, the more the threshold voltage of the TFT (Vt
It can be read that the variation of h) tends to be reduced.

In addition, as the channel length L is longer, both the threshold voltage and the on-state variation, that is, the electrical characteristics of the TFT are reduced. Is also reduced.

Further, also in a light emitting device having an OLED, the smaller the occupied area of the TFT disposed in the pixel, the better. Since the conventional TFT size is small, the variation in individual TFT characteristics is large, which is a main cause of display unevenness in the display device.

When controlling the current flowing to the OLED with the TFT, there are roughly two methods. Specifically, there are a method of controlling the current in a voltage range called a saturation region and a method of controlling the current in a voltage range until the saturation region is reached. As shown in FIG. 9, the TFT applies a certain gate voltage Vg, gradually increases the voltage Vd between the source and the drain, measures the value of the flowing current, and determines the Vd-Id curve. Thus, a graph is obtained in which the current value is substantially constant. In the present specification, in the Vd-Id curve, the range of Vd in which the current value is substantially constant is called a saturation region.

The present invention is also effective in operating the TFT for supplying current to the OLED in a voltage range up to the saturation region, but in particular for operating the TFT for supplying current to the OLED in the saturation region, the current flowing to the OLED If the driving method is to keep the constant, the effect of reducing the variation can be seen remarkably.

In addition, although it is preferable to use a TFT for supplying a current to the OLED to a p-channel TFT in which the variation is reduced as compared to the n-channel TFT as shown in FIG. 3 and FIG. P-channel TF even if the supplied TFT is n-channel TFT
It may be T. For example, in the case where a TFT for supplying a current to an OLED is a p-channel TFT, connection as shown in FIG. 10A may be performed. Further, for example, in the case where a TFT for supplying a current to an OLED is an n-channel TFT, the connection shown in FIG. 10B may be performed. Although FIGS. 10A and 10B show only the TFTs for supplying current to the OLEDs, various circuits including a plurality of TFTs may be provided after the gate electrodes of the TFTs. Needless to say, it is not particularly limited.

A configuration of the invention disclosed in the present specification is a light emitting device including a light emitting element having a cathode, an organic compound layer in contact with the cathode, and an anode in contact with the organic compound layer, which is connected to the light emitting element The channel length L of the TFT is 100 μm or more, preferably 100 μm to 500 μm.

In the above configuration, the ratio of the channel width W to the channel length L of the TFT is 0.1 to 0..
It is characterized by being 01.

In addition, a structure of another invention disclosed in the present specification is a light emitting device including a light emitting element having a cathode, an organic compound layer in contact with the cathode, and an anode in contact with the organic compound layer, The ratio of the channel width W to the channel length L of the TFT connected to is 0.1 to 0.01.

In each of the above configurations, the TFT connected to the light emitting element has a channel conductance gd of 0 to 1 × 10 ⁻⁸ S in a range where the sum of the voltage Vd between the source and the drain and the threshold voltage Vth is larger than the gate voltage Vg. , Preferably 0 to 5 × 10 ^-9 S, more preferably 0 to 2 ×
It is characterized by being 10 ^-9 S.

In addition, a structure of another invention disclosed in the present specification is a light emitting device including a light emitting element having a cathode, an organic compound layer in contact with the cathode, and an anode in contact with the organic compound layer, The TFT connected to the light emitting device is characterized in that the channel conductance gd is 0 to 2 × 10 ⁻⁹ S in a range where the sum of the voltage Vd between the source and the drain and the threshold voltage Vth is larger than the gate voltage Vg. is there.

In each of the above configurations, the TFT connected to the light emitting element is a p-channel TFT or an n-channel TFT.

Note that a region called a channel formation region in the present specification is a carrier (electron or hole)
Indicates a region including a flowing portion (also referred to as a channel), the length of the channel forming region in the carrier flowing direction is called a channel length, and the width is called a channel width.

Further, in the present specification, the channel conductance gd refers to the conductivity of the channel and can be expressed by the following equation.

Here, L indicates a channel length, W indicates a channel width, Vg indicates a gate voltage, Vth indicates a threshold voltage, μ n indicates mobility, and C _OX indicates oxide film capacitance. In the TFT, when Vg becomes equal to or higher than Vth, channel conductance starts to occur.

In addition, when the channel length L is increased, the oxide film capacitance C _OX is increased, so that part of the capacitance can be used as the retention capacitance of the OLED. Conventionally, a space for forming a storage capacitor is required to form a storage capacitor for each pixel, and a capacitor line, a capacitor electrode, and the like are provided. However, with the pixel configuration of the present invention, the capacitor line and the capacitor electrode It can be omitted. When the storage capacitance is formed by the oxide film capacitance C _OX , the storage capacitance is formed by using the gate insulating film as a dielectric, the gate electrode, and the semiconductor (channel forming region) overlapping with the gate electrode through the gate insulating film. Ru. Therefore, even if the channel length of the TFT is increased, the aperture ratio can be reduced if the semiconductor layer 102 of the TFT is disposed below the power supply line 106 and the source wiring disposed above the gate electrode as shown in FIG. The pixel can be designed without That is, with the pixel configuration of the present invention, a sufficient storage capacitance can be provided even if the space for forming the capacitive electrode and the capacitive wiring is omitted, and the aperture ratio can be further increased.

In the TFT size and the semiconductor layer shape in FIGS. 18 to 19, the oxide film capacitance C _OX is 192 (fF), L × in the case of L × W = 87 μm × 7 μm (rectangular shape), respectively.
364.5 (fF), L × W = 88 in the case of W = 165 μm × 7 μm (rectangular shape)
In the case of μm × 4 μm (rectangular shape), 111.1 (fF), L × W = 165 μm × 4
208.3 (fF) in μm (rectangular shape), 631.3 (fF) in the case of L × W = 500 μm × 4 μm (A type)
In the case of L × W = 500 μm × 4 μm (B type), 631.3 (fF). Also, as another value when obtaining the oxide film capacitance C _OX , the thickness T of the gate insulating film (oxide film)
It was set as ox = 115 nm, (epsilon) ₀ = 8.8542 * 10 < ^-12 > (F / m < ² >), (epsilon) _OX = 4.1.

In each of the above configurations, the capacitance C _OX of the TFT connected to the light emitting element is 100 f
It is characterized by being F or more, preferably 100 fF to 700 fF.

In each of the above-described configurations, a storage capacitor is formed by the gate electrode of the TFT connected to the light emitting element and the wiring thereabove. Specifically, as shown in FIG.
With the interlayer insulating film (organic insulating film or inorganic insulating film) provided over the gate electrode 100 as a dielectric, a capacitance is formed by the gate electrode 100 and a power supply line 106 overlapping the gate electrode. In FIG. 5, the area (12 μm × 127 μm = about 1524 μm ² ) overlapping with the gate electrode 100 and the power supply line 106 overlapping the gate electrode is large, and although depending on the film thickness and dielectric constant of the interlayer insulating film, a storage capacitance is formed. Be done. The capacitance formed between the gate electrode 100 and the power supply line 106 can all function as a storage capacitance of the EL element. Therefore, desirably, the total of the capacitance C _{OX of the} TFT connected to the light emitting element and the capacitance formed between the gate electrode of the TFT and the current supply line is appropriately designed to be several hundred fF. Just do it.

In the present specification, all layers formed between the anode and the cathode of the OLED are defined as the organic light emitting layer. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer and the like. Basically, an OLED has a structure in which an anode / a light emitting layer / a cathode is sequentially stacked, and in addition to this structure, an anode / a hole injection layer / a light emitting layer / a cathode, or an anode / a hole injection layer / The light emitting layer / electron transport layer / cathode may be laminated in this order.

An OLED is a layer (hereinafter referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) from which luminescence (Electroluminescence) generated by applying an electric field is obtained, an anode,
And a cathode. Luminescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Among the light emissions described above, any one of the light emissions may be used, or both light emissions may be used.

Further, although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure, and for example, it is applied to a bottom gate type (reverse stagger type) TFT or forward stagger type TFT Is possible.

In the light emitting device of the present invention, the method of driving the screen display is not particularly limited. For example, a point sequential driving method, a line sequential driving method, a surface sequential driving method or the like may be used.
Typically, a line sequential driving method may be used, and a time division gray scale driving method or an area gray scale driving method may be used as appropriate. Further, the video signal input to the source line of the light emitting device may be an analog signal or a digital signal, and a driver circuit or the like may be appropriately designed according to the video signal.

According to the present invention, in the pixel portion where a plurality of TFTs are arranged, T that supplies current to the OLED
In the FT, not only simple on current variations but also standardized variations can be reduced, and brightness variations can be significantly reduced in a display device having an OLED.

Further, according to the present invention, even if variations occur in the TFT manufacturing process such as laser light irradiation conditions, variations in the electrical characteristics among the respective TFTs can be reduced.

Further, according to the present invention, in addition to the variation among the TFTs, the variation of the OLED itself caused by the area contraction of the EL layer due to the patterning and the heat treatment can be reduced.

Further, according to the present invention, in addition to the variation among the TFTs, even if the OLED is deteriorated for some reason, the current flowing to the OLED can be kept constant, and a constant luminance can be maintained.

Further, according to the present invention, a part of the capacitance Cox of the TFT can be intentionally used as a storage capacitance, and the pixel structure can be simplified and the aperture ratio can be improved.

It is a figure which shows the relationship between the channel length of TFT, and channel conductance gd. It is a figure which shows 3 (sigma) which shows the dispersion | variation of the electric current standardized to 3 (sigma) which shows the dispersion | variation in an electric current. It is a graph which shows the relationship between the variation in the electric current of n channel type TFT, and Vg in a certain channel length. It is a graph which shows the relationship between the variation in the electric current of n channel type TFT, and Vg in a certain channel length. It is a figure which shows a pixel top view. It is a figure which shows a pixel top view. It is a figure which shows the cross-section of an active-matrix type light emitting display. FIG. 5 is a diagram showing an equivalent circuit of an active matrix light emitting display device. It is a figure which shows the graph which shows an Id-Vd curve. It is a figure which shows the connection relation of TFT connected with OLED and this OLED. It is a figure which shows 3 (sigma) which shows the dispersion | variation of the electric current standardized to 3 (sigma) which shows the dispersion | variation in an electric current. It is a figure which shows the load curve and Id-Vd curve of OLED. It is a figure which shows a pixel top view. (Example 2) It is a figure which shows a module. (Example 3) It is a figure which shows a module. (Example 3) It is a figure showing electronic equipment. (Example 4) It is a figure showing electronic equipment. (Example 4) It is a graph (Vg = -5V) which shows the relationship between the TFT size of this invention, and the dispersion | variation in on current. It is a graph (Vg = -10V) which shows the relationship between the TFT size of this invention, and the dispersion | variation in on current. It is a graph which shows the relationship between the TFT size of this invention, and the dispersion | variation in a threshold value. It is a graph which makes a current value constant (Id = 0.5 microampere), and shows the relationship between the TFT size of this invention, and the variation of on current.

  Embodiments of the present invention will be described below.

FIG. 5 is an enlarged top view of a part of a pixel portion of a light emitting device having an OLED.
In FIG. 5, the EL layer is not shown for simplification, and only one electrode (pixel electrode 107) of the OLED is shown.

In FIG. 5, the semiconductor layer 101 is a layer to be an active layer of the switching TFT, a region overlapping with the gate wiring 105 is a channel forming region, a region connecting with the source wiring 104 is a source region (or drain region), and a connection electrode A region connected to 103 is a drain region (or a source region). The switching TFT has a double gate structure having two channel formation regions.

In addition, the semiconductor layer 102 is a layer to be an active layer of a TFT for supplying a current to the OLED,
A region overlapping with the gate electrode 100 is a channel formation region. T that supplies current to the OLED
The gate electrode 100 of the FT is connected to the connection electrode 103.
Also, the source region (or drain region) of the TFT for supplying current to the OLED is connected with the power supply line 106, and the drain region (or source region) of the TFT for supplying current to the OLED is connected with the connection electrode 108. A pixel electrode 107 is formed in contact with the connection electrode 108. Further, above the gate electrode 100, the power supply line 106 and the source wiring of the adjacent pixel are disposed so as to partially overlap with each other. Note that the power supply line 106 is provided above the channel formation region in the semiconductor layer 102 overlapping with the gate electrode 100 with the gate insulating film interposed therebetween.
And the source wiring of adjacent pixels are arranged so as to partially overlap with each other. This gate electrode 10
The capacitance formed between 0 and the power supply line 106 can all be used as a storage capacitance of the EL element. Therefore, the required storage capacitance can be secured to some extent by the capacitance formed between the gate electrode 100 and the power supply line 106.

6 is a top view corresponding to FIG. 5, and the semiconductor layers 101 and 102 and the gate wiring 10 are shown.
FIG. 5 is a diagram at a stage when the gate electrode 100 is formed. The semiconductor layer 102 is the gate electrode 100
A region overlapping with the gate insulating film (not shown), that is, a channel formation region is indicated by a dotted line in FIG.

In the present invention, the length of the channel formation region of the TFT for supplying current to the OLED (channel length L
) Has a much longer TFT (L = 100 μm to 500 μm, here 500 μm) and is driven in the on state with a gate voltage value much higher than before, and the channel conductance gd is
Low TFT (gd = 0 to 1 × 10 ^-8 S, preferably 5 × 10 ^-9 S or less, here 2 × 1
0 ^-9 S) or less).

With the above configuration, as shown in FIG. 2, in the pixel portion where a plurality of TFTs are arranged, not only simple ON current variations but also standardized variations in TFTs supplying current to the OLEDs. This can be reduced and the variation in luminance can be significantly reduced in a display device having an OLED.

In addition, the present invention, as a method of driving the OLED, OLE in the voltage range called saturation region
When the method of controlling the current flowing to D is adopted, it has a very remarkable effect. With the above-described configuration, as shown in FIG.
Variations that occur during fabrication (variations in the OLED itself caused by area contraction of the EL layer due to patterning and heat treatment, etc.) can also be reduced. Further, with the above configuration, as shown in FIG. 12, the current flowing to the OLED can be kept constant even if the OLED is deteriorated due to any cause other than the variation between the respective TFTs, and the constant luminance Can be held.

Also, the present invention is directed to a method of driving an OLED, wherein the voltage range up to the saturation region is reached.
The method of controlling the current flowing to the LED is also useful.

Needless to say, the present invention is not limited to the top views of FIGS. 5 and 6. 5 and 6 show an example of a light-emitting device (typically, the light-emitting device shown in FIG. 14) which emits light by passing through a substrate on which a TFT is formed. In the region where the connection electrode 108 is not formed, the TFT having a long channel length L is used to widen the opening.
Are disposed below the power supply line 106 and the source line. This long channel length L TF
The capacitance formed between the gate electrode 100 of T and the power supply line 106 can all be used as a storage capacitance of the EL element. In the case of a light-emitting device emitting light in the opposite direction to that in FIGS. 5 and 6 (typically, the light-emitting device shown in FIG. 15), the opening becomes the same region as the pixel electrode and the TFT with a long channel length L May be disposed below the pixel electrode, and a TFT having a longer channel length L of 500 .mu.m or more can be formed.

Further, if the pixel structure shown in FIGS. 5 and 6 is used, a part of the oxide film capacitance Cox can be used as the storage capacitance without forming a capacitance portion for forming the storage capacitance. Storage capacitors and memories (SRAM, DRAM, etc.).
Furthermore, a plurality of (two or more) TFTs or various circuits (such as a current mirror circuit) may be incorporated in one pixel.

Further, although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure, and for example, it is applied to a bottom gate type (reverse stagger type) TFT or forward stagger type TFT Is possible.

The present invention configured as described above will be described in more detail in the following examples.

Here, a pixel portion (n-channel TFT and p-channel TFT) and a TFT (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion are simultaneously manufactured on the same substrate to form an OLED. A manufacturing method for manufacturing the light emitting device having the light emitting device will be described in detail.

First, a heat-resistant glass substrate (first substrate 300) having a thickness of 0.7 mm is formed by plasma CVD as a lower layer 301 of a base insulating film by plasma CVD at a deposition temperature of 400 ° C., source gases SiH ₄ and NH _3. , A silicon oxynitride film produced from N ₂ O (composition ratio Si = 32%, O =
27%, N = 24%, H = 17%) are formed to 50 nm (preferably 10 to 200 nm). Next, the surface is washed with ozone water, and then the oxide film on the surface is removed with dilute hydrofluoric acid (1/100 dilution). Next, as the upper layer 302 of the base insulating film, the film forming temperature is 400 ° C. by plasma CVD.
Silicon oxynitride film produced from source gases SiH ₄ and N ₂ O (composition ratio Si = 32%, O =
A laminated film of 59%, N = 7%, H = 2%) is formed to a thickness of 100 nm (preferably 50 to 200 nm), and the film forming temperature is 300 ° C. by plasma CVD without opening to the atmosphere. _Four
The semiconductor film (in this case, an amorphous silicon film) having an amorphous structure at a thickness of 54 nm
Preferably, it is formed in 25-80 nm.

Although the base insulating film 104 is described as having a two-layer structure in this embodiment, the base insulating film 104 may be formed as a single-layer film or two or more layers of an insulating film containing silicon as a main component. Although there is no limitation on the material of the semiconductor film, preferably silicon or silicon germanium _{(Si X Ge 1-X (} X = 0.
0001 to 0.02)) An alloy or the like may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method or the like). The plasma CVD apparatus may be a single wafer apparatus or a batch apparatus. In addition, the base insulating film and the semiconductor film may be continuously formed without being exposed to the air in the same film formation chamber.

Next, after cleaning the surface of the semiconductor film having an amorphous structure, the surface is approximately 2 nm in ozone water.
Form a very thin oxide film. Next, doping with a slight amount of impurity element (boron or phosphorus) is performed to control the threshold value of the TFT. Here, ion doping method is used in which plasma excitation is performed without mass separation of diborane (B ₂ H ₆ ), and the doping condition is acceleration voltage 15 kV,
Diborane diluted with hydrogen to 1% gas flow rate 30 sccm, dose 2 × 10 ¹² / c
Boron was added to the amorphous silicon film at m ² .

Next, a nickel acetate solution containing 10 ppm of nickel by weight was applied with a spinner. Instead of coating, a method may be used in which the nickel element is dispersed over the entire surface by sputtering.

Next, heat treatment is performed to cause crystallization to form a semiconductor film having a crystal structure.
The heat treatment may be heat treatment of an electric furnace or irradiation of intense light. When heat treatment is performed in an electric furnace, the heat treatment may be performed at 500 ° C. to 650 ° C. for 4 to 24 hours. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) was performed to obtain a silicon film having a crystal structure. Although the crystallization is performed using heat treatment using a furnace here, the crystallization may be performed using a lamp annealing apparatus that can perform crystallization in a short time. Although a crystallization technique using nickel as a metal element for promoting the crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, the laser light (XeCl: wavelength 308 n) is used to increase the crystallization rate and repair defects left in the crystal grains.
The irradiation of m) is performed in the air or in an oxygen atmosphere. As the laser light, an excimer laser light having a wavelength of 400 nm or less, or a second or third harmonic of a YAG laser is used. Here, using a pulse laser beam with a repetition frequency of about 10 to 1000 Hz, the laser beam is condensed to 100 to 500 mJ / cm ² with an optical system and irradiated with an overlap ratio of 90 to 95%, and the silicon film surface Scan it. Here, the repetition frequency 30 Hz, energy density 4
The laser light was applied at 70 mJ / cm ² in the atmosphere. In addition, since it carries out in air | atmosphere or oxygen atmosphere, an oxide film is formed in the surface by irradiation of a laser beam. Note that although an example using a pulse laser is shown here, a continuous wave laser may be used, and in crystallization of an amorphous semiconductor film, continuous wave oscillation is possible to obtain crystals with a large grain size. It is preferable to apply the second to fourth harmonics of the fundamental wave using a solid-state laser. Typically, the second harmonic (532 nm) or the third harmonic (355 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. When a continuous wave laser is used, laser light emitted from a continuous wave YVO ₄ laser with an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting a harmonic by inserting a YVO ₄ crystal and a non-linear optical element into a resonator. Then, the laser light is preferably formed into a rectangular or elliptical laser light on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, the semiconductor film may be moved and irradiated relatively to the laser light at a speed of approximately 10 to 2000 cm / s.

Here, although the technique of applying laser light after performing thermal crystallization using nickel as a metal element for promoting crystallization of silicon was used here, a continuous wave laser (YVO ₄ without adding nickel is used. The amorphous silicon film may be crystallized by the second harmonic of the laser).

Next, after removing the oxide film formed by the laser light irradiation with dilute hydrofluoric acid, the surface is treated with ozone water for 120 seconds to form a barrier layer consisting of an oxide film of 1 to 5 nm in total. Here, a barrier layer is formed using ozone water, but the surface of a semiconductor film having a crystal structure is oxidized by irradiation of ultraviolet light in an oxygen atmosphere, or the surface of a semiconductor film having a crystal structure is oxidized by oxygen plasma treatment. An oxide film of about 1 to 10 nm may be deposited by a method, plasma CVD method, sputtering method, evaporation method or the like to form a barrier layer. In the present specification, the barrier layer refers to a layer having a film quality or film thickness through which a metal element can pass in the gettering step, and a layer serving as an etching stopper in the removal step of the layer to be the gettering site.

Next, an amorphous silicon film containing an argon element to be a gettering site is formed over the barrier layer by sputtering to a thickness of 50 nm to 400 nm, which is 150 nm here. The film forming conditions here are a film forming pressure of 0.3 Pa, a gas (Ar) flow rate of 50 (sccm), a film forming power of 3 kW, and a substrate temperature of 150 ° C. The atomic concentration of argon contained in the amorphous silicon film under the above conditions is 3 × 10 ²⁰ / cm ^{3 to} 6 × 10 ²⁰ / cm ³ , and the atomic concentration of oxygen is 1 × 10 ¹⁹ / cm ³ It is 3 × 10 ¹⁹ / cm ³ . Then, using an electric furnace 550
C. for 4 hours for gettering to reduce the nickel concentration in the semiconductor film having a crystal structure.
A lamp annealing apparatus may be used instead of the electric furnace.

Next, the amorphous silicon film containing an argon element, which is a gettering site, is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that since nickel tends to move to a region with high oxygen concentration during gettering, it is preferable to remove the barrier layer made of an oxide film after gettering.

Next, a thin oxide film is formed with ozone water on the surface of the obtained silicon film (also called polysilicon film) having a crystal structure, a mask made of a resist is formed, and etching is performed to a desired shape to form islands. Form a semiconductor layer separated into After the semiconductor layer is formed, the resist mask is removed.

Next, after removing the oxide film with an etchant containing hydrofluoric acid and simultaneously cleaning the surface of the silicon film, an insulating film containing silicon as a main component to be the gate insulating film 303 is formed. here,
Silicon oxynitride film (composition ratio Si = 32%, thickness 115 nm by plasma CVD method
O = 59%, N = 7%, H = 2%).

Next, a first conductive film with a thickness of 20 to 100 nm and a thickness of 100 to 40 on the gate insulating film
A second conductive film of 0 nm is stacked. In the present embodiment, a film thickness of 5 on the gate insulating film 303
A 0 nm tantalum nitride film and a tungsten film having a thickness of 370 nm are sequentially stacked, and patterning is performed according to the following procedure to form gate electrodes and wirings.

As a conductive material for forming the first conductive film and the second conductive film, Ta, W, Ti, Mo,
It is formed of an element selected from Al, Cu, or an alloy material or compound material containing the above element as a main component. Alternatively, as the first conductive film and the second conductive film, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used. Further, the present invention is not limited to the two-layer structure, and for example, a tungsten film having a film thickness of 50 nm, a film thickness of 500 n
A three-layer structure in which an aluminum-silicon alloy (Al-Si) film of m and a titanium nitride film with a film thickness of 30 nm are sequentially stacked may be used. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum and silicon (Al-Si) film of the second conductive film may be used instead of aluminum. An alloy film of titanium (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.

It is preferable to use an ICP (Inductively Coupled Plasma) etching method for etching the first conductive film and the second conductive film (the first etching process and the second etching process). The film is formed into a desired tapered shape by appropriately adjusting the etching conditions (the amount of power applied to the coil type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) Can be etched. here,
After forming a mask made of resist, 700 W RF (13.56 MHz) power is applied to the coil type electrode at a pressure of 1 Pa as the first etching condition, and CF ₄ and Cl ₂ are used as etching gases.
And the O ₂ gas, and the respective gas flow rate ratio is 25/25/10 (sccm),
In the sample stage, 150 W of RF (13.56 MHz) power is applied, and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil type electrode area size (here, a quartz disk provided with a coil) has a diameter of 25 c.
It is a disk of m. Under the first etching conditions, the W film is etched to make the end portion tapered. After that, the second etching conditions are changed without removing the resist mask, and CF ₄ and Cl ₂ are used as etching gases, and the gas flow ratio of each is 30/30 (sc
cm), and an RF (13.56 MHz) power of 500 W was applied to the coil type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. 2 on the substrate side (sample stage)
Apply 0 W RF (13.56 MHz) power and apply a substantially negative self-bias voltage. CF ₄
The second etching conditions using the gas mixture of Cl ₂ are etched to the same extent, the W film and the TaN film. Here, the first etching condition and the second etching condition are referred to as a first etching process.

Next, a second etching process is performed without removing the resist mask.
Here, as the third etching conditions, CF ₄ and Cl ₂ are used as etching gases, the gas flow ratio of each is set to 30/30 (sccm), and a pressure of 1 Pa is applied to the coil type electrode 500
An RF (13.56 MHz) power of W was applied to generate plasma, and etching was performed for 60 seconds. 20 W RF (13.56 MHz) on the substrate side (sample stage)
Power is applied and a substantially negative self bias voltage is applied. After that, the fourth etching conditions are changed without removing the resist mask, and CF ₄ , Cl ₂ and O ₂ are used as etching gases.
And generate a plasma by supplying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa with a gas flow ratio of 20/20/20 (sccm) for each of about 20 seconds. Etching was done. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Note that here, the third etching condition and the fourth etching condition are referred to as a second etching process. At this stage, the gate electrode 304 has the first conductive layer 304 a as a lower layer and the second conductive layer 304 b as an upper layer.
And each of the electrodes 305 to 307 is formed. At this stage, the top surface structure of the pixel may be, for example, that shown in FIG.

Next, after removing a mask made of resist, a first doping process is performed to dope the entire surface using the gate electrodes 304 to 307 as a mask. The first doping treatment may be performed by ion doping or ion implantation. The conditions for the ion doping method are:
The acceleration voltage is set to 5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage is set to 60 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as an impurity element imparting n-type. First impurity regions (n ^- regions) 322 to 325 are formed in a self-aligned manner.

Next, a mask made of resist is newly formed, but at this time, the switching TFT 4 is formed.
In order to reduce the off current value of 03, the mask is formed to cover the channel formation region of the semiconductor layer forming the switching TFT 403 of the pixel portion 401 and a part thereof. The mask is also provided to protect the channel formation region of the semiconductor layer forming the p-channel TFT 406 of the driver circuit and the peripheral region thereof. In addition, the mask is used for current control T of the pixel portion 401.
It is formed to cover the channel formation region of the semiconductor layer forming the FT 404 and the region around it.

Next, a second doping process is selectively performed using a mask made of the above resist to form an impurity region (n ⁻ region) overlapping with part of the gate electrode. The second doping treatment may be performed by ion doping or ion implantation. Here, ion doping is performed, a gas obtained by diluting phosphine (PH ₃ ) with hydrogen to 5% is used at a flow rate of 30 sccm, a dose amount is 1.5 × 10 ¹⁴ atoms / cm ² , and an acceleration voltage is 90 keV. In this case, the mask made of resist and the second conductive layer serve as a mask for the impurity element imparting n-type conductivity, whereby the second impurity regions 311 and 312 are formed. 1 × 10 ¹⁶ to the second impurity region
An impurity element imparting n-type is added in a concentration range of 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the second impurity region is also referred to as an n ⁻ region.

Next, a third doping process is performed without removing the resist mask.
The third doping process may be performed by ion doping or ion implantation.
Typically, phosphorus (P) or arsenic (As) is used as an impurity element imparting n-type.
Here, a gas obtained by diluting phosphine (PH ₃ ) to 5% by ion doping is used at a flow rate of 40 sccm, a dose amount of 2 × 10 ¹⁵ atoms / cm ² , and an acceleration voltage of 80 keV
Do as. In this case, the mask made of resist and the first conductive layer and the second conductive layer serve as masks for the impurity element imparting n-type conductivity, and the third impurity regions 313, 314, and 326.
~ 328 are formed. An impurity element imparting n-type conductivity is added to the third impurity region in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the third impurity region is also referred to as an n ⁺ region.

Next, after removing the mask made of resist, a mask made of resist is newly formed and a fourth doping process is performed. Fourth impurity regions 318, 319, 332, and 333 in which an impurity element imparting p-type conductivity is added to a semiconductor layer for forming a semiconductor layer for forming a p-channel TFT by a fourth doping process 5 impurity regions 316 and 317
, 330, 331.

In addition, 1 × 10 ²⁰ to 1 × 10 ²¹ / c can be added to the fourth impurity regions 318, 319, 332, and 333.
An impurity element imparting p-type is added in a concentration range of m ³ . Note that phosphorus (P) is added to the fourth impurity regions 318, 319, 332, 333 in the previous step.
In the region (n ^- region) where the concentration of the impurity element imparting p-type is 1.5
The conductivity type is p-type because it is added by ~ 3 times. Here, a region having the same concentration range as the fourth impurity region is also referred to as ap ⁺ region.

The fifth impurity regions 316, 317, 330, and 331 are formed in a region overlapping with the tapered portion of the second conductive layer, and have a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. An impurity element imparting p-type is added. Here, a region having the same concentration range as the fifth impurity region is also referred to as ap ⁻ region.

Through the above steps, an impurity region having n-type or p-type conductivity is formed in each semiconductor layer. The conductive layers 304 to 307 become gate electrodes of the TFT.

Next, an insulating film (not shown) covering almost the entire surface is formed. In the present embodiment, plasma C
A 50 nm thick silicon oxide film was formed by the VD method. Of course, this insulating film is not limited to a silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step may be a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating YAG laser or excimer laser from the back side, a heat treatment using a furnace, or a combination of any of these methods. Do it the same way.

Further, although the example in which the insulating film is formed before the activation is described in this embodiment, the step of forming the insulating film may be performed after the activation is performed.

Next, a first interlayer insulating film 308 made of a silicon nitride film is formed and heat treatment (300 to
A heat treatment is performed at 550 ° C. for 1 to 12 hours to perform a step of hydrogenating the semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer by hydrogen contained in the first interlayer insulating film 308. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation.

Then, a second interlayer insulating film 309 made of an organic insulating material is formed on the first interlayer insulating film 308.
Form In this embodiment, an acrylic resin film 309a having a thickness of 1.6 μm is formed by a coating method, and a 200 nm silicon nitride film 309b is further stacked by a sputtering method. Note that
Although an example in which a silicon nitride film is stacked on an acrylic resin of 1.6 μm is shown here, the material or thickness of the interlayer insulating film is not particularly limited, and the gate electrode and the power supply line formed thereon are used. In the case of forming a capacitance between the two, appropriately, the film thickness of the organic insulating film or the inorganic insulating film is 0.5 μm.
It may be about 2.0 μm.

Next, a pixel electrode 334 is formed in contact with the drain region of the current control TFT 404 composed of a p-channel TFT and in contact with and overlapping with a connection electrode formed later. In this embodiment,
The pixel electrode functions as an anode of the OLED, and is a transparent conductive film in order to pass the light emission of the OLED to the pixel electrode.

Then, a contact hole reaching the conductive layer to be a gate electrode or a gate wiring and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, after the third interlayer insulating film is etched using the second interlayer insulating film as an etching stopper, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and then the first interlayer is formed. The insulating film was etched.

Thereafter, electrodes 335 to 341, specifically, a source wiring, a power supply line, an extraction electrode, a connection electrode, and the like are formed using Al, Ti, Mo, W, and the like. Here, patterning was performed using a laminated film of a Ti film (film thickness 100 nm), an Al film (film thickness 350 nm) containing silicon, and a Ti film (film thickness 50 nm) as the materials of these electrodes and wirings. Thus, source electrodes and source wirings, connection electrodes, extraction electrodes, power supply lines, and the like are formed as appropriate. Note that a lead-out electrode for contacting the gate wiring covered with the interlayer insulating film is provided at an end of the gate wiring, and the end of each of the other wirings is also connected to an external circuit or an external power supply. An input / output terminal portion in which a plurality of electrodes are provided is formed. A connection electrode 341 provided in contact with and overlapping the pixel electrode 334 formed earlier is in contact with the drain region of the current control TFT 404.

As described above, the driver circuit 402 includes the n-channel TFT 405, the p-channel TFT 406, and the CMOS circuit in which these are complementarily combined, and a plurality of n-channel TFT 403 or p-channel TFT 404 in one pixel. The pixel portion 401 can be formed.

In this embodiment, the length of the channel forming region 329 of the p-channel TFT 404 connected to the OLED 400 is made extremely long. For example, the top structure may be as shown in FIG. In FIG. 5, the length of the channel length L is 500 μm. The channel width W was 4 μm.

After patterning of each electrode is completed, the resist is removed and heat treatment is performed, and then insulators 342a and 342b called banks are formed at both ends so as to cover the end of the pixel electrode 334. The banks 342a and 342b may be formed of an insulating film or a resin film containing silicon.
Here, after the insulating film made of an organic resin film is patterned to form the bank 342a,
A silicon nitride film is formed by sputtering and patterned to form a bank 342b.

Then, the EL layer 343 and the OLED are formed on the pixel electrode 334 covered at both ends with the bank.
Form the cathode 344 of the

As the EL layer 343, a light emitting layer, a charge transport layer, or a charge injection layer may be combined freely.
An L layer (a layer for emitting light and moving a carrier therefor) may be formed. For example, low molecular weight organic EL materials or high molecular weight organic EL materials may be used. Alternatively, a thin film of a light emitting material (singlet compound) which emits light (fluorescent light) by singlet excitation or a thin film of a light emitting material (triplet compound) which emits light (phosphorescence) by triplet excitation can be used as the EL layer. In addition, it is also possible to use an inorganic material such as silicon carbide as the charge transport layer or the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In addition, as a material used for the cathode 344, a metal having a small work function (typically, one of the periodic table
It is said that it is preferable to use an alloy containing these or a metal element belonging to group 2 or group 2). Among them, an alloy material containing Li (lithium), which is one of alkali metals, is desirable as a material used for the cathode, because the smaller the work function, the higher the light emission efficiency. The cathode also functions as a wiring common to all the pixels, and has a terminal electrode at the input terminal portion via the connection wiring.

  FIG. 7 shows the stage where the steps up to here are completed.

Then, by sealing the OLED having at least the cathode, the organic compound layer, and the anode with an organic resin, a protective film, a sealing substrate, or a sealing can, the OLED is completely shielded from the outside, moisture and It is preferable to prevent entry of a substance such as oxygen which accelerates deterioration of the EL layer by oxidation. However, a protective film or the like may not be provided on the input / output terminal portion which needs to be connected to the FPC later.

Then, a flexible printed circuit (FPC) is attached to each electrode of the input / output terminal portion with an anisotropic conductive material. The anisotropic conductive material is made of resin and conductive particles with a diameter of several tens to several hundreds of μm, the surface of which is plated with Au or the like, and is formed on each electrode of the input / output terminal portion and FPC by conductive particles. The wiring is electrically connected.

In addition, if necessary, an optical film such as a circularly polarizing plate including a polarizing plate and a retardation plate may be provided, or an IC chip may be mounted.

  Through the above steps, the module-type light emitting device to which the FPC is connected is completed.

Further, in the case of full color display, an equivalent circuit diagram in a pixel portion of this embodiment is shown in FIG.
Reference numeral 701 in FIG. 8 corresponds to the switching TFT 403 in FIG. 7, and reference numeral 702 corresponds to the current control TFT 404. In the pixel for displaying red, the OLED 703R for emitting red light is connected to the drain region of the current control TFT 404, and the anode side power supply line (R) 706R is provided in the source region. In the OLED 703 R, the cathode side power supply line 70
0 is provided. Further, in the pixel displaying green, the OLED 703 G emitting green light is connected to the drain region of the current control TFT, and the anode side power supply line (G) 7 is connected to the source region.
06G is provided. In the pixel displaying blue, the OLED 703B emitting blue is connected to the drain region of the current control TFT, and the anode side power supply line (B
) 706B is provided. Different voltages are applied to pixels of different colors depending on the EL material. In the present embodiment, in order to reduce the channel conductance gd,
The channel length is lengthened, and it is driven in the on state at a gate voltage value much higher than that of the prior art.

Here, as a display driving method, a time-division gray scale driving method which is one of line-sequential driving methods is used. Also, the video signal input to the source line may be an analog signal,
It may be a digital signal, and a driver circuit or the like may be designed appropriately in accordance with the video signal.

In this embodiment, FIGS. 13A and 13B are top views which are partially different from the top views (FIGS. 5 and 6) in which a part of the pixel portion in Example 1 is enlarged.

FIG. 13A is a top view corresponding to FIG. 6, and the same parts use the same reference numerals.
FIG. 13A shows an example in which semiconductor layers 1102 having different patterning shapes are used instead of the semiconductor layer 102 in FIG. Here, the semiconductor layer 1102 is made to meander. In FIG. 13A, channel length L × channel width W is the same as that in FIG. 6, and 500 μm × 4.
It is assumed to be μm. FIG. 13A is the same as that of the first embodiment except for the semiconductor layer 1102 having a different patterning shape, so that the description of the other parts may be referred to the first embodiment.

Further, FIG. 13B shows another top view different from the above. The same parts as in FIG. 6 use the same reference numerals. FIG. 13B shows an example in which the semiconductor layer 1202 in FIG. 6 is replaced with semiconductor layers 1202 with different patterning shapes, and the electrode 100 is replaced with electrodes 1200 with different patterning shapes. In FIG. 13B, the channel length is 165 μm. Figure 1
3 (B) shows Example 1 except the semiconductor layer 1202 and the electrode 1200 which have different patterning shapes.
The other parts may be referred to the first embodiment.

  Further, this embodiment can be freely combined with Embodiment Mode or Embodiment 1.

The top view and sectional drawing of a modular type light-emitting device (it is also called an EL module) obtained by Example 1 or Example 2 are shown.

6A is a top view showing the EL module, and FIG. 14B is a cross-sectional view taken along the line A-A 'of FIG.
It is sectional drawing cut | disconnected. In FIG. 14A, a base insulating film 501 is provided over a substrate 500 (for example, a heat resistant glass or the like), and a pixel portion 502, a source driver circuit 504, and the like are formed over the base insulating film 501.
And the gate side drive circuit 503 is formed. These pixel portions and drive circuits can be obtained according to the first embodiment and the second embodiment.

Further, 518 is an organic resin, 519 is a protective film, the pixel portion and the driver circuit portion are covered with the organic resin 518, and the organic resin is covered with the protective film 519. Furthermore, an adhesive may be used to seal with a cover material. The cover material may be adhered before peeling as a support.

Reference numeral 508 denotes a wiring for transmitting signals input to the source side drive circuit 504 and the gate side drive circuit 503, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 509 serving as an external input terminal. Although only the FPC is illustrated here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in this specification includes not only the light emitting device main body but also the FPC or P
It also includes the state in which the WB is attached.

Next, the cross-sectional structure will be described with reference to FIG. The base insulating film 501 is provided in contact with the substrate 500, and the pixel portion 502 and the gate driver circuit 503 are provided above the insulating film 501.
The pixel portion 502 is formed of a plurality of pixels including the current control TFT 511 and the pixel electrode 512 electrically connected to the drain thereof. In addition, gate side drive circuit 5
03 is a CMOS combining n-channel TFT 513 and p-channel TFT 514
It is formed using a circuit.

These TFTs (including 511, 513 and 514) are n-channel type T of the first embodiment.
It may be fabricated according to FT, the p-channel TFT of Example 1 above.

Note that the pixel portion 502, the source driver circuit 504, and the gate driver circuit 503 are formed over the same substrate in accordance with the first embodiment.

The pixel electrode 512 functions as a cathode of a light emitting element (OLED). In addition, the pixel electrode 512
Banks 515 are formed at both ends of the pixel electrode 512, and an organic compound layer 516 and an anode 517 of a light emitting element are formed on the pixel electrode 512.

As the organic compound layer 516, a light emitting layer, a charge transporting layer, or a charge injecting layer may be freely combined to form an organic compound layer (a layer for emitting light and moving a carrier therefor). For example, low molecular weight organic compound materials or high molecular weight organic compound materials may be used. In addition, a thin film made of a light emitting material (singlet compound) which emits light (fluorescent light) by singlet excitation or a thin film made of a light emitting material (triplet compound) which emits light (phosphorescence) by triplet excitation is used as the organic compound layer 516 it can. In addition, it is also possible to use an inorganic material such as silicon carbide as the charge transport layer or the charge injection layer. Known materials can be used as these organic materials and inorganic materials.

The anode 517 also functions as a wiring common to all pixels, and the FPC 5 is connected through the connection wiring 508.
It is electrically connected to 09. Further, all elements included in the pixel portion 502 and the gate driver circuit 503 are covered with an anode 517, an organic resin 518, and a protective film 519.

As the organic resin 518, it is preferable to use a material that is as transparent or translucent as possible to visible light. In addition, it is desirable that the organic resin 518 be a material which transmits as little moisture and oxygen as possible.

In addition, after completely covering the light emitting element with the organic resin 518, it is preferable to provide a protective film 519 on the surface (exposed surface) of the organic resin 518 as shown at least in FIG. Also,
A protective film may be provided on the entire surface including the back surface of the substrate 500. Here, the external input terminal (FPC)
It is necessary to be careful not to deposit a protective film on the portion where the. The protective film may not be formed using a mask, or the external input terminal portion is covered with a tape such as Teflon (registered trademark) used as a masking tape in a CVD apparatus so that the protective film is not formed. It is also good. As the protective film 519, a silicon nitride film, a DLC film, or AlN _X O _Y
A membrane may be used.

By sealing the light emitting element with the protective film 519 having the above structure, the light emitting element can be completely shut off from the outside, and a substance which promotes deterioration due to oxidation of the organic compound layer such as water or oxygen penetrates from the outside You can prevent it. Therefore, a highly reliable light emitting device can be obtained.

In addition, a pixel electrode is used as a cathode, and an organic compound layer and a light transmitting anode are laminated as shown in FIG.
The light may be emitted in the opposite direction. Alternatively, the pixel electrode may be used as an anode, and the organic compound layer and the cathode may be stacked to emit light in the direction opposite to that in FIG.
An example is shown in FIG. The top view is omitted because it is the same.

The cross-sectional structure shown in FIG. 15 will be described below. An insulating film 610 is provided on a substrate 600, and a pixel portion 602 and a gate driver circuit 603 are formed above the insulating film 610. The pixel portion 602 is electrically connected to the current control TFT 611 and its drain. It is formed by a plurality of pixels including the pixel electrode 612. The gate driver circuit 603 is formed using a CMOS circuit in which an n-channel TFT 613 and a p-channel TFT 614 are combined.

These TFTs (including 611, 613 and 614) are n-channel type T of the first embodiment.
It may be fabricated according to FT, the p-channel TFT of Example 1 above.

The pixel electrode 612 functions as an anode of a light emitting element (OLED). In addition, the pixel electrode 612
Banks 615 are formed at both ends of the pixel electrode 612, and an organic compound layer 616 and a cathode 617 of the light emitting element are formed on the pixel electrode 612.

The cathode 617 also functions as a wiring common to all pixels, and the FPC 6 via the connection wiring 608
It is electrically connected to 09. Further, all elements included in the pixel portion 602 and the gate driver circuit 603 are covered with the cathode 617, the organic resin 618, and the protective film 619. Furthermore, the cover material 620 may be bonded with an adhesive.
In addition, a recess may be provided in the cover member 620 and the desiccant 621 may be provided.

Further, in FIG. 15, since the pixel electrode is an anode and the organic compound layer and the cathode are stacked, the light emission direction is the direction of the arrow shown in FIG.

Further, although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure, and for example, it is applied to a bottom gate type (reverse stagger type) TFT or forward stagger type TFT Is possible.

Module having an OLED by practicing the present invention (active matrix type E
All electronic devices incorporating the L module) are completed.

As such electronic devices, video cameras, digital cameras, head mounted displays (goggle type displays), car navigation systems, projectors, car stereos, etc.
Personal computers, portable information terminals (mobile computers, mobile phones, electronic books, etc.) and the like can be mentioned. Examples of those are shown in FIGS.

FIG. 16A shows a personal computer, which includes a main body 2001, an image input unit 2002, a display unit 2003, a keyboard 2004, and the like.

FIG. 16B shows a video camera, which has a main body 2101, a display portion 2102, and an audio input portion 210.
3 includes an operation switch 2104, a battery 2105, an image receiving unit 2106, and the like.

FIG. 16C shows a mobile computer (mobile computer), which is a main body 2201,
It includes a camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205 and the like.

FIG. 16D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like.

FIG. 16E shows a player using a recording medium storing a program (hereinafter referred to as a recording medium), and a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404,
Operation switch 2405 etc. are included. Note that this player is a DVD (Dig) as a recording medium.
Using a tial Versatile Disc), a CD, etc., it is possible to perform music appreciation, movie appreciation, games and the Internet.

FIG. 16F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece 250
3 includes an operation switch 2504, an image receiving unit (not shown), and the like.

FIG. 17A shows a mobile phone, which has a main body 2901, an audio output portion 2902, and an audio input portion 29.
03, display portion 2904, operation switch 2905, antenna 2906, image input portion (CCD
, Image sensor etc.) 2907 etc.

FIG. 17B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003.
3 includes a storage medium 3004, an operation switch 3005, an antenna 3006 and the like.

FIG. 17C shows a display, which is a main body 3101, a support base 3102, a display portion 3103.
Etc.

By the way, the display shown in FIG.
The screen size is in inches. In addition, in order to form a display portion of such a size, it is preferable to mass-produce by using a substrate with one side of 1 m and performing multiple chamfers.

As described above, the scope of application of the present invention is so wide that it can be applied to manufacturing methods of electronic devices in various fields. Further, the electronic device of the present embodiment can be realized by using a configuration including any combination of the embodiment and the embodiments 1 to 3.

Claims (1)

A light emitting device comprising a light emitting element having a cathode, an organic compound layer in contact with the cathode, and an anode in contact with the organic compound layer,
The channel length L of the TFT connected to the light emitting element is 100 μm or more.

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