JP5008223B2 - Active matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
[0002]
The present invention relates to a color image display device (active matrix color image display device) for displaying information such as video by switching elements and pixels arranged in a matrix, particularly a digital driving method and image display using the same. The present invention relates to devices and electronic devices.
[0003]
[Prior art]
Recently, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT) has been rapidly developed. This is because the demand for active matrix image display devices has increased.
[0004]
Active matrix image display devices include active matrix liquid crystal display devices that use liquid crystals as display elements and EL display devices that use electroluminescence (EL) elements. Hereinafter, an active matrix liquid crystal display device will be described as an example as a typical example of an active matrix image display device.
[0005]
As shown in FIG. 30, the active matrix liquid crystal display device includes a source signal line drive circuit 101, a gate signal line drive circuit 102, and a pixel array unit 103 arranged in a matrix. The source signal line driver circuit 101 samples an input video signal in synchronization with a timing signal such as a clock signal and writes data to each source signal line 104. The gate signal line driving circuit 102 sequentially selects the gate signal lines 105 in synchronization with the timing of the clock signal or the like, and turns on / off the TFT (pixel TFT) 106 that is a switching element in each pixel of the pixel array unit 103. It comes to control off. As a result, data written to each source signal line 104 is sequentially written to each pixel.
[0006]
There are an analog method and a digital method as a driving method of the source signal line driver circuit, and a digital active matrix liquid crystal display device capable of high-definition and high-speed driving has been attracting attention.
[0007]
A conventional digital source signal line driver circuit is shown in FIG. In FIG. 31, reference numeral 201 denotes a shift register unit, which is composed of a shift register basic circuit 202 including a flip-flop circuit and the like. When the start pulse SP is input to the shift register unit 201, sampling pulses are sequentially sent to the latch 1 circuit 203 (LAT1) in synchronization with the clock signal CLK.
[0008]
The latch 1 circuit 203 (LAT1) is an n-bit (n is a natural number) digital signal supplied from a data bus line (DATA-R, DATA-G, DATA-B) in synchronization with a sampling pulse from the shift register unit. Video signals are stored sequentially.
[0009]
After a signal for one horizontal pixel is written to the LAT1 portion, the digital video signal held in each latch 1 circuit 203 (LAT1) is synchronized with the latch pulse supplied from the latch signal bus line (LP). The data is transferred all at once to the latch 2 circuit 204 (LAT2).
[0010]
When the digital video signal is held in the latch 2 circuit 204 (LAT2), the start pulse (SP) is input again, and the digital video signal for the pixel in the next row is newly written in the LAT1 portion. During this time, the digital video signal for the pixels in the previous row is stored in the LAT2 section, and the digital video signal is converted into a digital video signal by a digital / analog signal conversion circuit (hereinafter referred to as a D / A conversion circuit) 205 (D / A). A corresponding analog video signal is written to each source signal line. In FIG. 31, Vref-R, Vref-G, and Vref-B are gradation power supplies connected to the D / A conversion circuit 205 corresponding to each color of R (red), G (green), and B (blue), respectively. Show the line. SL1, SL2,... Are numbered source signal lines, and R, G, B shown below SL1, etc. are red, green, and blue, respectively. Is assumed.
[0011]
Each D / A conversion circuit 205 shown in FIG. 31 is connected to one source signal line and writes an analog video signal to the one source signal line. However, when creating a high-resolution and high-definition liquid crystal display device, it is an obstacle to miniaturization of a liquid crystal display device that has been desired in recent years to make the same number of D / A conversion circuits occupying a large area as the source signal lines. Japanese Patent Laid-Open No. 11-167373 proposes a method of driving a plurality of source signal lines with one D / A conversion circuit.
[0012]
FIG. 32 shows a configuration example of a source signal line driver circuit that drives four source signal lines with one D / A conversion circuit. As can be seen from comparison with FIG. 31, a parallel / serial conversion circuit 301 (P / S conversion circuit), a source line selection circuit 302, and a selection signal (SS) input thereto are newly added to FIG. . Even if such a circuit is added, if one D / A converter circuit can write a signal to four source signal lines, the number of necessary D / A converter circuits can be reduced to ¼. Largely, the area occupied by the source signal line driving circuit can be reduced.
[0013]
[Problems to be solved by the invention]
In FIG. 31, three independent gradation power supply lines for RGB are supplied to the source signal line driving circuit. However, unlike the source signal line driver circuit shown in FIG. 32, only one gray scale power supply line is supplied unlike FIG. Generally, when the power supply voltage of the gradation power supply line is given, the output voltage range of the D / A conversion circuit is uniquely determined. Accordingly, in the source signal line driver circuit of FIG. 32 to which one system of gradation power supply line is supplied, the voltage range written to each source signal line is the same regardless of RGB.
[0014]
Now, the dependency of the luminance ratio of the liquid crystal display device on the liquid crystal applied voltage is not exactly the same for each color of RGB, but differs depending on the color as in the example shown in FIG. In this example, the voltage values at which the luminance ratio takes a minimum value are different from VR, (<) VG, and (<) VB for RGB. Therefore, the maximum voltage that can be applied to the liquid crystal is VR, VG, and VB for each of RGB so that the monotonicity of gradation expression is not lost when a voltage is applied to the liquid crystal. However, when only one gray scale power supply line as shown in FIG. 32 is supplied, the voltage range that can be applied to the liquid crystal becomes uniform without distinction between RGB as described above, and therefore has the luminance ratio-voltage characteristic of FIG. For the liquid crystal, the maximum voltage that can be applied is VR. At this time, there is a problem that G and B are not sufficiently dark, the contrast is lowered, and accurate color expression is poor.
[0015]
For the above reasons, it is desirable that the grayscale power supply lines are also supplied in three independent RGB systems as shown in FIG. 31 so that the voltage applied to the liquid crystal can be controlled independently of RGB.
[0016]
However, when a plurality of source signal lines are driven by a single D / A conversion circuit by the above-described method of supplying the three systems of gradation power supply lines, not only the number of gradation power supply lines is increased, but those levels are also increased. A switch for switching the connection between one of the regulated power supply lines and the D / A conversion circuit is required. These cause new problems such as an increase in the number of external input pins, an increase in the area occupied by the drive circuit due to the area where the gradation power supply line is wired, the above-described additional switch and the like. This eliminates the advantage of driving a plurality of source signal lines with a single D / A conversion circuit and reducing the area occupied by the drive circuit.
[0017]
Therefore, the present invention provides a driving method that solves these problems.
[0018]
[Means for Solving the Problems]
The gradation power supply line supplied to the source signal line drive circuit is only one system, and each D / A converter circuit uses three source signal lines corresponding to RGB as a unit, and an analog video for the multiple source signal lines. Write signal. Further, the power supply voltage of the gradation power supply line is also changed within one horizontal writing period. Each source line selection circuit synchronizes the period for selecting the source signal line corresponding to each color of RGB, and the power supply voltage applied to the gradation power supply line corresponds to R during the period when the R source signal line is selected. A power supply voltage corresponding to G is applied during a period when the G source signal line is selected, and a power supply voltage corresponding to B is applied during a period when the B source signal line is selected.
[0019]
This makes it possible to control the voltage of the pixel electrode independently of RGB without causing an increase in the number of external input pins and an increase in the area occupied by the drive circuit.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021]
[Embodiment]
In the present embodiment, a method will be described in which one gradation power supply line is supplied to the source signal line driving circuit, and each D / A conversion circuit drives three source signal lines corresponding to RGB.
[0022]
Further, in the present embodiment, a case will be described as an example corresponding to digital video signal input of (n + 1) bits (n is a natural number) for each of RGB colors.
[0023]
FIG. 1 shows a schematic circuit diagram of this embodiment. In FIG. 1, a shift register unit that generates sampling pulses for sequentially sampling digital video signals, a latch 1 circuit unit that latches digital video signals by the sampling pulses, and a latch 1 circuit unit that receives latch pulses. A latch 2 circuit portion for latching the stored digital video signals all at once is not shown in the figure. The parallel / serial conversion circuit (P / S conversion circuit) outputs the parallel output data (D0 [3k + 1] to Dn [3k + 1], D0 [3k + 2] to Dn [3k + 2], D0 [3k + 3] to Dn [Dn [ 3k + 3] (k is an integer greater than or equal to 0)) are converted into serial data for each bit signal. Here, D0 [3k + 1] indicates the least significant (first) bit (LSB) digital video signal for the (3k + 1) th source signal line, and Dn [3k + 1] is also the most significant (3k + 1) th source signal line ( The (n + 1) th bit (MSB) digital video signal is shown. Hereinafter, the notation Dl [s] represents the (l + 1) th bit digital video signal for the sth source signal line. The (3k + 1) th source signal line is a source signal line for displaying R, the (3k + 2) th source signal line is for G, and the (3k + 3) th source signal line is for displaying B.
[0024]
The source line selection circuit includes three switches sw1, sw2, and sw3. When sw1 is turned on, the (3k + 1) th source signal line (source signal line in charge of R) is turned on, and when sw2 is turned on, the (3k + 2) th is turned on. When the source signal line (source signal line in charge of G) is turned on, the (3k + 3) th source signal line (source signal line in charge of B) is connected to the output of each D / A conversion circuit. . SS1 to SS3 are selection signals for controlling on / off of sw1 to sw3, respectively.
[0025]
The signal operation timing for the drive circuit of FIG. 1 is shown in FIG. One gate line selection period is divided into three. In the first period, the selection signal SS1 is set to Hi level and sw1 is turned on. In the second period, the selection signal SS2 is set to Hi level and sw2 is turned on. An operation in which the selection signal SS3 is set to the Hi level and the sw3 is turned on in the second period is shown. Note that the output signals (PS0 [k] to PSn [k]) of each P / S conversion circuit are synchronized with the selection signals (SS1 to SS3) described above, and one gate line selection period is divided into three. The digital video signal for the (3k + 1) source signal line is output in the second period, the digital video signal for the (3k + 2) source signal line is output in the second period, and the digital video signal is output in the third period. Control is performed by a selection signal SS input to the P / S conversion circuit so as to output a digital video signal to the (3k + 3) source signal line. In this way, the digital video signal corresponding to each source signal line is reflected in the writing of an appropriate source signal line. This state is shown in PS0 [1] to PSn [1] and PS0 [2] to PSn [2] in FIG. Here, PSl [k] represents the output signal of the (l + 1) th bit of the kth P / S conversion circuit. Therefore, PSl [k] is composed of digital video signals of Dl [3k-2], Dl [3k-1], and Dl [3k]. In FIG. 2, Dl [s, g] indicates the (l + 1) -th bit digital video signal for the pixel in the s-th column and the g-th row, and information on the gate signal line is added to the notation Dl [s]. It is a thing.
[0026]
Next, a method of inputting a power supply voltage to the gradation power supply line Vref is shown in Vref of FIG. In the figure, Vref-R, Vref-G, and Vref-B indicate that the power supply voltage of the gradation power supply line corresponding to each color of R, G, and B is applied. In the first period obtained by dividing one gate line selection period into three, the (3k + 1) th source signal line (source signal line in charge of R) is selected by the source line selection circuit. Is applied to the gradation power supply line. Similarly, power supply voltages for displaying G and B are respectively applied to the gradation power supply lines in the second and third periods obtained by dividing one gate line selection period into three.
[0027]
As described above, according to the present embodiment, in the form in which three source signal lines of RGB are driven by one D / A conversion circuit, only one system of gradation power supply lines is supplied to the source signal line drive circuit. However, the voltage of the pixel electrode can be controlled independently of RGB. In the present embodiment, a case where three source signal lines of RGB are driven by one D / A conversion circuit is taken as an example, but the present invention is not limited to this, and three, The present invention can also be applied to a case where the source signal lines of multiples of 3 such as 6 and so on are driven by one D / A conversion circuit. Further, the order in which the source line selection circuit selects the source signal lines is not limited to the order of R, G, and B as in the present embodiment, and may be in other orders. Furthermore, in the present embodiment, a parallel / serial conversion circuit (P / S conversion circuit) is used, but the present invention is not limited to this. That is, the present invention can be applied to any method in which digital video signals for a plurality of source signal lines are serially input to a D / A conversion circuit for one gate line selection period.
[0028]
【Example】
Now, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following examples.
[0029]
[Example 1]
In this embodiment, an example in which the present invention is applied to an active matrix image display device is shown. As shown in the conventional example, the active matrix image display device includes a source signal line driving circuit, a gate signal line driving circuit, and a pixel array unit arranged in a matrix. Since the operations of the gate signal line driving circuit and the pixel array portion are the same as those of the conventional example, the source signal line driving circuit will be described in this embodiment. As shown in FIG. 3, in this embodiment, the digital video signal for each color of RGB is assumed to be 3 bits, and a case where three source signal lines of RGB are driven by one D / A conversion circuit will be described as an example. .
[0030]
The shift register portion includes a flip-flop circuit (FF), a NAND circuit, and an inverter circuit, and receives a clock signal (CLK), an inverted clock signal (CLKb) of the clock signal, and a start pulse (SP). As shown in FIG. 4A, the flip-flop circuit (FF) includes a clocked inverter circuit and an inverter circuit.
[0031]
When the start pulse (SP) is input, the sampling pulse is sequentially shifted in synchronization with the clock signals (CLK, CLKb).
[0032]
The latch 1 part and the latch 2 part, which are memory circuits, are composed of a basic latch circuit (LAT). A basic latch circuit is shown in FIG. The basic latch circuit (LAT) is composed of a clocked inverter circuit and an inverter circuit. R, G, B, 3-bit digital video signals (DR0, DR1, DR2, DG0, DG1, DG2, DB0, DB1, DB2) are input to the latch 1 unit, and sampling pulses from the shift register unit Latch digital video signal. The latch 2 unit simultaneously latches the digital video signals held in the latch 1 unit by a latch pulse (LP) input during the horizontal blanking period, and simultaneously transmits information to a downstream circuit. At this time, the latch 2 portion holds data for one horizontal writing period.
[0033]
4A and 4B, the connection of the clock input terminal to the P-channel transistor of each clocked inverter circuit is omitted, but in actuality, the clock input terminal to the N-channel transistor is input to the clock input terminal. The inverted signal of the control signal is input. In this embodiment, the flip-flop circuit (FF) and the basic latch circuit (LAT) have the same circuit configuration, but may have different circuit configurations.
[0034]
To the parallel / serial conversion circuit (referred to as P / S conversion circuit A in FIG. 3), the digital video stored in the latch 2 section of 3 (number of bits) × 3 (three source signal lines in RGB) A signal and selection signals (SS1 to SS3) are input. As shown in FIG. 5A, the P / S conversion circuit A is composed of a NAND circuit.
[0035]
FIG. 7 shows signal operation timings paying attention to the P / S conversion circuit A related to the first to third source signal lines (SL1 to SL3). One gate line selection period is divided into three, the selection signal (SS1) is set to Hi level in the first period, and the digital video signal for the first source signal line (SL1) is output to the D / A conversion circuit. In the second period, the selection signal (SS2) is set to the Hi level, and the digital video signal for the second source signal line (SL2) is output to the D / A conversion circuit. In the third period, the selection signal (SS3) is set to the Hi level, and the digital video signal for the third source signal line (SL3) is output to the D / A conversion circuit. This state is shown in PS0 [1] to PS2 [1] in FIG. Here, PSl [1] is the output data of the (l + 1) th bit of the P / S conversion circuit A related to the first to third source signal lines (SL1 to SL3). As described above, Dl [s, g] indicates the (l + 1) th bit digital video signal for the pixel in the sth column and the gth row. Here, DRl, DGl, DBl (l = 0-2) and Dl [s] (l = 0-2) distinguished by RGB have the following relationship.
DRl [s] = Dl [3s-2] (l = 0-2)
DGl [s] = Dl [3s-1] (l = 0-2)
DBl [s] = Dl [3s] (l = 0-2)
In addition, what added gate signal line information to notation such as DRl [s] is denoted as DRl [s, g].
[0036]
An operation similar to the above is also performed in parallel in the P / S conversion circuit A related to the other source signal lines (SL4 to SL6, SL7 to SL9,...).
[0037]
A circuit configuration example of the D / A conversion circuit is shown in FIG. FIG. 6 shows a resistor string type D / A conversion circuit. In order to obtain an output in a certain voltage range, it is necessary to supply two gradation power supply lines. In FIG. 6, these are indicated as Vref-L and Vref-H. These gradation power supply voltages are divided by resistors and a voltage value corresponding to a 3-bit digital video signal is output.
[0038]
The output of the D / A conversion circuit is connected to an appropriate source signal line via the source line selection circuit A. A circuit configuration example of the source line selection circuit A is shown in FIG. The source line selection circuit A includes three transmission gates (switches), and selection signals (SS1 to SS3) and their inverted signals are input to each gate. According to the signal operation timing of FIG. 7, one gate line selection period is divided into three. In the first period, the switch sw1 is turned on to the R first source signal line (SL1). Write the output of. In the second period, the switch sw2 is turned on to write the output of the D / A conversion circuit to the G second source signal line (SL2). In the last, third period, the switch sw3 is turned on and the output of the D / A conversion circuit is written to the B third source signal line (SL3).
[0039]
Such writing is performed in parallel to other source signal lines. The data written to each source signal line is sequentially written to each pixel by the action of the gate signal line driving circuit and the pixel TFT.
[0040]
In this embodiment, of the two gradation power supply lines Vref-L and Vref-H, Vref-L is set to V0 as the same voltage for each color of RGB, and Vref-H is set to VR, VG, and VB for RGB, respectively. FIG. 7 shows how the power supply voltage of the gradation power supply line is changed during one gate line selection period. A power supply voltage corresponding to R is applied during a period when the R source signal line is selected by the source line selection circuit, and a period during which the G source signal line is selected by the source line selection circuit corresponds to G. The power supply voltage corresponding to B is applied during a period in which the power supply voltage is applied and the source signal line of B is selected by the source line selection circuit.
[0041]
When three source signal lines are driven by one D / A conversion circuit by the above driving method, even if only one grayscale power supply line is supplied to the source signal line driving circuit, it is applied to the pixel. The voltage to be controlled can be controlled independently for RGB.
[0042]
In this embodiment, the circuit drive power supply supplied to the source signal line drive circuit is assumed to be one system, but two or more systems may be used, and a level shifter circuit may be inserted in a necessary portion. In this embodiment, the power supply voltage of the gradation power supply line Vref-L is the same as that for RGB, but may be different.
[0043]
[Example 2]
In the present embodiment, an example in which the present invention is applied to an active matrix image display device as in the first embodiment is shown. However, unlike the first embodiment, one D / A conversion circuit has six (RGB × 2) sources. An example of driving a signal line will be described. In this embodiment, the source signal line driver circuit will be mainly described. The shift register unit, the latch unit 1 and the latch unit 2 are the same as those in the first embodiment, and the description thereof will be omitted below. FIG. 8 shows a circuit configuration example downstream from the latch 2 circuit in this embodiment. Also in this embodiment, the digital video signal for each color of RGB is 3 bits.
[0044]
The parallel / serial conversion circuit (referred to as P / S conversion circuit B in FIG. 8) is stored in the latch 2 section of 3 (number of bits) × 6 (6 source signal lines for RGB × 2). A digital video signal and selection signals (SS1 to SS6) are input. As shown in FIG. 9A, the P / S conversion circuit B is composed of a NAND circuit.
[0045]
FIG. 10 shows signal operation timings paying attention to the P / S conversion circuit B related to the first to sixth source signal lines (SL1 to SL6). The six selection signals SS1, SS4, SS2, SS5, SS3, and SS6 are input in this order so as to become the Hi level in each period obtained by dividing one gate line selection period into six. In this way, the P / S conversion circuit B outputs the digital video signals corresponding to the source signal lines SL1 (R), SL4 (R), SL2 (G), SL5 (G), SL3 (B), and SL6 (B) in this order. To output to the D / A conversion circuit. This state is shown in PS0 [1] to PS2 [1] in FIG. Here, PS1 [1] is the output data of the (l + 1) th bit of the P / S conversion circuit B related to the first to sixth source signal lines (SL1 to SL6). As described above, Dl [s, g] indicates the (l + 1) th bit digital video signal for the pixel in the sth column and the gth row. Here, the following relations hold true for DR1, DG1, DB1 (l = 0 to 2) and Dl [s] (l = 0 to 2) distinguished by RGB.
DRl [s] = Dl [3s-2] (l = 0-2)
DGl [s] = Dl [3s-1] (l = 0-2)
DBl [s] = Dl [3s] (l = 0-2)
In addition, what added gate signal line information to notation such as DRl [s] is denoted as DRl [s, g].
[0046]
The same operation as described above is performed in parallel in the P / S conversion circuit B related to the other source signal lines (SL7 to SL12, SL13 to SL18,...).
[0047]
The D / A conversion circuit is the same as that of the first embodiment and is shown in FIG.
[0048]
The output of the D / A conversion circuit is connected to an appropriate source signal line via the source line selection circuit B. A circuit configuration example of the source line selection circuit B is shown in FIG. The source line selection circuit B includes six transmission gates (switches), and selection signals (SS1 to SS6) and their inverted signals are input to each gate. According to the signal operation timing of FIG. 10, one gate line selection period is divided into six, and six selection signals SS1, SS4, SS2, SS5, SS3, and SS6 become Hi level in this order in each period. As a result, the switches in the source line selection circuit B are turned on in the order of sw1, sw4, sw2, sw5, sw3, sw6, and the source signal lines SL1 (R), SL4 (R), SL2 (G), SL5 (G). SL3 (B) and SL6 (B) are connected to the D / A conversion circuit in this order, and writing to each source signal line is performed.
[0049]
Such writing is performed in parallel to other source signal lines. The data written to each source signal line is sequentially written to each pixel by the action of the gate signal line driving circuit and the pixel TFT.
[0050]
Also in this embodiment, of the two gradation power supply lines Vref-L and Vref-H, Vref-L is set to the same voltage V0 for RGB colors, and Vref-H is set to VR, VG, and VB for RGB, respectively. FIG. 10 shows how the power supply voltage of the gradation power supply line is changed during one gate line selection period. A power supply voltage corresponding to R is applied during a period when the R source signal line is selected by the source line selection circuit, and a period during which the G source signal line is selected by the source line selection circuit corresponds to G. The power supply voltage corresponding to B is applied during a period in which the power supply voltage is applied and the source signal line of B is selected by the source line selection circuit.
[0051]
As in this embodiment, within one gate line selection period, the source signal lines of the same color for RGB are continuously connected to the D / A conversion circuit to change the power supply voltage applied to the gradation power supply line. The cycle can be lengthened, leading to a reduction in circuit operation burden.
[0052]
When six source signal lines are driven by one D / A conversion circuit by the above driving method, even if only one grayscale power supply line is supplied to the source signal line driving circuit, it is applied to the pixel. The voltage to be controlled can be controlled independently for RGB.
[0053]
In this embodiment, the circuit drive power supply supplied to the source signal line drive circuit is assumed to be one system, but two or more systems may be used, and a level shifter circuit may be inserted in a necessary portion. In this embodiment, the power supply voltage of the gradation power supply line Vref-L is the same as that for RGB, but may be different. Further, the order of selecting the source signal lines of the source line selection circuit is not limited to this embodiment.
[0054]
[Example 3]
In this embodiment, as an example of a manufacturing method in the case where the first and second embodiments are applied to an active matrix liquid crystal display device, a pixel TFT which is a switching element of a pixel portion and a driving circuit ( A method for manufacturing a TFT of a source signal line driver circuit, a gate signal line driver circuit, or the like over the same substrate will be described in detail according to steps. However, in order to simplify the description, a CMOS circuit, which is a basic configuration circuit, is illustrated as the drive circuit unit, and an n-channel TFT is illustrated as the pixel TFT unit.
[0055]
In FIG. 11, a non-alkali glass substrate typified by a Corning 1737 glass substrate is used as the substrate 401, for example. A base film 402 is formed on the surface of the substrate 401 on which the TFT is formed by a plasma CVD method or a sputtering method. As the base film 402, a silicon nitride film is formed to a thickness of 25 to 100 nm, here 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 nm, here 150 nm. Alternatively, the base film 402 may be formed using only a silicon nitride film or a silicon nitride oxide film.
[0056]
Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 402 by a plasma CVD method. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atom% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0057]
Here, both the base film and the amorphous silicon film are produced by the plasma CVD method. At this time, the base film and the amorphous silicon film may be continuously formed in a vacuum. After the formation of the base film, once the process is not exposed to the air atmosphere, surface contamination can be prevented, and variation in characteristics of the manufactured TFT can be reduced.
[0058]
A known laser crystallization technique or thermal crystallization technique may be used for the step of crystallizing the amorphous silicon film. In this embodiment, a pulsed oscillation type KrF excimer laser beam is condensed into a linear shape and irradiated to an amorphous silicon film to form a crystalline silicon film.
[0059]
In this embodiment, the crystalline silicon film to be the semiconductor layer is formed from an amorphous silicon film. However, a microcrystalline silicon film may be used instead of the amorphous silicon film, or a crystalline silicon film may be used directly. May be formed.
[0060]
The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 403, 404, and 405.
[0061]
Next, a gate insulating film 406 containing silicon oxide or silicon nitride as a main component is formed so as to cover the island-shaped semiconductor layers 403, 404, and 405. The gate insulating film 406 is made of N by plasma CVD. ₂ O and SiH _Four A silicon oxynitride film made from a raw material may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. Here, it is formed to a thickness of 100 nm.
[0062]
Then, a first conductive film 407 serving as a first gate electrode and a second conductive film 408 serving as a second gate electrode are formed on the surface of the gate insulating film 406. The first conductive film 407 may be formed of one kind of element selected from Si and Ge, or a semiconductor film containing these elements as a main component. The thickness of the first conductive film 407 needs to be 5 to 50 nm, preferably 10 to 30 nm. Here, the Si film is formed with a thickness of 20 nm.
[0063]
An impurity element imparting n-type or p-type conductivity may be added to the semiconductor film used as the first conductive film 407. The semiconductor film may be formed by a known method. For example, disilane (Si ₂ H ₆ ) 250 SCCM and helium (He) 300 SCCM. At the same time, Si ₂ H ₆ Against PH _Three The n-type semiconductor film may be formed by mixing 0.1 to 2%.
[0064]
The second conductive film 408 serving as the second gate electrode may be formed using an element selected from Ti, Ta, W, and Mo or a compound containing these elements as a main component. This is considered in order to lower the electrical resistance of the gate electrode, and for example, a Mo—W compound may be used. Here, Ta was used and was formed by sputtering to a thickness of 200 to 1000 nm, typically 400 nm. (Fig. 11 (A))
[0065]
Next, a resist mask is formed using a known patterning technique, and the second conductive film 408 is etched to form a second gate electrode. Since the second conductive film 408 is formed of a Ta film, etching is performed by a dry etching method. As conditions for dry etching, Cl ₂ 80 SCCM is introduced and 500 W high frequency power is applied at 100 mTorr. Then, as shown in FIG. 11B, second gate electrodes 409, 410, 412, and 413 and wirings 411 and 414 are formed. The length of the second gate electrode in the channel length direction is 3 μm in the second gate electrodes 409 and 410 forming the CMOS circuit, and the pixel TFT has a multi-gate structure. The length of each of the electrodes 412 and 413 was 2 μm.
[0066]
The second conductive film 408 can also be removed by a wet etching method. For example, in the case of Ta, it can be easily removed with a hydrofluoric acid-based etching solution.
[0067]
In addition, a storage capacitor is provided on the drain side of the n-channel TFT constituting the pixel TFT. At this time, a wiring electrode 414 having a storage capacitor is formed using the same material as the second conductive film.
[0068]
Next, a step of adding a first impurity element imparting n-type is performed. This step is a step for forming the second impurity region. Here, phosphine (PH _Three ) Is used. In this step, in order to add phosphorus to the underlying semiconductor layers 403, 404, and 405 through the gate insulating film 406 and the first conductive film 407, the acceleration voltage is set as high as 80 keV. The concentration of phosphorus added to the semiconductor layers 403, 404, and 405 is 1 × 10. ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three And Then, regions 415, 416, 417, 418, 419, 420, 421, and 422 in which phosphorus is added to the semiconductor layer are formed. (Fig. 11 (B))
[0069]
At this time, phosphorus is also added to a region where the first conductive film 407 does not overlap with the second gate electrodes 409, 410, 411, 412, 413, and 414. The phosphorus concentration in this region is not particularly defined, but an effect of reducing the resistivity of the first conductive film can be obtained.
[0070]
Next, a step of covering part of the region where the n-channel TFT is formed with resist masks 423 and 424 and removing part of the first conductive film 407 is performed by a dry etching method. The first conductive film 407 is Si, and the dry etching condition is CF. _Four 50 SCCM, O ₂ 45 SCCM is introduced and 200 W high frequency power is applied at 50 mTorr. As a result, 425, 426, 427, and 428 which are part of the first conductive film covered with the resist mask or the gate electrode remain.
[0071]
Then, a step of adding a third impurity element imparting p-type to a region where the p-channel TFT is formed is performed. Here, diborane (B ₂ H ₆ ) Using an ion doping method. Again, the acceleration voltage is 80 keV and 2 × 10 ²⁰ atoms / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 11C, third impurity regions 429 and 430 to which boron is added at a high concentration are formed. (Figure 11 (C))
[0072]
Further, the resist masks 423 and 424 are completely removed, and resist masks 431, 432, 433, 434, 435, and 436 are formed again. Then, using the resist masks 431, 434, 435, and 436, the first conductive film portions 425 and 428 are etched to form new first conductive film portions 437, 438, 439, and 440, respectively. (Fig. 12 (A))
[0073]
The resist mask 431 is formed with a length of 9 μm, and the resist masks 434 and 435 are formed with a length of 7 μm. Accordingly, in the semiconductor layer to which phosphorus is added in the first impurity addition step for imparting n-type, the lower regions covered with the resist masks 431, 434, and 435 serve as the second impurity regions. It will be confirmed after the process.
[0074]
Next, a step of adding a second impurity element imparting n-type is performed. Here, phosphine (PH _Three ) Using an ion doping method. Also in this step, in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 406, the acceleration voltage is set as high as 80 keV. Then, first impurity regions 441, 442, 443, 444, and 445 to which phosphorus is added are formed. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Is preferred, here 1 × 10 ²⁰ atoms / cm ^Three And (Fig. 12 (A))
[0075]
Further, the resist masks 431, 432, 433, 434, 435, 436 are removed, and new resist masks 446, 447, 448, 449, 450, 451 are formed. In this process, the length of the resist masks 446, 449, and 450 formed in the n-channel TFT in the channel length direction is important in determining the TFT structure. The resist masks 446, 449, and 450 are provided for the purpose of removing part of the first conductive films 437, 438, and 439, and the second impurity region overlaps with the gate electrode depending on the length of the resist mask. Areas and areas that do not overlap can be freely determined within a certain range. (Fig. 12 (B))
[0076]
Then, first gate electrodes 452, 453, and 454 are formed by etching using the resist masks 446, 449, and 450 as shown in FIG. Here, the length of the first gate electrode 452 in the channel length direction is 6 μm, and the length of the first gate electrodes 453 and 454 in the channel length direction is 4 μm.
[0077]
In the pixel portion, an electrode 455 of a storage capacitor portion is formed.
[0078]
When the steps up to FIG. 12C are completed, a step of forming a silicon nitride film 456 and a first interlayer insulating film 457 is performed. First, a silicon nitride film 456 is formed to a thickness of 50 nm. The silicon nitride film 456 is formed by a plasma CVD method, and SiH _Four 5SCCM, NH _Three 40 SCCM, N ₂ 100 SCCM is introduced and high frequency power of 0.7 Torr and 300 W is applied. Subsequently, a silicon oxide film is employed as the first interlayer insulating film 457, and TEOS is changed to 500 SCCM, O ₂ 50 SCCM is introduced, high-frequency power of 1 Torr and 200 W is applied, and a film having a thickness of 950 nm is formed.
[0079]
Next, a heat treatment step is performed. The heat treatment step needs to be performed in order to activate the impurity element imparting n-type or p-type added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. Here, the activation process is performed by thermal annealing. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., here 450 ° C. for 2 hours.
[0080]
Thereafter, the first interlayer insulating film 457 and the silicon nitride film 456 are etched to form contact holes that reach the source and drain regions of the respective TFTs by patterning. Then, source electrodes 458, 459, and 460 and drain electrodes 461 and 462 are formed. Although not shown, in this embodiment, this electrode is used as an electrode having a three-layer structure in which a Ti film is 100 nm, an Al film 300 nm containing Ti, and a Ti film 150 nm are continuously formed by sputtering.
[0081]
Then, a passivation film 463 is formed so as to cover the source electrodes 458, 459 and 460, the drain electrodes 461 and 462, and the first interlayer insulating film 457. The passivation film 463 is a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 464 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0082]
Through the above steps, a channel formation region 465, first impurity regions 468 and 469, and second impurity regions 466 and 467 are formed in the n-channel TFT of the CMOS circuit. Here, the second impurity region has a length of 1.5 μm in regions (GOLD regions) 466 a and 467 a overlapping with the gate electrode, and a length of 1.5 μm in regions (LDD regions) 466 b and 467 b not overlapping with the gate electrode. Each is formed. The first impurity region 468 serves as a source region, and the first impurity region 469 serves as a drain region.
[0083]
In the p-channel TFT, similarly, a gate electrode having a clad structure is formed, and a channel formation region 470 and third impurity regions 471 and 472 are formed. The third impurity region 471 becomes a source region, and the third impurity region 472 becomes a drain region.
[0084]
An n-channel TFT which is a pixel TFT is a multi-gate, and channel formation regions 473 and 478, first impurity regions 476, 477 and 481, and second impurity regions 474, 475, 479 and 480 are formed. . Here, in the second impurity region, regions 474b, 475b, 479b, and 480b that do not overlap with the regions 474a, 475a, 479a, and 480a which overlap with the gate electrode are formed.
[0085]
Thus, as shown in FIG. 13, an active matrix substrate in which a CMOS circuit and pixel TFTs are formed on a substrate 401 is manufactured. In addition, a storage capacitor portion is simultaneously formed on the drain side of the n-channel TFT which is a pixel TFT.
[0086]
[Example 4]
In this example, an example in which part of the first conductive film is removed by another method after obtaining the state shown in FIG. 12A in the same process as Example 3 will be described with reference to FIG. .
[0087]
First, using the resist masks 431, 432, 433, 434, 435, and 436 formed in FIG. 12A as they are, a part of the first conductive films 437, 438, 439, and 440 in FIG. Is removed by etching, and the first conductive film is shaped as shown by 482, 483, 484, and 485 in FIG.
[0088]
When the first gate electrode is a silicon film, the etching process can be performed by introducing 40 SCCM of SF6 and 10 SCCM of O2 and applying high frequency power of 100 mTorr and 200 W by dry etching. .
[0089]
Under this dry etching condition, the selectivity with respect to the underlying gate insulating film is high, and the gate insulating film 406 is hardly etched.
[0090]
Here, the resist mask 431 is formed with a length of 9 μm in the TFT channel length direction, and the resist masks 434 and 435 are formed with a length of 7 μm. Then, the first conductive film is removed by 1.5 μm by dry etching to form first gate electrodes 482, 483, 484, and 485.
[0091]
If the resist masks 431, 432, 433, 434, 435, and 436 are removed, the portion relating to the TFT becomes the state shown in FIG. The subsequent steps may be performed in accordance with the third embodiment. As shown in FIG. 13, the silicon nitride film 456, the first interlayer insulating film 457, the source electrodes 458, 459 and 460, the drain electrodes 461 and 462, the passivation film 463, the first Two interlayer insulating films 464 are formed to form the active matrix substrate shown in FIG.
[0092]
[Example 5]
In this example, a crystalline semiconductor film used as a semiconductor layer in Example 3 is formed by a thermal crystallization method using a catalytic element. In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0093]
Here, FIG. 15 shows an example in which the technique disclosed in Japanese Patent Laid-Open No. 7-130652 is applied to the present invention. First, a silicon oxide film 1202 is provided over a substrate 1201, and an amorphous silicon film 1203 is formed thereon. Furthermore, a nickel-containing layer 1204 is formed by applying a nickel acetate salt solution containing 10 ppm of nickel in terms of weight. (Fig. 15 (A))
[0094]
Next, after a dehydrogenation step at 500 ° C. for 1 hour, heat treatment is performed at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours, thereby forming a crystalline silicon film 1205. The crystalline silicon film 1205 obtained in this way has a very excellent crystalline quality. (Fig. 15 (B))
[0095]
Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. A case where this technique is applied to the present invention will be described with reference to FIG.
[0096]
First, a silicon oxide film 1302 is provided over a glass substrate 1301, and an amorphous silicon film 1303 and a silicon oxide film 1304 are successively formed thereon. At this time, the thickness of the silicon oxide film 1304 is 150 nm.
[0097]
Next, the silicon oxide film 1304 is patterned to selectively form the opening 1305, and then a nickel acetate salt solution containing 10 ppm of nickel in terms of weight is applied. As a result, a nickel-containing layer 1306 is formed, and the nickel-containing layer 1306 is in contact with the amorphous silicon film 1303 only at the bottom of the opening 1305. (FIG. 16 (A))
[0098]
Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours to form a crystalline silicon film 1307. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally therefrom. The crystalline silicon film 1307 formed in this way is formed by a collection of rod-like or needle-like crystals, and each crystal grows with a specific direction as viewed macroscopically, so that the crystallinity is uniform. There is an advantage. (Fig. 16 (B))
[0099]
The catalyst elements that can be used in the above two techniques are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt ( Elements such as Co), platinum (Pt), copper (Cu), and gold (Au) may be used.
[0100]
A crystalline TFT semiconductor layer can be formed by forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described technique and performing patterning. A TFT manufactured from a crystalline semiconductor film by using the technique of this embodiment can obtain excellent characteristics, and therefore, high reliability is required. However, by adopting the TFT structure of the present invention, it has become possible to produce a TFT that makes the most of the technique of this embodiment.
[0101]
[Example 6]
In this example, as a method of forming the semiconductor layer used in Example 3, after forming a crystalline semiconductor film using the catalytic element using an amorphous semiconductor film as an initial film, the catalytic element is converted into crystalline. The example which performed the process removed from a semiconductor film is shown. In this embodiment, the technique described in Japanese Patent Laid-Open No. 10-135468 or Japanese Patent Laid-Open No. 10-135469 is used as the method.
[0102]
The technique described in this publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film by a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10. ¹⁷ atms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atms / cm ^Three It can be reduced to.
[0103]
The configuration of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by Corning's 1737 substrate is used. FIG. 17A shows a state in which a base film 1402 and a crystalline silicon film 1403 are formed by using the crystallization technique shown in Embodiment 5. A silicon oxide film 1404 for a mask is formed to a thickness of 150 nm on the surface of the crystalline silicon film 1403, and an opening is provided by patterning to form a region where the crystalline silicon film is exposed. Then, a step of adding phosphorus is performed to provide a region 1405 in which phosphorus is added to the crystalline silicon film.
[0104]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, a region 1405 in which phosphorus is added to the crystalline silicon film serves as a gettering site, The catalytic element remaining in the porous silicon film 1403 can be segregated in the region 1405 to which phosphorus is added. (Fig. 17 (B))
[0105]
Then, the silicon oxide film 1404 for the mask and the region 1405 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is 1 × 10. ¹⁷ atms / cm ^Three A crystalline silicon film reduced to the following can be obtained. This crystalline silicon film can be used as it is as the semiconductor layer of the TFT of the present invention shown in Example 3.
[0106]
[Example 7]
This embodiment shows another embodiment in which a semiconductor layer and a gate insulating film are formed in the process of manufacturing the TFT of the present invention shown in Embodiment 3. The configuration of this embodiment is shown in FIG.
[0107]
Here, a substrate having heat resistance of at least about 700 to 1100 ° C. is necessary, and a quartz substrate 1501 is used. Then, a crystalline semiconductor is formed by using the techniques shown in Embodiments 5 and 6, and semiconductor layers 1502 and 1503 are formed by patterning into an island shape in order to make this a semiconductor layer of a TFT. Then, a film containing silicon oxide as a main component is formed as the gate insulating film 1504 so as to cover the semiconductor layers 1502 and 1503. In this embodiment, a silicon nitride oxide film with a thickness of 70 nm is formed by plasma CVD. (FIG. 18 (A))
[0108]
Then, heat treatment is performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this example, the temperature was 950 ° C. for 30 minutes. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected between 10 minutes and 8 hours. (Fig. 18B)
[0109]
As a result, under the conditions of this embodiment, a thermal oxide film is formed at the interface between the semiconductor layers 1502 and 1503 and the gate insulating film 1504, and a gate insulating film 1507 combined with the formed gate insulating film 1504 is formed. . In addition, in the process of oxidation in a halogen atmosphere, a metal impurity element, in particular, an impurity contained in the gate insulating film 1504 and the semiconductor layers 1502 and 1503 can form a compound with halogen and can be removed into the gas phase.
[0110]
The gate insulating film 1507 manufactured through the above steps has high withstand voltage, and the interface between the semiconductor layers 1505 and 1506 and the gate insulating film 1507 is very good. In order to obtain the structure of the TFT of the present invention, the subsequent steps may be performed in accordance with Embodiment 3.
[0111]
[Example 8]
In this example, a crystalline semiconductor film is formed by the method shown in Example 5, and in the method of manufacturing an active matrix substrate in the step shown in Example 3, the catalyst element used in the crystallization step is removed by gettering. An example is shown. First, in Example 3, the semiconductor layers 403, 404, and 405 shown in FIG. 11A were crystalline silicon films manufactured using a catalytic element. At this time, since the catalyst element used in the crystallization process remains in the semiconductor layer, it is desirable to perform a gettering process.
[0112]
Here, the steps up to the step shown in FIG. 11C were performed as they were, and then the resist masks 423 and 424 were removed.
[0113]
Then, as shown in FIG. 19, new resist masks 1601, 1602, 1603, 1604, 1605 and 1606 are formed. Next, a second impurity addition step for imparting n-type is performed. As a result, regions 1607, 1608, 1609, 1610, 1611, 1612, and 1613 in which phosphorus is added to the semiconductor layer are formed.
[0114]
Here, boron, which is an impurity element imparting p-type conductivity, is already added to the regions 1609 and 1610 to which phosphorus is added. At this time, the phosphorus concentration is 1 × 10 6. ¹⁹ ~ 1x10 ²⁰ atoms / cm ^Three Since it is added at a concentration of about 1/2 with respect to boron, it does not affect the characteristics of the p-channel TFT.
[0115]
In this state, a heat treatment process is performed in a nitrogen atmosphere at 400 to 800 ° C. for 1 to 24 hours, for example, 600 ° C. for 12 hours. By this step, the added impurity element imparting n-type and p-type can be activated. Further, the region to which phosphorus is added becomes a gettering site, and the remaining catalytic element can be segregated after the crystallization step. As a result, the catalyst element can be removed from the channel formation region. (Fig. 19B)
[0116]
When the step of FIG. 19B is completed, the subsequent steps are performed in accordance with the steps of Embodiment 3, and the state of FIG. 13 is formed, whereby an active matrix substrate can be manufactured.
[0117]
[Example 9]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described.
[0118]
A light shielding film 1101 and a third interlayer insulating film 1102 are formed on the active matrix substrate in the state of FIG. 13 as shown in FIG. As the light-shielding film 1101, an organic resin film containing a pigment or a metal film such as Ti or Cr is preferably used. The third interlayer insulating film 1102 was formed of an organic resin film such as polyimide. Then, a contact hole reaching the drain electrode 462 is formed in the third interlayer insulating film 1102, the second interlayer insulating film 464, and the passivation film 463, and the pixel electrode 1103 is formed. The pixel electrode 1103 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 1103 is formed.
[0119]
Next, as shown in FIG. 20B, an alignment film 1104 is formed so as to cover the third interlayer insulating film 1102 and the pixel electrode 1103. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 1106 and an alignment film 1107 are formed on the opposite substrate 1105. After the alignment film is formed, the alignment film is subjected to a rubbing process to perform parallel alignment with a certain pretilt angle of liquid crystal molecules.
[0120]
Through the above steps, the pixel TFT, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process. Thereafter, a liquid crystal material 1108 is injected between both substrates and completely sealed with a sealant (not shown). In this way, the active matrix liquid crystal display device shown in FIG. 20B is completed.
[0121]
Note that the TFT formed by the above process has a top gate structure, but the present invention can be applied to a TFT having a bottom gate structure and other structures.
[0122]
Further, the present invention can also be applied to an EL display device that is a self-luminous display device using an electroluminescence (EL) material instead of a liquid crystal material. Note that in this specification, an element formed of an anode, an organic compound layer, and a cathode is referred to as a light emitting element. The light-emitting element includes a layer containing an organic compound (hereinafter referred to as an organic compound layer) from which electroluminescence (luminescence generated by applying an electric field) is obtained, an anode, and a cathode. Luminescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. It is also applicable to a light emitting device using
[0123]
In the present specification, all layers provided between the anode and the cathode are defined as organic compound layers. Specifically, the organic compound layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the light-emitting element has a structure in which an anode / light-emitting layer / cathode is laminated in order, and in addition to this structure, an anode / hole injection layer / light-emitting layer / cathode and an anode / hole injection layer. In some cases, the light emitting layer / the electron transporting layer / the cathode are laminated in this order.
[0124]
[Example 10]
In this embodiment, a manufacturing example in the case where the first and second embodiments are applied to an EL display device will be described.
[0125]
FIG. 21A is a top view of an EL display device to which the present invention is applied, and FIG. 21B is a cross-sectional view of the EL display device taken along line AA ′ shown in FIG. In FIG. 21A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source signal line driver circuit, and 4013 denotes a gate signal line driver circuit. Each driver circuit reaches an FPC 4017 through wirings 4014 to 4016 and is externally connected. Connected to the device.
[0126]
At this time, a cover material 4600, a sealing material (also referred to as a housing material) 4100, and a sealing material (second sealing material) 4101 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0127]
Further, as shown in FIG. 21B, a driver circuit TFT (here, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined) is illustrated over a substrate 4010 and a base film 4021. ) 4022 and a pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here). These TFTs may have a known structure (top gate structure or bottom gate structure).
[0128]
When a driver circuit TFT 4022 and a pixel portion TFT 4023 are completed using a known manufacturing method, a transparent conductive layer electrically connected to the drain of the pixel portion TFT 4023 on an interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 made of a film is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0129]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0130]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used.
Needless to say, an EL display device emitting monochromatic light can also be used.
[0131]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0132]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0133]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0134]
A passivation film 4603, a filler 4604, and a cover material 4600 are formed so as to cover the surface of the EL element thus formed.
[0135]
Further, a sealing material 4100 is provided inside the cover material 4600 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 4101 is formed outside the sealing material 4100.
[0136]
At this time, the filler 4604 also functions as an adhesive for bonding the cover material 4600. As the filler 4604, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4604 because the moisture absorption effect can be maintained.
[0137]
Further, a spacer may be contained in the filler 4604. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0138]
In the case where a spacer is provided, the passivation film 4603 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0139]
Further, as the cover material 4600, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that in the case of using PVB or EVA as the filler 4604, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0140]
However, the cover material 4600 needs to have a light-transmitting property depending on a light emission direction (light emission direction) from the EL element.
[0141]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 4100 and the sealing material 4101 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 4100 and the sealing material 4101 in the same manner.
[0142]
In this embodiment, the cover material 4600 is adhered after the filler 4604 is provided, and the sealing material 4100 is attached so as to cover the side surface (exposed surface) of the filler 4604. However, the cover material 4600 and the sealing material 4100 are attached. The filler 4604 may be provided after the attachment. In this case, a filler inlet that leads to a gap formed by the substrate 4010, the cover material 4600, and the sealing material 4100 is provided. The voids are in a vacuum state (10 ^-2 The Torr is equal to or less than Torr), and the inlet is immersed in a water tank containing a filler, and then the pressure outside the gap is made higher than the pressure inside the gap to fill the filler into the gap.
[0143]
[Example 11]
In this example, an example in which an EL display device having a different form from that of Example 10 is manufactured using the present invention will be described with reference to FIGS. The same reference numerals as those in FIGS. 21A and 21B indicate the same parts, and the description thereof is omitted.
[0144]
FIG. 22A is a top view of the EL display device of this example, and FIG. 22B is a cross-sectional view taken along line AA ′ of FIG.
[0145]
According to the tenth embodiment, a passivation film 4603 is formed to cover the surface of the EL element.
[0146]
Further, a filler 4604 is provided so as to cover the EL element. The filler 4604 also functions as an adhesive for bonding the cover material 4600. As the filler 4604, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4604 because the moisture absorption effect can be maintained.
[0147]
Further, a spacer may be contained in the filler 4604. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0148]
In the case where a spacer is provided, the passivation film 4603 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0149]
Further, as the cover material 4600, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that in the case of using PVB or EVA as the filler 4604, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0150]
However, the cover material 4600 needs to have a light-transmitting property depending on a light emission direction (light emission direction) from the EL element.
[0151]
Next, after the cover material 4600 is bonded using the filler 4604, the frame material 4601 is attached so as to cover the side surface (exposed surface) of the filler 4604. The frame material 4601 is bonded by a sealing material (functioning as an adhesive) 4602. At this time, a photocurable resin is preferably used as the sealing material 4602, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 4602 is preferably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 4602.
[0152]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 4602 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 4602 in the same manner.
[0153]
In this embodiment, the cover material 4600 is adhered after the filler 4604 is provided, and the frame material 4601 is attached so as to cover the side surface (exposed surface) of the filler 4604. However, the cover material 4600 and the frame material 4601 are attached. The filler 4604 may be provided after the attachment. In this case, an injection port for a filler that leads to a gap formed by the substrate 4010, the cover material 4600, and the frame material 4601 is provided. The voids are in a vacuum state (10 ^-2 The Torr is equal to or less than Torr), and the inlet is immersed in a water tank containing a filler, and then the pressure outside the gap is made higher than the pressure inside the gap to fill the filler into the gap.
[0154]
[Example 12]
Here, FIG. 23 shows a more detailed cross-sectional structure of the pixel portion in the EL display device, FIG. 24A shows a top surface structure, and FIG. 24B shows a circuit diagram. 23, 24 (A), and 24 (B) use common reference numerals and may be referred to each other.
[0155]
In FIG. 23, an n-channel TFT formed by a known method is used as a switching TFT 4502 provided over a substrate 4501. In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, a p-channel TFT formed by a known method may be used.
[0156]
Further, an n-channel TFT formed by a known method is used as the current control TFT 4503. The switching TFT 4502 has 34 source lines (source signal lines). The drain wiring 35 of the switching TFT 4502 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate wiring (gate signal line) that electrically connects the gate electrodes 39a and 39b of the switching TFT 4502.
[0157]
Since the current control TFT 4503 is an element that controls the amount of current flowing through the EL element, a large amount of current flows and is also an element that has a high risk of deterioration due to heat or hot carriers. Therefore, a structure in which an LDD region is provided on the drain side of the current control TFT 4503 so as to overlap the gate electrode through a gate insulating film is extremely effective.
[0158]
In this embodiment, the current control TFT 4503 is shown as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0159]
Further, as shown in FIG. 24A, the wiring 36 that becomes the gate electrode 37 of the current control TFT 4503 is electrically connected to the drain wiring 40 of the current control TFT 4503 through an insulating film in a region indicated by 4504. Overlaps with the power supply line 4506. At this time, a capacitor is formed in a region indicated by 4504 and functions as a holding capacitor for holding a voltage applied to the gate electrode 37 of the current control TFT 4503. The storage capacitor 4504 is formed between a semiconductor film 4507 electrically connected to the power supply line 4506, an insulating film (not shown) in the same layer as the gate insulating film, and the wiring 36. A capacitor formed by the wiring 36, the same layer (not shown) as the first interlayer insulating film, and the power supply line 4506 can also be used as the storage capacitor. Note that the drain of the current control TFT is connected to a power supply line (power supply line) 4506, and a constant voltage is always applied.
[0160]
A first passivation film 41 is provided on the switching TFT 4502 and the current control TFT 4503, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0161]
A pixel electrode 43 (EL element cathode) made of a highly reflective conductive film is electrically connected to the drain of the current control TFT 4503. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.
[0162]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). In FIG. 24A, some banks are omitted in order to clarify the position of the storage capacitor 4504, and only the banks 44a and 44b are shown, but the power supply line 4506 and the source wiring (source signal line) are shown. ) 34 is provided between the power supply line 4506 and the source wiring (source signal line) 34 so as to partially cover. Although only two pixels are shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0163]
There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.
[0164]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0165]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0166]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0167]
In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0168]
When the anode 47 is formed, the EL element 4505 is completed. Note that the EL element 4505 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 24A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0169]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0170]
As described above, the EL display device of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. Have. Therefore, an EL display device having high reliability and capable of displaying a good image can be obtained.
[0171]
[Example 13]
In this embodiment, a structure in which the structure of the EL element 4505 is inverted in the pixel portion described in Embodiment 12 will be described. FIG. 25 is used for the description. Note that the only difference from the structure of FIG. 23 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0172]
In FIG. 25, a p-channel TFT formed by a known method is used as the current control TFT 4503.
[0173]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0174]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 4701 is formed.
[0175]
In the case of the present embodiment, the light generated in the light emitting layer 52 is emitted toward the substrate on which the TFT is formed, as indicated by the arrows.
[0176]
[Example 14]
In this embodiment, FIGS. 26A to 26C show an example in which the pixel has a structure different from the circuit diagram shown in FIG. In this embodiment, 4801 is a source wiring (source signal line) of the switching TFT 4802, 4803 is a gate wiring (gate signal line) of the switching TFT 4802, 4804 is a current control TFT, 4805 is a storage capacitor, 4806 and 4808. Is a power supply line and 4807 is an EL element.
[0177]
FIG. 26A illustrates an example in which the power supply line 4806 is shared between two pixels. That is, there is a feature in that the two pixels are formed so as to be symmetrical with respect to the power supply line 4806. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0178]
FIG. 26B illustrates an example in which the power supply line 4808 is provided in parallel with the gate wiring (gate signal line) 4803. Note that in FIG. 26B, the power supply line 4808 and the gate wiring (gate signal line) 4803 are provided so as not to overlap with each other; It can also provide so that it may overlap through a film | membrane. In this case, since the exclusive area can be shared by the power supply line 4808 and the gate wiring (gate signal line) 4803, the pixel portion can be further refined.
[0179]
In FIG. 26C, similarly to the structure of FIG. 26B, a power supply line 4808 is provided in parallel with the gate wiring (gate signal line) 4803, and two pixels are connected to the power supply line 4808. It is characterized in that it is formed so as to be symmetrical. It is also effective to provide the power supply line 4808 so as to overlap with any one of the gate wirings (gate signal lines) 4803. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0180]
[Example 15]
In FIGS. 24A and 24B shown in Embodiment 12, the storage capacitor 4504 is provided to hold the voltage applied to the gate of the current control TFT 4503. However, the storage capacitor 4504 may be omitted. Is possible. In the case of Example 12, an LDD region is provided on the drain side of the current control TFT 4503 so as to overlap the gate electrode with a gate insulating film interposed therebetween. In this overlapped region, a parasitic capacitance generally called a gate capacitance is formed, but this embodiment is characterized in that this parasitic capacitance is positively used in place of the holding capacitor 4504.
[0181]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the LDD region overlap, the capacitance of the parasitic capacitance is determined by the length of the LDD region included in the overlapping region.
[0182]
Similarly, in the structure of FIGS. 26A, 26B, and 26C shown in Embodiment 14, the storage capacitor 4805 can be omitted.
[0183]
[Example 16]
In this embodiment, an electronic device incorporating an active matrix liquid crystal display device or an EL display device using the driving method of the present invention will be described. Examples of these electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers, televisions, and the like. Examples of these are shown in FIGS. However, FIGS. 27, 28, and 29 are applied to the active matrix liquid crystal display device, and FIGS. 27 and 28 are applied to the EL display device.
[0184]
FIG. 27A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display portion 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to the display portion 9004.
[0185]
FIG. 27B illustrates a video camera which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the display portion 9102.
[0186]
FIG. 27C illustrates a mobile computer or a portable information terminal which is a kind of personal computer, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display portion 9205. The present invention can be applied to the display portion 9205.
[0187]
FIG. 27D illustrates a head mounted display (goggles type display) which includes a main body 9301, a display portion 9302, and an arm portion 9303. The present invention can be applied to the display portion 9302.
[0188]
FIG. 27E illustrates a television set including a main body 9401, speakers 9402, a display portion 9403, a receiving device 9404, an amplifying device 9405, and the like. The present invention can be applied to the display portion 9403.
[0189]
FIG. 27F illustrates a portable book, which includes a main body 9501, a display portion 9502, a storage medium 9504, an operation switch 9505, and an antenna 9506, and is stored on a mini disc (MD) or DVD (Digital Versatile Disc). Data and data received by the antenna are displayed. The present invention can be applied to the display portion 9502.
[0190]
FIG. 28A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display portion 9603, and a keyboard 9604. The present invention can be applied to the display portion 9603.
[0191]
FIG. 28B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display portion 9702, a speaker portion 9703, a recording medium 9704, and an operation switch 9705. This apparatus uses a DVD, CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 9702.
[0192]
FIG. 28C illustrates a digital camera which includes a main body 9801, a display portion 9802, an eyepiece portion 9803, an operation switch 9804, and an image receiving portion (not shown). The present invention can be applied to the display portion 9802.
[0193]
FIG. 28D illustrates a one-eye head-mounted display which includes a display portion 9901 and a head mount portion 9902. The present invention can be applied to the display portion 9901. FIG.
[0194]
FIG. 29A illustrates a front type projector which includes a projection device 3601 and a screen 3602.
[0195]
FIG. 29B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704.
[0196]
Note that FIG. 29C illustrates an example of the structure of the projection devices 3601 and 3702 in FIGS. 29A and 29B. The projection devices 3601 and 3702 include a light source optical system 3801, a mirror 3802, a dichroic mirror 3803, a microlens array 3804, a liquid crystal display unit 3805, a Fresnel lens 3806, and a projection optical system 3807. The projection optical system 3807 is composed of an optical system including a projection lens. This embodiment is a single-plate projection device. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG. Good. The present invention can be applied to the liquid crystal display portion 3805.
[0197]
FIG. 29D shows an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 29D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0198]
As described above, the applicable range of the present invention is extremely wide and can be applied to electronic devices in various fields using an image display device.
[0199]
【Effect of the invention】
According to the driving method of the present invention, in a method of driving a plurality of source signal lines with a single D / A conversion circuit, it is applied to the liquid crystal without causing an increase in the number of external input pins and an increase in the area occupied by the driving circuit. The voltage can be controlled independently of RGB.
[0200]
In addition, this makes it possible to prevent a decrease in contrast, and to display a high-quality image with excellent color expression.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a drive circuit according to an embodiment of the present invention.
FIG. 2 is an example of operation timing according to the embodiment of FIG. 1;
FIG. 3 is a source signal line drive circuit diagram according to the first exemplary embodiment.
4 is a circuit diagram of a flip-flop circuit (FF) and a basic latch circuit (LAT) in Embodiment 1. FIG.
5 is a circuit diagram of a P / S conversion circuit and a source line selection circuit in Embodiment 1. FIG.
6 is a circuit diagram of a D / A conversion circuit in Embodiment 1. FIG.
FIG. 7 is a diagram illustrating signal operation timing in the first embodiment.
8 is a source signal line driver circuit diagram according to the second embodiment. FIG.
9 is a circuit diagram of a P / S conversion circuit and a source line selection circuit in Embodiment 2. FIG.
FIG. 10 is a diagram illustrating signal operation timing in the second embodiment.
FIG. 11 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 12 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 13 is a cross-sectional view of an active matrix substrate.
FIG. 14 is a cross-sectional view showing a manufacturing process of a TFT.
FIGS. 15A and 15B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
FIG. 16 is a diagram illustrating a manufacturing process of a crystalline silicon film.
FIG. 17 is a diagram illustrating a manufacturing process of a crystalline silicon film.
FIG. 18 is a diagram showing a manufacturing process of a crystalline silicon film.
FIG. 19 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 20 is a cross-sectional view showing a manufacturing process of a liquid crystal display device.
FIG. 21 illustrates an example of manufacturing an EL display device.
FIG. 22 is a diagram showing an example of manufacturing an EL display device.
FIG. 23 illustrates an example of manufacturing an EL display device.
FIG. 24 illustrates an example of manufacturing an EL display device.
FIG. 25 is a diagram illustrating an example of manufacturing an EL display device.
FIG. 26 illustrates an example of manufacturing an EL display device.
FIG. 27 is a diagram illustrating an example of an image display device.
FIG. 28 is a diagram illustrating an example of an image display device.
FIG. 29 is a diagram showing a configuration of a projection type liquid crystal display device.
FIG. 30 is a schematic view of an active matrix liquid crystal display device.
FIG. 31 is a schematic diagram of a conventional digital source signal line driving circuit.
FIG. 32 is a schematic diagram of a source signal line driving circuit that drives four source signal lines with one D / A conversion circuit.
FIG. 33 is an example of luminance ratio-voltage characteristics for each color in a liquid crystal display device.
[Explanation of symbols]
101 Source signal line drive circuit
102 Gate signal line driving circuit
103 Pixel array section
104 Each source signal line
105 Each gate signal line
106 TFT as a switching element of each pixel
201 Shift register
202 Basic circuit of shift register
203 latch 1 circuit
204 Latch 2 circuit
205 D / A conversion circuit
301 Parallel / serial conversion circuit
302 Source line selection circuit

Claims (6)

A source signal line driving circuit for driving a plurality of source signal lines; a gate signal line driving circuit for driving a plurality of gate signal lines; and a region where the plurality of source signal lines and the plurality of gate signal lines intersect. An active matrix display device having a plurality of pixel electrodes provided and a plurality of switching elements for driving the pixel electrodes,
The source signal line driving circuit includes a plurality of D / A conversion circuits, a plurality of source line selection circuits,
Have
The plurality of D / A conversion circuits have a function of converting a digital video signal into an analog video signal,
The plurality of D / A conversion circuits are electrically connected to a gradation power supply line,
The gradation power supply line has a function of supplying a maximum value of a reference voltage and a minimum value of a reference voltage in order to output a power supply voltage corresponding to RGB, and the maximum value of the reference voltage is Different corresponding to the RGB,
Each of the plurality of D / A conversion circuits is electrically connected to the multiple of three source signal lines corresponding to the RGB via any one of the plurality of source line selection circuits,
In synchronization with the timing at which the digital video signal is input to the plurality of D / A conversion circuits, the plurality of source line selection circuits respectively select source signal lines corresponding to the digital video signal among the plurality of source signal lines. The analog video signal output from the plurality of D / A conversion circuits is written to the selected source signal line,
Having one gate line selection period divided into first, second and third periods;
In the first period, the power supply voltage corresponding to the first color of the RGB is applied to the gradation power supply line, and at the same time, the source line selection circuit is one corresponding to the first color. Alternatively, a plurality of the source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits,
In the second period, the power supply voltage corresponding to the second color of the RGB is applied to the grayscale power supply line, and at the same time, the source line selection circuit has one line corresponding to the second color. Alternatively, a plurality of the source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits,
In the third period, the power supply voltage corresponding to the third color of the RGB is applied to the gradation power supply line, and at the same time, the source line selection circuit has one line corresponding to the third color. Alternatively, an active matrix display device, wherein a plurality of source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits. A source signal line driving circuit for driving a plurality of source signal lines; a gate signal line driving circuit for driving a plurality of gate signal lines; and a region where the plurality of source signal lines and the plurality of gate signal lines intersect. An active matrix display device having a plurality of pixel electrodes provided and a plurality of switching elements for driving the pixel electrodes,
The source signal line driving circuit includes a plurality of D / A conversion circuits, a plurality of source line selection circuits,
Have
The plurality of D / A conversion circuits have a function of converting a digital video signal into an analog video signal,
The plurality of D / A conversion circuits are electrically connected to a gradation power supply line,
The gradation power supply line has a function of supplying a maximum value of a reference voltage and a minimum value of a reference voltage in order to output a power supply voltage corresponding to RGB, and the maximum value of the reference voltage is Different corresponding to the RGB,
Each of the plurality of D / A conversion circuits is electrically connected to the multiple of three source signal lines corresponding to the RGB via any one of the plurality of source line selection circuits,
In synchronization with the timing at which the digital video signal is input to the plurality of D / A conversion circuits, the plurality of source line selection circuits respectively select source signal lines corresponding to the digital video signal among the plurality of source signal lines. The analog video signal output from the plurality of D / A conversion circuits is written to the selected source signal line,
Having one gate line selection period divided into first, second and third periods;
In the first period, the power supply voltage corresponding to the first color of the RGB is applied to the gradation power supply line, and at the same time, the source line selection circuit is one corresponding to the first color. Alternatively, a plurality of the source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits,
In the second period, the power supply voltage corresponding to the second color of the RGB is applied to the grayscale power supply line, and at the same time, the source line selection circuit has one line corresponding to the second color. Alternatively, a plurality of the source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits,
In the third period, the power supply voltage corresponding to the third color of the RGB is applied to the grayscale power supply line, and at the same time, the source line selection circuit has one line corresponding to the third color. Alternatively, a plurality of the source signal lines are selected and electrically connected to any one of the plurality of D / A conversion circuits,
The source signal line drive circuit has a plurality of P / S conversion circuits electrically connected to the plurality of D / A conversion circuits,
Each of the plurality of P / S conversion circuits outputs a video signal for a source signal line corresponding to the first color in the first period,
In the second period, a video signal for the source signal line corresponding to the second color is output,
An active matrix display device, wherein a video signal for a source signal line corresponding to the third color is output in the third period. In claim 1 or claim 2 ,
The source signal line drive circuit has a plurality of P / S conversion circuits electrically connected to the plurality of D / A conversion circuits,
An active matrix display device, wherein the plurality of source line selection circuits are controlled by a selection signal input to the plurality of P / S conversion circuits. In claim 3 ,
The active matrix display device, wherein the selection signal and an inverted signal of the selection signal are input to the plurality of source line selection circuits. In any one of Claims 1 thru | or 4 ,
In the one gate line selection period, each of the plurality of source line selection circuits sequentially selects all the source signal lines and is electrically connected to any one of the plurality of D / A conversion circuits.
Source signal lines electrically connected to the plurality of D / A conversion circuits correspond to the same color for RGB.
The active power supply type display device, wherein the power supply voltage for displaying a color corresponding to the source signal line corresponding to the same color is applied to the gradation power supply line. In claim 5 ,
The plurality of D / A conversion circuits are electrically connected to the source signal lines of 6 or more and a multiple of 3 through any one of the plurality of source line selection circuits,
The active matrix display device, wherein the source signal lines corresponding to the same color for each of the RGB are continuously selected in the plurality of D / A conversion circuits in the one gate line selection period.

Images