JP2645663B2 - Thin film semiconductor device and method of manufacturing the same - Google Patents
Thin film semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2645663B2 JP2645663B2 JP1013094A JP1309489A JP2645663B2 JP 2645663 B2 JP2645663 B2 JP 2645663B2 JP 1013094 A JP1013094 A JP 1013094A JP 1309489 A JP1309489 A JP 1309489A JP 2645663 B2 JP2645663 B2 JP 2645663B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor
- semiconductor thin
- conductive layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 134
- 239000004065 semiconductor Substances 0.000 title claims description 124
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 25
- 239000013078 crystal Substances 0.000 description 17
- 230000000295 complement effect Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 239000000969 carrier Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 (1) 発明の属する技術分野 本発明は、半導体薄膜を用いて実現できる高性能な薄
膜半導体装置とその製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a high performance thin film semiconductor device which can be realized by using a semiconductor thin film, and a method for manufacturing the same.
(2) 従来技術とその問題点 薄膜半導体装置は、近年、特に三次元集積回路の構成
要素あるいは平面ディスプレイ用スイッチング素子とし
て注目され、盛んに研究が行われており、例えばD.S.Ma
lhi等による論文が、IEEE Trans.Electron Devices ED
−32(1985)pp258〜281に報告されている。このような
用途に使用される半導体薄膜としては、アモルファス状
態、多結晶状態や単結晶状態のものまである。しかし,
アモルファス状態の薄膜を用いた半導体装置では、性能
が他の2者に比べて劣る問題がある。高性能な薄膜半導
体装置としては、現在、多結晶状態もしくは単結晶状態
の半導体薄膜を用いるものが最も広く研究されている。
これらの薄膜半導体装置は、キャリアとして電子を用い
るnチャネル型薄膜トランジスタ、もしくは、ホールを
用いるpチャネル型薄膜トランジスタのいずれかを使用
している。このような薄膜半導体装置では、動作時の消
費電力が大きく、その用途は、著しく制限されている。
従って、この消費電力を低減するために、nチャネル型
薄膜トランジスタとpチャネル型薄膜トランジスタと
を、同一基板上に形成し、これらの薄膜トランジスタを
連結した構造の相補型薄膜半導体装置が試みられてい
る。(2) Conventional technology and its problems In recent years, thin film semiconductor devices have attracted attention as a component of a three-dimensional integrated circuit or a switching element for a flat display, and have been actively studied.
lhi et al. published IEEE Trans.Electron Devices ED.
−32 (1985), pp. 258-281. Semiconductor thin films used for such applications include those in an amorphous state, a polycrystalline state, and a single crystalline state. However,
A semiconductor device using a thin film in an amorphous state has a problem that performance is inferior to those of the other two. As a high-performance thin film semiconductor device, a device using a semiconductor thin film in a polycrystalline state or a single crystal state has been most widely studied at present.
These thin film semiconductor devices use either an n-channel thin film transistor using electrons as carriers or a p-channel thin film transistor using holes. Such a thin-film semiconductor device consumes a large amount of power during operation, and its use is significantly restricted.
Therefore, in order to reduce this power consumption, a complementary thin film semiconductor device having a structure in which an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate and these thin film transistors are connected has been attempted.
この種の相補型薄膜半導体装置は、従来、第1図に示
す工程によって製造されている。シリコンのような半導
体もしくは絶縁材から成る基板11上に、多結晶状態、も
しくは単結晶状態の半導体薄膜のパタン12,12′を所望
の位置に形成し、ゲート絶縁膜13,13′を形成した〔第
1図(a)〕後、これを介して、ゲート電極14,14′が
形成される〔第1図(b)〕。その後、半導体薄膜のパ
タン12とゲート電極11とを露出し、一方、半導体薄膜の
パターン12′とゲート電極14′とを、レジスト15等で覆
い、この状態でn型の導電性を示す隣やひ素をイオン注
入し、ソース/ドレイン電極16を形成する。〔第11図
(c)〕。次に、イオン注入を施した半導体薄膜のパタ
ン12を、レジスト17等で覆った状態で、半導体薄膜のパ
タン12′に、p型の導電性を示すボロンをイオン注入
し、ソース/ドレイン電極16′を形成する〔第1図
(d)〕。その後、層間絶縁膜18の形成とスルーホール
開口を行う〔第1図(e)〕。次に配線19の形成によ
り、pチャネル型薄膜トランジスタ、ならびにnチャネ
ル型薄膜トランジスタのドレイン電極相互を、結線する
ことにより相補型薄膜半導体装置の製造を終わる〔第1
図(f)〕。This type of complementary thin film semiconductor device is conventionally manufactured by the steps shown in FIG. On a substrate 11 made of a semiconductor or an insulating material such as silicon, patterns 12 and 12 ′ of a semiconductor thin film in a polycrystalline state or a single crystal state were formed at desired positions, and gate insulating films 13 and 13 ′ were formed. [FIG. 1 (a)], and thereafter, gate electrodes 14, 14 'are formed via this [FIG. 1 (b)]. Thereafter, the pattern 12 of the semiconductor thin film and the gate electrode 11 are exposed, while the pattern 12 ′ of the semiconductor thin film and the gate electrode 14 ′ are covered with a resist 15 or the like. Arsenic is ion-implanted to form source / drain electrodes 16. [FIG. 11 (c)]. Next, while the ion-implanted pattern 12 of the semiconductor thin film is covered with a resist 17 or the like, boron showing p-type conductivity is ion-implanted into the pattern 12 ′ of the semiconductor thin film to form a source / drain electrode 16. '(FIG. 1 (d)). Thereafter, formation of an interlayer insulating film 18 and opening of a through hole are performed [FIG. 1 (e)]. Next, by forming the wiring 19, the drain electrodes of the p-channel thin-film transistor and the n-channel thin-film transistor are connected to each other, thereby completing the manufacture of the complementary thin-film semiconductor device [first.
(F) of FIG.
以上のような構造を有する薄膜半導体装置におけるゲ
ート電極14,14′に、制御電圧を印加すると、ゲート絶
縁膜13,13′と半導体薄膜12,12′との界面近傍に、電子
もしくはホールから成るキャリアが誘起され、チャネル
が形成される。この状態で、ソース電極/ドレイン電極
16,16′との間に電圧を加えることにより、両電極間を
上記チャネルに沿って電流が流れ、相補型薄膜半導体装
置として動作する。When a control voltage is applied to the gate electrodes 14 and 14 'in the thin film semiconductor device having the above structure, electrons or holes are formed near the interface between the gate insulating films 13 and 13' and the semiconductor thin films 12 and 12 '. Carriers are induced to form a channel. In this state, the source electrode / drain electrode
When a voltage is applied between the electrodes 16 and 16 ', a current flows between the two electrodes along the channel, and the device operates as a complementary thin film semiconductor device.
しかし、第1図に示した従来の半導体装置には、その
構造に起因する特性上の欠点がある。すなわち、チャネ
ルが、数μmから数十μmと長いため、充分に大きなド
レイン電流を得ることが困難である。この問題を解決す
るために、チャネル長をさらに短くする方法がとられて
いる。しかし、この方法では、加工技術の限界値よりも
チャネル長を短くできず、性能向上にも限界がある。さ
らに、チャネル長を短くすると、相対的に、加工のばら
つき、すなわち、半導体装置の性能のばらつきが大きく
なり、装置の製造歩留まりが低下する欠点が生じてく
る。However, the conventional semiconductor device shown in FIG. 1 has a characteristic defect due to its structure. That is, since the channel is as long as several μm to several tens μm, it is difficult to obtain a sufficiently large drain current. In order to solve this problem, a method of further shortening the channel length has been adopted. However, in this method, the channel length cannot be made shorter than the limit value of the processing technology, and there is a limit in performance improvement. Further, when the channel length is shortened, the variation in the processing, that is, the variation in the performance of the semiconductor device becomes relatively large, and there is a disadvantage that the manufacturing yield of the device is reduced.
さらに、第1図に示した相補型薄膜半導体装置におけ
る半導体薄膜としては、多結晶状態、もしくは単結晶状
態のものが広く用いられている。多結晶半導体薄膜を有
する薄膜半導体装置では、単結晶状態のものに比べて、
著しく劣った特性しか得られないのが現状である。その
理由は、結晶粒同士の境(通常、結晶粒界と称されてい
る)が、ソース電極とドレイン電極との間でのキャリア
の流れの妨げとなり、キャリアの移動度が低下するから
である。Further, as a semiconductor thin film in the complementary thin film semiconductor device shown in FIG. 1, a semiconductor thin film in a polycrystalline state or a single crystal state is widely used. In a thin film semiconductor device having a polycrystalline semiconductor thin film, compared to a single crystal semiconductor device,
At present, only extremely inferior characteristics can be obtained. The reason is that boundaries between crystal grains (usually referred to as crystal grain boundaries) hinder the flow of carriers between the source electrode and the drain electrode, and reduce the mobility of carriers. .
この半導体薄膜からなる半導体装置の欠点を除去する
目的で、キャリアの流れの妨げとなっている結晶粒界
の、チャネル内での本数を減らすか、もしくは、無くす
る方法が提案されている。前者のチャネル内での結晶粒
界を減らす方法は、長時間の熱処理を施すことにより、
結晶粒を巨大化するものである。この方法は、数十時間
という極めて長い熱処理を必要とする欠点がある。さら
に、この方法による装置の性能も十分でない。For the purpose of removing the drawbacks of the semiconductor device made of the semiconductor thin film, a method has been proposed in which the number of crystal grain boundaries that hinder the flow of carriers in the channel is reduced or eliminated. The former method of reducing the grain boundaries in the channel is to perform a long heat treatment,
It enlarges the crystal grains. This method has a drawback that requires an extremely long heat treatment of several tens of hours. Furthermore, the performance of the device by this method is not sufficient.
一方、チャネル内から結晶粒界を無くし、半導体装置
の性能を向上するために、多結晶状もしくはアモルファ
ス上の半導体薄膜にレーザ光もしくは電子ビームを照射
して、一度溶融し、単結晶状態にする方法も広く用いら
れている。しかし、この方法は、半導体装置の性能は優
れているが、半導体薄膜が溶融するために、基板とし
て、安価なガラス等の耐熱性に劣る基板を使用すること
は困難である。On the other hand, in order to eliminate the crystal grain boundaries from within the channel and improve the performance of the semiconductor device, the semiconductor thin film on the polycrystal or amorphous is irradiated with a laser beam or an electron beam, once melted, and turned into a single crystal state. Methods are also widely used. However, in this method, although the performance of the semiconductor device is excellent, it is difficult to use an inexpensive substrate such as glass which is inferior in heat resistance because the semiconductor thin film is melted.
以上に述べたように、従来の薄膜半導体装置では、優
れた性能が得られなかったり、安価な基板が使用できな
い欠点、さらに、製造歩留まりが低下する欠点がある。As described above, the conventional thin film semiconductor device has a drawback that excellent performance cannot be obtained, an inexpensive substrate cannot be used, and a manufacturing yield is reduced.
(3) 発明の目的 本発明の目的は、従来からの相補型薄膜半導体装置に
おける前記の問題点を解決し、高性能な装置を、安価な
基板上にも形成できるようにした薄膜半導体装置とその
製造方法に提供することである。(3) Object of the Invention It is an object of the present invention to provide a thin-film semiconductor device which solves the above-mentioned problems in a conventional complementary thin-film semiconductor device so that a high-performance device can be formed on an inexpensive substrate. It is to provide for the manufacturing method.
(4) 発明の構成 本発明の薄膜半導体装置のチャネルは、半導体薄膜の
パタンの側壁部に形成されており、半導体薄膜の面上に
形成されている従来のものとは異なり、著しく優れた性
能が得られる。以下、実施例を用いて、本発明の薄膜形
半導体装置とその製造方法を詳細に述べる。(4) Constitution of the Invention The channel of the thin film semiconductor device of the present invention is formed on the side wall of the pattern of the semiconductor thin film, and unlike the conventional one formed on the surface of the semiconductor thin film, extremely excellent performance is obtained. Is obtained. Hereinafter, the thin film semiconductor device of the present invention and the method of manufacturing the same will be described in detail with reference to examples.
第2図は、本発明の実施例を説明するための断面図で
ある。シリコンのような半導体もしくは絶縁材から成る
基板21上に、第一の導電層22を形成し、その後、順次、
第一の導電型のチャネルを形成するための第一の半導体
薄膜23,第二の導電層24,第二の半導体薄膜25,第三の導
電層26を形成する〔第2図(a)〕。その後、第一の導
電層22をはじめ、第一の半導体薄膜23,第二の導電層24,
第一の導電型とは異なる第二の導電型のチャネルを形成
するための第二の半導体薄膜25,第三の導電層26をエッ
チング加工し、ゲート絶縁膜27を堆積する〔第2図
(b)〕。これら、加工を施した半導体薄膜23,25のパ
タンの側壁部を覆って、ゲート電極28を形成する。次
に、第一の導電層22の一部、ならびに第二の導電層24の
一部が露出した状態になるように、第一の半導体薄膜2
3,第二の導電層24,第二の半導体薄膜25,第三の導電層26
およびゲート絶縁膜27をエッチング加工する〔第2図
(c)〕。その後、層間絶縁膜29の堆積とスルーホール
開口を行い〔第2図(d)〕、配線30を形成して、半導
体装置の製造を終わる〔第2図(e)〕。FIG. 2 is a sectional view for explaining an embodiment of the present invention. A first conductive layer 22 is formed on a substrate 21 made of a semiconductor or insulating material such as silicon, and then,
A first semiconductor thin film 23, a second conductive layer 24, a second semiconductor thin film 25, and a third conductive layer 26 for forming a channel of the first conductivity type are formed (FIG. 2A). . Thereafter, starting with the first conductive layer 22, the first semiconductor thin film 23, the second conductive layer 24,
The second semiconductor thin film 25 and the third conductive layer 26 for forming a channel of a second conductivity type different from the first conductivity type are etched to deposit a gate insulating film 27 [FIG. b)). A gate electrode 28 is formed so as to cover the sidewalls of the processed semiconductor thin films 23 and 25. Next, the first semiconductor thin film 2 is so exposed that a part of the first conductive layer 22 and a part of the second conductive layer 24 are exposed.
3, the second conductive layer 24, the second semiconductor thin film 25, the third conductive layer 26
Then, the gate insulating film 27 is etched (FIG. 2C). Thereafter, deposition of an interlayer insulating film 29 and opening of a through hole are performed [FIG. 2 (d)], and a wiring 30 is formed, thereby completing the manufacture of the semiconductor device [FIG. 2 (e)].
以上のようにして製造した相補型薄膜半導体装置にお
ける薄膜トランジスタのチャネルは、第一の半導体薄膜
23、ならびに第二の半導体薄膜25のパタンの側壁部に形
成されている。従って、ゲート電極28に、制御電圧を印
加すると、第一の半導体薄膜23、ならびに、第二の半導
体薄膜25のパタンの側壁部にキャリアが誘起され、チャ
ネルが形成される。この状態で、第一の導電層22、なら
びに、第三の導電層26との間に電圧を印加すると、相補
型薄膜半導体装置として動作し、第二の導電層24に所定
の出力が現れる。The channel of the thin film transistor in the complementary thin film semiconductor device manufactured as described above is the first semiconductor thin film.
23, and the side wall of the pattern of the second semiconductor thin film 25. Therefore, when a control voltage is applied to the gate electrode 28, carriers are induced on the side walls of the patterns of the first semiconductor thin film 23 and the second semiconductor thin film 25, and a channel is formed. In this state, when a voltage is applied between the first conductive layer 22 and the third conductive layer 26, the device operates as a complementary thin film semiconductor device, and a predetermined output appears on the second conductive layer 24.
第2図に示した第一の半導体薄膜23、ならびに第二の
半導体薄膜25は、気相成長法や真空蒸着法により、単結
晶、もしくは多結晶のものを堆積するか、あるいは上記
の方法やスパッタリング法によってアモルファス状態の
薄膜を堆積し、この薄膜にレーザ光や電子ビームを照射
したり、炉中でのアニール処理により、単結晶、もしく
は多結晶状態に変えて製作される。このような構造にな
っているため、以下に述べる理由から、たとえ半導体薄
膜が多結晶状態であっても、第1図に示した従来の半導
体装置に比べて、その性能を著しく向上することができ
る。As the first semiconductor thin film 23 and the second semiconductor thin film 25 shown in FIG. 2, a single crystal or a polycrystal is deposited by a vapor phase growth method or a vacuum evaporation method, or A thin film in an amorphous state is deposited by a sputtering method, and the thin film is manufactured by irradiating the thin film with a laser beam or an electron beam or by annealing in a furnace to change the thin film into a single crystal or a polycrystalline state. With such a structure, for the reasons described below, even if the semiconductor thin film is in a polycrystalline state, its performance can be significantly improved as compared with the conventional semiconductor device shown in FIG. it can.
この理由は、本発明の装置では、チャネル長は、専
ら、半導体薄膜の膜厚によって決まり、加工精度に特に
留意することなく、従来の半導体装置のチャネル長が数
μmから数100μmであるの対して、半導体薄膜の厚さ
に等しい0.05μmから5μmの範囲にまで小さくできる
ために、大きなドレイン電流値が得られるからである。The reason is that, in the device of the present invention, the channel length is determined solely by the thickness of the semiconductor thin film, and the channel length of the conventional semiconductor device is several μm to several hundred μm without paying special attention to the processing accuracy. This is because a large drain current value can be obtained because the thickness can be reduced from 0.05 μm to 5 μm, which is equal to the thickness of the semiconductor thin film.
さらに、本発明に用いられる第一,第二の半導体薄膜
が単結晶でなく、たとえ多結晶であっても、この多結晶
半導体薄膜における結晶粒の特性を制御することによ
り、本発明半導体装置の性能をさらに向上することがで
きる。即ち、スパッタリング法によって、アモルファス
状のシリコンもしくはゲルマニウムあるいはこれらを混
合した半導体薄膜を堆積した後、レーザ光もしくは電子
ビームを照射して多結晶化すると、基板面に垂直な柱状
の結晶粒から成る半導体薄膜となる。この半導体薄膜の
結晶粒界は、基板面に垂直で、チャネルの方向とほぼ平
行になり、キャリアの輸送の妨げとはならない。このた
め、半導体装置の性能をさらに向上することができるか
らである。Further, even if the first and second semiconductor thin films used in the present invention are not single crystals, but are polycrystalline, the characteristics of the crystal grains in the polycrystalline semiconductor thin film are controlled. Performance can be further improved. That is, after depositing amorphous silicon or germanium or a semiconductor thin film mixed with these by a sputtering method, a laser beam or an electron beam is applied to polycrystallize the semiconductor thin film to form a columnar crystal grain perpendicular to the substrate surface. It becomes a thin film. The crystal grain boundary of the semiconductor thin film is perpendicular to the substrate surface and substantially parallel to the direction of the channel, and does not hinder carrier transport. For this reason, the performance of the semiconductor device can be further improved.
上述の本発明における半導体薄膜の厚さとしては0.05
μmから5μmの範囲が最も適している。その理由とし
ては、厚さ0.05μm未満では、均一な多結晶半導体薄膜
を得ることができず、性能の劣った半導体装置となる。
一方、5μmよりも厚くすると、薄膜が基板から剥離し
たり、あるいはこの薄膜の加工が困難となる問題が生じ
てくる。The thickness of the semiconductor thin film in the present invention described above is 0.05
The range from μm to 5 μm is most suitable. If the thickness is less than 0.05 μm, a uniform polycrystalline semiconductor thin film cannot be obtained, resulting in a semiconductor device having poor performance.
On the other hand, when the thickness is more than 5 μm, there arises a problem that the thin film is peeled off from the substrate or that processing of the thin film becomes difficult.
さて、本発明の半導体薄膜としては、シリコンやゲル
マニウムもしくは、これらの混合物の他に、GaAsやInSb
等の化合物半導体も有効である。しかし、シリコンやゲ
ルマニウムの単体もしくは、これらの混合物は、薄膜の
形成と特性の制御が容易であるために本発明には最も適
している。Now, as the semiconductor thin film of the present invention, in addition to silicon, germanium, or a mixture thereof, GaAs or InSb
And the like are also effective. However, a simple substance of silicon or germanium or a mixture thereof is most suitable for the present invention because it is easy to form a thin film and control characteristics.
第2図に述べた本発明の実施例では、チャネルが半導
体薄膜のパタンの端部の一部即ち、パタンの外周の一部
のみを使用している。しかし、本発明によると、第2図
に示すのと本質的に同じ製造方法により、パタンの全周
辺をチャネルとして使用することができる。第3図は本
発明の他の実施例である。ゲート絶縁膜37とゲート電極
38を、第一の半導体薄膜33、ならびに、第二の半導体薄
膜35のパタンの周辺部全体をおおって形成し、この周辺
部全体がチャネルとなっている。31は基板を表わし、3
2,34および36は、ソース電極/ドレイン電極となる第一
の導電膜、第二の導電膜、および第三の導電膜である。
このようにすることにより、半導体装置のチャネル幅を
著しく大きくすることができ、これに比例してドレイン
電流を増大することができる。In the embodiment of the present invention described in FIG. 2, the channel uses only a part of the end of the pattern of the semiconductor thin film, that is, a part of the outer periphery of the pattern. However, according to the present invention, the entire periphery of the pattern can be used as a channel by essentially the same manufacturing method as shown in FIG. FIG. 3 shows another embodiment of the present invention. Gate insulating film 37 and gate electrode
38 is formed over the entire peripheral portion of the pattern of the first semiconductor thin film 33 and the second semiconductor thin film 35, and the entire peripheral portion serves as a channel. 31 indicates a substrate, 3
Reference numerals 2, 34 and 36 denote a first conductive film, a second conductive film, and a third conductive film serving as source / drain electrodes.
By doing so, the channel width of the semiconductor device can be significantly increased, and the drain current can be increased in proportion thereto.
なお、第2図や第3図に示した相補型薄膜半導体装置
における、上層部および下層部の薄膜トランジスタをp
チャネル型,nチャネル型のいずれにするかは、これらの
薄膜トランジスタのソース電極およびドレイン電極を構
成する材料により定めることができる。例えば、第2図
や第3図において、第一の半導体薄膜23,33のパタンの
端部にnチャネル薄膜トランジスタを、一方、第二の半
導体薄膜25,35のパタンの端部にpチャネル薄膜トラン
ジスタを製作するには、第一の導電層22,32をPやAs等
のn型不純物を含む半導体薄膜で、一方、第三の導電層
26,36は、B等のp型不純物を含む半導体薄膜で構成
し、さらに第二の導電層24,34としては、第一の半導体
薄膜23,33に接する側にはn型不純物を含む半導体薄膜
を、一方、第二の半導体薄膜25,35に接する側にはp型
不純物を含む半導体薄膜を配し、さらに、これらの半導
体薄膜で金属膜を挟んだ3層構造の導電層を用いれば良
い。上述とは反対に、第一の半導体薄膜23,33にpチャ
ネル薄膜トランジスタを、一方、第二の半導体薄膜25,3
5にはnチャネル薄膜トランジスタの相補型薄膜半導体
装置の場合には、第一,第二,第三の導電層における半
導体薄膜中の不純物の型を取り替えればよい。また、第
一の導電層22,32や第三の導電層26,36としては、不純物
を含む半導体薄膜と金属膜との複合膜とすることによ
り、この導電層の抵抗が低くなり、本半導体装置をさら
に高性能にすることができる。In the complementary thin film semiconductor device shown in FIGS. 2 and 3, the upper and lower thin film transistors are represented by p.
Whether to use the channel type or the n-channel type can be determined by the material forming the source electrode and the drain electrode of these thin film transistors. For example, in FIGS. 2 and 3, an n-channel thin film transistor is provided at the end of the pattern of the first semiconductor thin films 23 and 33, while a p-channel thin film transistor is provided at the end of the pattern of the second semiconductor thin films 25 and 35. To manufacture, the first conductive layers 22 and 32 are semiconductor thin films containing n-type impurities such as P and As, while the third conductive layer
Reference numerals 26 and 36 denote semiconductor thin films containing p-type impurities such as B. Further, as the second conductive layers 24 and 34, semiconductors containing n-type impurities on the sides in contact with the first semiconductor thin films 23 and 33 On the other hand, a semiconductor thin film containing a p-type impurity is disposed on the side in contact with the second semiconductor thin films 25 and 35, and a conductive layer having a three-layer structure in which a metal film is sandwiched between these semiconductor thin films is used. good. Contrary to the above, p-channel thin film transistors are provided on the first semiconductor thin films 23 and 33, while second semiconductor thin films 25 and 3 are provided.
In the case of a complementary thin-film semiconductor device having an n-channel thin film transistor, the type of impurities in the semiconductor thin film in the first, second, and third conductive layers may be replaced. In addition, the first conductive layers 22 and 32 and the third conductive layers 26 and 36 are formed of a composite film of a semiconductor thin film containing impurities and a metal film, so that the resistance of the conductive layers is reduced. The device can be made even more sophisticated.
以上に示した本発明では、半導体薄膜の結晶状態は多
結晶であれば良いために、低い温度で製造することがで
きる。このために、ガラス等の安価な基板状に高性能な
半導体装置を形成することができる。In the present invention described above, the semiconductor thin film can be manufactured at a low temperature because the crystalline state of the semiconductor thin film only needs to be polycrystalline. For this reason, a high-performance semiconductor device can be formed on an inexpensive substrate such as glass.
(5) 発明の効果 以上に説明したように、本発明では、チャネルを半導
体薄膜のパタンの側壁部に形成するために、チャネルの
短い薄膜半導体装置となる。さらに、本半導体薄膜が多
結晶状態の場合には、キャリアの輸送の妨げとなる結晶
粒界をチャネルの方向とほぼ平行にすることができる。
これらの理由から、本発明により高性能な相補型薄膜半
導体装置が得られる。(5) Effects of the Invention As described above, in the present invention, a channel is formed on the side wall of the pattern of the semiconductor thin film, so that the thin film semiconductor device has a short channel. Further, when the present semiconductor thin film is in a polycrystalline state, a crystal grain boundary which hinders carrier transport can be made substantially parallel to the channel direction.
For these reasons, the present invention provides a high-performance complementary thin-film semiconductor device.
さらに、本発明では、低い温度で相補型薄膜半導体装
置が製作できるため、安価なガラス等の基板が使用でき
る利点もある。Further, in the present invention, since a complementary thin film semiconductor device can be manufactured at a low temperature, there is an advantage that an inexpensive substrate such as glass can be used.
第1図は従来の薄膜形半導体装置の製造方法を説明する
ための断面図、第2図は本発明による薄膜形半導体装置
の製造方法を説明するこめの断面図、第3図は本発明に
よる薄膜形半導体装置の他の実施例を示す断面図であ
る。 11,21,31……基板、12,12′……半導体薄膜パタン、23,
33……第一の半導体薄膜、25,35……第二の半導体薄
膜、22,32……第一の導電層、24,34……第二の導電層、
26,36……第三の導電層、13,13′,27,37……ゲート絶縁
膜、14,14′,28,38……ゲート電極、16,16′……ソース
電極/ドレイン電極、18,29,39……層間絶縁膜、19,30,
40……配線。FIG. 1 is a cross-sectional view for explaining a conventional method for manufacturing a thin-film semiconductor device, FIG. 2 is a cross-sectional view for explaining a method for manufacturing a thin-film semiconductor device according to the present invention, and FIG. It is sectional drawing which shows the other Example of a thin film type semiconductor device. 11,21,31 …… Substrate, 12,12 ′ …… Semiconductor thin film pattern, 23,
33 ... first semiconductor thin film, 25,35 ... second semiconductor thin film, 22,32 ... first conductive layer, 24,34 ... second conductive layer,
26,36 ... third conductive layer, 13, 13 ', 27, 37 ... gate insulating film, 14, 14', 28, 38 ... gate electrode, 16, 16 '... source electrode / drain electrode, 18,29,39 …… Interlayer insulating film, 19,30,
40 ... Wiring.
Claims (2)
チャネル型薄膜トランジスタから成る薄膜半導体装置に
おいて、前記pチャネル型薄膜トランジスタならびにn
チャネル型薄膜トランジスタを構成する半導体薄膜の積
層体が、導電層を挟んで積層された第一の半導体薄膜な
らびに第二の半導体薄膜から構成され、さらに、前記第
一の半導体薄膜のパタンの側壁部ならびに前記第二の半
導体薄膜のパタンの側壁部を覆って、ゲート電極がゲー
ト絶縁膜を介し、形成されていることを特徴とする薄膜
半導体装置。1. A p-channel type thin film transistor and n
A thin film semiconductor device comprising a channel type thin film transistor, wherein the p channel type thin film transistor and n
A stacked body of semiconductor thin films constituting a channel type thin film transistor is composed of a first semiconductor thin film and a second semiconductor thin film stacked with a conductive layer interposed therebetween, and further, a sidewall portion of the pattern of the first semiconductor thin film and A thin film semiconductor device, wherein a gate electrode is formed via a gate insulating film so as to cover a side wall of the pattern of the second semiconductor thin film.
第一の導電型のチャネルを形成するための第一の半導体
薄膜を前記第一の導電層上に形成する工程と、第二の導
電層を前記第一の半導体薄膜上に形成する工程と、前記
第一の導電型とは異なる第二の導電型のチャネルを形成
するための第二の半導体薄膜を前記第二の導電層上に形
成する工程と、第三の導電層を前記第二の半導体薄膜上
に形成する工程と、前記第一の導電層を加工する工程
と、前記第一の半導体薄膜を加工する工程と、前記第二
の導電層を加工する工程と、前記第二の半導体薄膜を加
工する工程と、前記第三の導電層を加工する工程と、さ
らに、前記の加工を施した第一の半導体薄膜と第二の半
導体薄膜のパタンの側壁部を覆って、ゲート電極をゲー
ト絶縁膜を介して形成する工程とを含むことを特徴とす
る薄膜半導体装置の製造方法。2. A step of forming a first conductive layer on a substrate;
A step of forming a first semiconductor thin film for forming a channel of the first conductivity type on the first conductive layer, and a step of forming a second conductive layer on the first semiconductor thin film, Forming a second semiconductor thin film on the second conductive layer for forming a channel of a second conductivity type different from the first conductivity type, and forming a third conductive layer on the second conductive layer; Forming on a semiconductor thin film, processing the first conductive layer, processing the first semiconductor thin film, processing the second conductive layer, and forming the second semiconductor A step of processing the thin film, a step of processing the third conductive layer, and further covering the side wall of the pattern of the processed first semiconductor thin film and the second semiconductor thin film, forming a gate electrode. Forming a thin film semiconductor device via a gate insulating film. Production method.
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