JPH01133381A - Superconducting transistor - Google Patents

Abstract

PURPOSE:To integrate an element configuration by providing a first semiconductor layer through an insulating layer on thin superconducting films which become source and drain regions formed oppositely at a narrow gap on a semiconductor substrate, forming a second semiconductor region buried in the gap between the films and connected to the first semiconductor layer, and providing a gate region on the semiconductor layer above the gap. CONSTITUTION:After thin superconducting films 2, 3 are deposited by a sputtering method or the like on a silicon substrate 1, silicon dioxide films 5, 6 are deposited, and patterned by an ion beam etching method or the like with a mask. Thereafter, silicon is grown by a molecular beam epitaxy method. In this case, a single crystalline silicon 4 is grown in the gap between superconducting regions in contact with the substrate 1, and polycrystalline films 7, 8 are grown on the films 5, 6. Thereafter, an aluminum electrode which becomes a gate is formed on the silicons 4 and 7, 8. Thus, since source, drain and gate electrodes can be all formed on the substrate, they can be easily integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to superconducting elements, and particularly to a three-terminal superconducting transistor that combines a semiconductor and a superconductor.

Conventional technology Three-terminal devices that utilize the superconducting phenomenon to achieve high-speed operation have been proposed in both bipolar and FET types, similar to semiconductor transistors, but the FET type has a simple structure and is not suitable for high performance. A stone considered to have a promising future. FIG. 2 shows a conventionally proposed superconducting FET. In FIG. 2, 11 is a semiconductor such as silicon, and 12 and 13 are superconducting regions, which are provided on the semiconductor 11 at extremely narrow intervals. Reference numeral 14 denotes a metal gate made of aluminum or the like, which is formed by making a recess from the back side of the semiconductor substrate directly under the gap between the superconductors. In the operation of this element, the wave functions of the two superconductors (12, 13) sandwiched by a narrow gap leak out, causing current to flow in the silicon substrate 11. This current is controlled by a voltage applied to the gate 14 close to the gap, and the current value can be increased or decreased.

Problems to be Solved by the Invention However, with this structure, as shown in the figure, since the gate is formed from the back side, it is impossible to integrate the structure into an integrated circuit.

The present invention has been made in view of these problems, and an object of the present invention is to provide an element structure that can be integrated into an integrated circuit in order to realize a superconducting transistor capable of high-speed operation.

Means for Solving the Problems In order to solve the above problems, the present invention includes a semiconductor substrate, a source and drain region formed of superconducting thin films facing each other with a narrow gap on the base thereof, and a first semiconductor layer provided above the drain region via an insulating layer; a second semiconductor bright ring that fills the gap between the superconducting thin films and is connected to the first semiconductor layer; and a semiconductor above the gap. The present invention provides a superconducting transistor comprising a gate region provided on a layer.

Function: Due to the above-described structure, the present invention has a lower source electrode than a conventional FET type superconducting transistor.

Since both the drain electrode and the gate electrode can be formed on the top of the substrate, integrated circuits can be easily realized, and as a result, superconducting transistors can be put to practical use.

Embodiment FIG. 1 shows a cross-sectional view of a superconducting transistor according to an embodiment of the present invention. In Figure 1, 1 is a silicon substrate, 2 is a superconducting thin film that becomes a drain, 3 is a superconducting thin film that becomes a source,
4 is a single crystal silicon region provided in the gap between superconducting regions 2 and 3, 5 and 6 are insulating films such as silicon dioxide, 7,
8 is a polycrystalline silicon region. 9 is a gate electrode made of metal such as aluminum.

Next, the manufacturing process of the superconducting transistor of the example will be briefly described. First, a superconducting thin film is deposited on a silicon substrate 1 by sputtering or the like, then a silicon dioxide film is further deposited, and a pattern is formed by ion beam etching or the like using a mask. Thereafter, silicon is grown using the molecular beam epi-chip method.

At this time, single crystal silicon grows in the gap between the superconducting regions in contact with the silicon substrate 1, and a polycrystalline film grows on the silicon dioxide film. Thereafter, an aluminum electrode serving as a gate is formed on the single crystal silicon 4 and the polycrystalline silicon 7.8.

The operation of the superconducting transistor with this structure is that it is a field effect type (FET type) transistor, similar to the conventional superconducting transistor shown in FIG. The current is increased or decreased by controlling the voltage.

Effects of the Invention Therefore, according to the present invention, an integrated circuit can be realized more easily than the conventional FET type superconducting transistor. Furthermore, since the film thickness of the silicon region directly under the gate, which serves as the channel region, can be controlled to be thin, it is possible to form a transistor in which the gate electric field is easy to increase and control.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a superconducting transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional superconducting transistor. 1... Silicon substrate, 2, 3... Superconducting layer, 4... Single crystal silicon region, 6, 6...
...Insulating film, 7゜8...Polycrystalline silicon,
9...Gate electrode. 9----day) Skin J1 Figure 2

Claims (1)

[Claims] A semiconductor substrate, source and drain regions formed of opposing superconducting films with a narrow gap on the semiconductor substrate, and a first semiconductor layer provided above the source and drain regions with an insulating layer interposed therebetween. , a second semiconductor region that fills the gap between the superconducting thin films and is connected to the first semiconductor layer; and a gate region provided above the gap via the first semiconductor layer and the second semiconductor region. A superconducting transistor comprising: