JP3057770B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor which is formed on an insulating substrate and is effective for application to a liquid crystal display device, an image scanner and the like.

[0002]

2. Description of the Related Art FIG. 3 shows a general example of a conventional method of manufacturing a thin film transistor formed on an insulating substrate. First, a semiconductor thin film layer 302 to which a high concentration impurity is added is formed as a source / drain region on a transparent insulating substrate 301, and is patterned as shown in FIG. Thereafter, a semiconductor layer 303 as an active region is laminated and patterned, and then a gate insulating film 304 is laminated, as shown in FIG.
Thereafter, a gate electrode 305 is laminated and patterned, an interlayer insulating film 306 is laminated, a contact hole 307 is opened, and a source electrode terminal 308 and a drain electrode terminal 3 are formed.
09 is formed to complete a thin film transistor as shown in FIG.

In the above-mentioned conventional technique, the source / drain region is formed by a semiconductor thin film containing impurities. However, according to this method, the overlap between the gate electrode and the source / drain region becomes a parasitic capacitance, and the thin film transistor of the thin film transistor is formed. It is disadvantageous for speeding up. In the contact between the source and drain regions and the semiconductor layer as the active region,
Since there is a junction defect, the off-state current cannot be reduced. Therefore, what has been considered is a method of forming the source and drain regions in a self-aligned manner by an ion implantation method or the like. FIG. 4 shows the structure of a thin film transistor formed by this method. Reference numeral 401 denotes an insulating substrate, 402 denotes source / drain regions formed in a self-aligned manner by ion implantation or the like, 403 denotes an active region, 404 denotes a gate insulating film, 405 denotes a gate electrode, 406 denotes an interlayer insulating film,
07 is a contact hole, 408 is a source electrode, 409
Represents a drain electrode.

As shown in FIG. 4, by forming the source and drain regions in a self-aligned manner, an overlapping portion between the source and drain regions and the gate electrode is formed.
Since only the impurity diffusion region is provided, the speed of the thin film transistor can be increased. In addition, the above-described bonding defects are eliminated, and off-state current can be suppressed.

In recent years, applications of the thin film transistor thus obtained to liquid crystal devices have been considered. Therefore, it is desired to use a glass substrate which is inexpensive and can have a large area as an insulating substrate. However, the glass substrate lacks heat resistance, and the vapor deposition method must be used to form the gate insulating film. Therefore, in the coplanar thin film transistor described in the above prior art, the composition shift is large at the interface between the semiconductor layer, which is the active region, and the gate insulating film, and impurities such as impurities exist on the surface of the active region. Therefore, it was difficult to form a clean interface, and it was difficult to obtain good electrical characteristics.

On the other hand, a method for recrystallizing the active region has been proposed as a means for increasing the mobility of the active region. However, in a thin film transistor having no clean interface formed by the above-described conventional technique, impurities adhering to the surface of the active region enter the inside of the active region during recrystallization and become a defect. The effect of conversion was also small.

The present invention solves the problems of the method of manufacturing a thin film transistor, including the step of forming a gate insulating film after forming such an active region. The object of the present invention is to form a clean interface. Higher speed, higher performance, and lower power consumption by obtaining good electrical characteristics, forming source and drain regions in a self-aligned manner, and recrystallizing the silicon layer that is the active region. It is an object of the present invention to provide a highly reliable method for manufacturing a thin film transistor.

[0008]

According to a method of manufacturing a thin film transistor of the present invention, a silicon layer is formed while flowing a hydrogen gas on a substrate disposed in a chamber, and the silicon layer is formed for a predetermined period even after the silicon layer is formed. By continuing to flow hydrogen gas and introducing oxygen into the chamber after the lapse of the predetermined period, the silicon layer and the first
Forming a gate insulating film continuously, patterning the silicon layer and the first gate insulating film,
Forming a second gate insulating film on the first gate insulating film. The method for manufacturing a thin film transistor according to the present invention includes forming a silicon layer while flowing hydrogen gas on a substrate disposed in a chamber, and reducing the flow rate of hydrogen gas introduced into the chamber and increasing the flow rate of oxygen. A step of continuously forming the silicon layer and the first gate insulating film on a substrate; a step of patterning the silicon layer and the first gate insulating film; and a second gate insulating film on the first gate insulating film And a step of forming In the method for manufacturing a thin film transistor according to the present invention, a step of crystallizing the silicon layer after forming the first gate insulating film and before a step of patterning the silicon layer and the first gate insulating film. It is characterized by having.

[0009]

FIG. 1 is a diagram showing one embodiment of the present invention in a method of manufacturing a thin film transistor in the order of manufacturing steps. First, as shown in FIG. 1A, a silicon layer 102 is formed on an insulating substrate 101 by an ECR-plasma technique, and the first gate insulating film layer is continuously formed in the same chamber without breaking vacuum. 103 is formed. After that, the silicon layer serving as an active region is recrystallized by performing a laser annealing process. After that, the first gate insulating film 103 and the silicon layer 102 are simultaneously patterned, and subsequently, a second gate insulating film 104 is formed on the entire surface. A silicon dioxide film, a silicon nitride film, or the like is formed on the second gate insulating film 104 by a normal-pressure CVD method, a low-pressure CVD method, a plasma CVD method, an ECR plasma CVD method, an optical CVD method.
It is formed and used by methods, or combinations thereof. Next, after a conductive thin film layer to be a gate electrode is formed by a sputtering method or the like, the portion except for the gate electrode 105 is etched to obtain FIG. 1 (b). For the gate electrode, a metal such as Al.Cr or a conductive thin film such as polycrystalline silicon is used. Then, as shown in FIG. 1C, the source and drain regions 107 are formed by implanting impurities 106 by an ion implantation method such as an ion implantation method or an ion doping method. Next, the interlayer insulating film layer 108 is laminated, and then,
The first gate insulating film 103, the second gate insulating film 104, and the interlayer insulating film are removed from portions where source / drain electrodes are to be formed to form contact holes 109, and a source electrode 110 and a drain electrode 111 are formed in those portions. And
FIG. 1D is obtained. In the formation of the second gate insulating film 104, polyimide or the like may be used for the interlayer insulating film 108 in addition to the insulating film formed by the same method as that used in the formation of the second gate insulating film 104.

In this embodiment, the time change of the flow rate of the forming gas when the silicon layer as the active region and the gate insulating film layer are continuously formed by the ECR-plasma technique is shown in FIG.
(A). When this method is used, the interface between the silicon layer and the gate insulating film layer, which are the active regions, is not exposed to the atmosphere, so that the interface becomes a clean interface free from attachment of impurities to the natural oxide film and the surface. Electrical characteristics are obtained. As still another method, as shown in FIG. 2B, the forming gas flow rate can be changed. By using this method, in addition to the advantages obtained by the above method, it is possible to eliminate the discontinuity of the material between the silicon layer and the gate insulating film layer which are the active regions. As a result, junction defects are reduced, so that charges trapped at the end surface of the silicon layer as an active region can be reduced. On the other hand, FIG.
Even if the gas flow rate is changed as in (c), trapping of charges on the silicon end face can be reduced. According to this method, the dangling bond (unpaired electron pair) on the silicon end face, which is a cause of charge trapping, can be filled by continuing the flow of hydrogen gas after forming the silicon layer. As a result, good electrical characteristics are also obtained. In addition, when the silicon layer and the gate insulating film layer are formed by the ECR-plasma technology, the formation pressure is in a high vacuum of about millimeters, so that the impurity in the atmosphere is formed in the thin film. An ideal thin film without traps due to the possibility of being mixed into the film can be formed.

When the silicon layer thus obtained is recrystallized, the mobility of the silicon layer is increased. As described above, since the interface between the silicon layer and the gate insulating film layer is clean without impurities attached, when the silicon layer is recrystallized, traps are formed in the thin film due to the impurities at the interface. The effect of recrystallization can be maximized without being performed. In this embodiment, the laser annealing for recrystallizing the silicon layer as the active region is performed after the formation of the first gate insulating film, but this is performed after the formation of the first gate insulating film. If so, you may go anytime. On the other hand, the same can be said for a case where a solid phase growth method is used for recrystallization of a silicon layer which is an active region.

In this embodiment, the source / drain regions are formed in a self-aligned manner. However, needless to say, a clean interface can be formed even when a semiconductor thin film layer to which impurities are added is used.

[0013]

As described above, according to the method for manufacturing a thin film transistor of the present invention, the following effects can be obtained. (A) Since a silicon layer and a gate insulating film, which are active regions, are successively formed and then patterned, there is no attachment of impurities and the like to the surface of the silicon layer, and since there is no natural oxide film, a clean interface is formed. it can. (B) When forming a silicon layer which is an active region and a gate insulating film in contact with the silicon layer, by making the boundary surface physically continuous, it is possible to reduce the composition deviation at the end surface of the thin film layer, Good electrical characteristics are obtained. (C) Since hydrogen gas flows when the silicon layer and the gate insulating film are continuously formed, dangling bonds on the silicon end face, which cause charge trapping, can be buried, and good electrical characteristics can be obtained.

By the above-described many effects, a highly reliable thin film transistor which can be operated at high speed, with high performance and with low power consumption can be constructed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views of a thin film transistor according to an embodiment of the present invention, for each manufacturing process.

FIGS. 2A to 2C are diagrams showing a change over time of a gas flow rate during continuous film formation of a silicon layer and a gate insulating film layer in an example of the present invention.

FIGS. 3A to 3C are cross-sectional views of a conventional coplanar thin film transistor for each manufacturing process.

FIG. 4 is an element cross-sectional view of a conventional coplanar thin film transistor in which source and drain regions are formed in a self-aligned manner.

[Explanation of symbols]

 101, 301, 401 Insulating substrate 107, 302, 402 Source / drain region 102, 303, 403 Semiconductor layer 103, 104, 304, 404 to be an active region Gate insulating film 105, 305, 405 Gate electrode 106 Impurity 108, 306 406 interlayer insulating film 109, 307, 407 contact hole 110, 308, 408 source electrode 111, 309, 409 drain electrode

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/205 H01L 21/31 H01L 21/336

Claims (3)

(57) [Claims] 1. A method for forming a silicon layer while flowing a hydrogen gas on a substrate disposed in a chamber, and continuously flowing the hydrogen gas for a predetermined period after the silicon layer is formed,
Flowing the oxygen into the chamber after the lapse of the predetermined period to continuously form the silicon layer and the first gate insulating film on the substrate, and patterning the silicon layer and the first gate insulating film The step and the first
Forming a second gate insulating film on the gate insulating film. 2. A silicon layer is formed while flowing hydrogen gas on a substrate disposed in a chamber, and the flow rate of hydrogen gas introduced into the chamber is reduced and the flow rate of oxygen is increased. A step of continuously forming a silicon layer and a first gate insulating film; a step of patterning the silicon layer and the first gate insulating film; and a step of forming a second gate insulating film on the first gate insulating film And a method of manufacturing a thin film transistor. 3. The method according to claim 1, further comprising a step of crystallizing the silicon layer after forming the first gate insulating film and before a step of patterning the silicon layer and the first gate insulating film. The method for manufacturing a thin film transistor according to claim 1 or 2, wherein: