JPS61224360A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a high reliability FET which has a required channel length in good reproductivity by preventing etching under a gate electrode, providing a mask on the side wall of the gate electrode on an insulation film. CONSTITUTION:An n<-> poly-Si thin film 2, an SiO2 layer 3 and a conductive poly-Si 4 are piled on a glass plate 1, the conductive layer 4 is etched, using a resist mask 5, and a gate electrode 6 W wide is made. A mask 20 is made on the side surface of the electrode 6 by RIE often covering with a photoresist 21. The formation of a bottom under the gate electrode 6 is prevented by isotropically etching with HF selecting the thickness T of the mask 20 and the width Ws of a gate insulation film 7. N<+> diffusion layers 2s, 2d; n<-> channel 2c are made by covering with a PSG 9 often removing resists 5, 7. Electrodes 10s, 10d are attached by opening a window on the PSG 9. This construction enables to avoid the unnecessary and unstable side surface etching of the gate insulation film, to effectively prevent unstable short channeling and to obtain a high reliability FET in good reproductivity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable and suitable for obtaining field effect transistors, particularly thin film transistors formed by a polycrystalline silicon layer formed on an insulating substrate, for example. It is concerned with the manufacturing method of field effect transistors.

[Summary of the invention]

In the present invention, prior to pattern etching of the gate insulating film, a mask member is placed on the side surface of the gate electrode formed thereon, and in this way, the mask material penetrates under the gate electrode and forms the gate insulating film. To avoid the inconvenience caused by overhanging portions caused by etching.

[Conventional technology]

For example, in a drive circuit for a liquid crystal display device, a thin film transistor such as an insulated gate field effect transistor (Mis-FET) is formed on a polycrystalline silicon layer deposited on an insulating substrate such as a glass substrate.

A conventional method for manufacturing such a thin film MIS-FET will be explained with reference to FIG.

First, as shown in Figure 2A, an insulating substrate (1
) A high resistivity n-type or p-type semiconductor (2) made of polycrystalline silicon, for example, is coated with an insulating layer (3) such as 5T02 which becomes a gate insulating film. A conductive layer (4) made of, for example, low resistivity polycrystalline silicon, which will eventually constitute a gate electrode, is deposited thereon.

Next, as shown in Figure B, the conductive layer (4) is etched into a predetermined pattern to form a gate electrode (6) having a predetermined width W corresponding to the gate length of the MIS-FET that is finally obtained.
form. The patterning for forming this gate electrode (6) is done by photolithography. In other words, a photoresist (5) is formed as an etching resist on the conductive layer (5) using a photographic technique, and this is used as a mask to form the conductive layer (5).
This can be done by selectively etching the odor.

Thereafter, as shown in FIG.
Etching of the 5L (h) insulating layer (3) to form the gate insulating layer (3) is usually carried out using an oxalic acid solution.

In this case, the etching is done isotropically.

Therefore, when etching the insulating layer (3), so-called side etching occurs, which proceeds from the edge of the gate electrode (6). Therefore, the gate insulating film (7) thus obtained is formed to have a width W1 smaller than the width W of the gate electrode (6) as shown in FIG. The edge of the gate electrode (6) extends above the eaves 8)
is formed.

Next, as shown in the second diagram, an insulating layer (9) of the same conductivity type as the semiconductor (2), such as phosphorus silicate glass doped with phosphorus, an n-type impurity, is completely covered. It is deposited by a technique such as chemical vapor deposition (CVD). Then, the impurities in this insulating layer (9) are diffused from the part directly deposited on the semiconductor (2) to form a semiconductor layer).
A source region (2S) and a drain region (2d) each having a high impurity concentration are formed on both sides of the gate insulating film (7). In this case, the source region (23) and the drain region (2
Since the diffusion d) is formed by penetrating under the gate insulating film (7) from its edge, the distance between both the source region (2s) and the drain region (2d), that is, the gate length (channel length) L, is the gate insulating film (7). It is formed to be smaller than the width W1 of the insulating film (7).

Next, electrode windows are selectively opened in the insulating layer (9), and ohmic source electrodes (10s) and drain electrodes (10d) are formed in the source region (23) and drain region (2d), respectively.
Form the adhesion. S, G, and D indicate source, gate, and drain terminals, respectively.

In this way, the source region (23
) and a drain region (2d) are formed, a channel formation region (2c) is formed between them, and a gate electrode (6) is formed on the channel formation region (2c) via a gate insulator 111 (7). The desired thin layer protrusion-type Mis-PET having a section is obtained.

-However, the MIS-FET obtained by this method
As explained with reference to FIG. 2C, the gate electrode (
6) Since 8) is formed below, a gate electrode 1111 is formed on the insulating layer (9) doped with impurities formed on the insulating layer (9) made of, for example, phosphorus silicate glass.
Cavities or unstable defects (11) that are not well adhered occur on both sides of the (?).

Therefore, in the Mis-FET obtained in this way,
This means that the portions of the source region (2s) and drain region (2d) adjacent to the gate portion are not well covered with the insulating layer. For this reason, this MIS-FET has the disadvantage of low reliability, such as leakage occurring between the gate, source, and drain. In addition, the insulating layer (3
) to form the gate insulating film (7), side etching occurs as described above;
Furthermore, since impurities from the insulating layer (9) for forming the source and drain are diffused into the thin semiconductor (2), the distance between the source region (2s) and the drain region (2d) is unstable. In particular, in thin-film Mis-FETs, it is difficult to manufacture Mis-FETs with a small channel length as designed and highly reliable and uniform characteristics with good reproducibility. The problem is that it is difficult.

[Problem that the invention seeks to solve]

In the present invention, as mentioned above, the thin film type MIS-FE
In the fabrication of a transistor T, it is an attempt to solve reliability problems such as leakage between the gate, source, and drain, and problems such as shortening of the channel.

(Means for Solving the Problems) In the present invention, as shown in the manufacturing process diagram in FIG. a step of forming a gate electrode (6) on this insulating layer; a step of forming an etching mask member (20) on the side wall of the gate electrode (6); and a step of etching the exposed portion of the insulating layer (3). removing the etching mask member (20) to form a gate insulating film (7);
This prevents the etching from being removed under the gate electrode when etching the insulating layer (3).

[Effect]

According to the method of the present invention described above, the etching mask member (20) is deposited on the side wall of the gate electrode (6), thereby forming the □ insulating layer (2) for forming the gate insulator 11i (7).
In the selective etching of 3), the gate electrode (6)
It is possible to avoid etching from occurring underneath. Therefore, the impurity-containing insulating layer to be formed later is deposited on the portion of the semiconductor (2) that is not covered by the gate insulating layer (3) without creating defects such as cavities, and the conventional method described at the beginning is used. Eliminate shortcomings.

〔Example〕

Referring again to FIG. 1, the thin film type M! according to the present invention will be described. 5-FET
An embodiment of the manufacturing method will be described in detail.

In FIG. 1, parts corresponding to those in FIG. 2 are given the same reference numerals. In this example as well, as shown in FIG. For example, a semiconductor (2) is selectively formed in a predetermined pattern, and an insulating layer (3) such as 5i (h), which will eventually constitute a gate insulating film, is formed on this semiconductor (2) by CVD or the like. A conductive layer (4) of low resistivity, i.e. polycrystalline silicon or the like doped with a high concentration of impurities, on which a gate electrode (6) will finally be formed is similarly formed by CVD etc. Deposited by.

Next, as shown in FIG. 1B, an etching resist (5) such as a photoresist is selectively formed on the conductive layer (4) in the portion where the gate portion will ultimately be formed, using a well-known technique. Using the etching resist (5) as an etching mask, the conductive layer (4) is selectively etched to form a gate electrode (6) having a predetermined width W.

Next is the 1st V! As shown in JC, a mask material (21) is applied over the entire surface of the gate electrode (6) so as to be coated on at least the side surfaces thereof. In this case, if a photoresist is used as the mask material (21), this can be used as the gate electrode (6).
It can be easily applied to cover the sides.

Next, as shown in the first diagram, etching progresses from the surface of the mask material (21) in the thickness direction, that is,
Etching is performed by reactive ion etching (RIE) using anisotropic 02 gas, for example, to leave a substantially thick portion 9 attached to the side surface of the electrode (6). By removing other portions of the mask material (21), mask members (20) selectively formed on the side surfaces of the gate electrode (6) are formed.

Next, as shown in FIG. 1E, using this mask member (20) as a mask, the insulating layer (3) is selectively etched by, for example, isotropic etching using hydrofluoric acid.
In this case, by selecting the thickness of the mask material (21) to allow light to pass through, the thickness t of the mask member (20) attached to the side wall of the gate electrode (6) is selected to a predetermined thickness; The width Ws of the gate insulating film (7) is selected so that even if side etching occurs in the gate insulating film (7), it will not get under the gate electrode (6) and create an eaves. .

As shown in FIG. 1F, the mask member (20) and the etching resist (5) are removed to remove impurities such as n-type impurity phosphorus that will eventually form the source and drain regions.
An insulating layer (9) made of phosphorus-silicate glass containing phosphorus and silicate glass is deposited on the entire surface, and impurities are diffused into the semiconductor (2) from the gate insulating film (the part not covered by the sword). A source region (2s) and a drain region (2d) with high impurity concentration are formed, and a region having a predetermined length between these source region (2s) and drain region (2d) and not doped with impurities, that is, a channel formation A region (2c) is formed.

Next, as shown in FIG.
2d) A source electrode (10s) and a drain electrode (10d) are respectively deposited on top. In this way, the target M
An IS-FET is obtained.

According to the MIS-FET obtained in this way, the formation of a gate insulating film (η) that penetrates under the gate electrode (6), that is, the formation of a canopy, is avoided. No defects such as cavities occur under the insulating layer (9), and the insulating layer (9) is made of a semiconductor (2c).
The gate insulating film (7) is formed so as to reliably cover the entire surface other than the deposited portion.

Note that although the illustrated example is an n-channel type MIS-FET, an MIS-FET having a conductivity type opposite to that shown in the figure
Various modifications may be made, such as forming an IS-FET.

〔Effect of the invention〕

As described above, according to the manufacturing method of the present invention, since the insulating layer (9) is reliably coated on the semiconductor (2), it is possible to avoid the occurrence of leakage between the gate and the source and drain described at the beginning. In addition, the gate insulating film is side-etched unnecessarily and unstablely, and unstable short channels are formed due to the intrusion of the source region (2s) and drain region (2d) due to impurity doping into the thin film semiconductor (2). Since the distortion can be effectively avoided, a highly reliable Mis-FET having the desired desired channel length can be obtained with good reproducibility, and it is of great benefit in practical use.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of an example of a method for manufacturing a field effect transistor according to the present invention, and FIG. 2 is a process diagram of a conventional method. (1) is an insulating substrate, (2) is a semiconductor, (3) is an insulating layer that constitutes a gate insulating film (7), and (4) is a gate electrode (6).
), (21) is a mask material, (20) is a mask member, (2s) and (2d) are source and drain regions. Yokeikosha Exit Diagram 1

Claims (1)

[Claims] (a) a step of forming an insulating layer to serve as a gate insulating film on the semiconductor; (b) a step of forming a gate electrode on the insulating layer; (c) a step of forming a gate electrode on the insulating layer;
) forming a mask member on the side wall of the gate electrode; (d) selectively removing the exposed portion of the insulating layer to form a gate insulating film; A method for manufacturing a field effect transistor, the method comprising: suppressing the removal of below the gate electrode.