JP2765142B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention mainly relates to a method of manufacturing a semiconductor device such as an insulated gate electrostatic induction transistor.

(Prior Art) As an insulated gate type electrostatic induction transistor, a structure as shown in FIG. 4 in which a conventional junction gate is replaced with an insulated gate can be considered. The structure is shown in FIG.
Is an n-type drain region, 11 is a drain electrode, and is in ohmic contact with the drain region 1. 2 is an n + source region, 3 is a gate electrode, and is insulated from the drain region 1 and the source region 2 by a gate insulating film 4. Reference numeral 5 denotes an interlayer insulating film on which a source electrode 22 is provided, which is electrically connected to the source region 2. The drain region sandwiched between the two insulated gates will be referred to as the “channel” of the device structure, and the distance between the two insulated gates indicated by H in the drawing will be referred to as the “channel region thickness”. To In this structure, the current is interrupted by the depletion layer developed around the insulated gate, but unlike the junction gate, the insulated gate is developed by forming a minority carrier accumulation layer around the gate insulating film. There is a limit to the width of the depletion layer that can be obtained. Therefore, the impurity concentration of the channel region
The thickness H of N _D and the channel region can limit given by the following equation. The meaning of the expression is twice as large as the width of the depletion layer that can be developed by one of the insulated gates. When H is larger than the right side of the equation,
No matter how much voltage is applied to the gate, the current cannot be cut off.

In the above equation, q is the elementary charge, ε is the dielectric constant of the semiconductor in the drain region, φ _f is the absolute value of the Fermi potential of the semiconductor,
It is given by the following equation.

.3033.3. Man's constant, T is the absolute temperature, N _i is the intrinsic carrier concentration of the semiconductor of the drain region. As an example of the numerical values, when the semiconductor is silicon, when the impurity concentration of the drain region is 1 × 10 ¹⁴ cm ⁻³ , the gate interval is 4.8 μm or less and 1 × 1
At 0 ¹⁵ cm ^-3 , the thickness is required to be 1.7 μm or less.

When the impurity concentration is required to be high to some extent, such as in a low breakdown voltage device, it is difficult to form such a fine structure.

As a proposal for avoiding the "limitation of the thickness of the channel region", there is a method described in Japanese Patent Publication No. 62-44698 "insulated gate transistor". The device according to the publication has a structure in which another fixed potential control gate is provided near a driving U-shaped insulating gate, and various characteristics of the device are controlled by the potential of the control gate. The fixed potential control gate may be a pn junction gate or a Schottky gate, or, of course, a different type of insulated gate.

FIG. 5A is a cross-sectional view showing the structure in the case where the control gate is fixed at the source potential by using the coupling gate. In FIG.
Numeral 1 is an n-type drain region, 11 is a drain electrode, and is in ohmic contact with the drain region 1. Reference numeral 2 denotes an n ⁺ source region, 3 denotes a driving gate electrode, and the drain region 1 and the source region 2 are insulated from each other by a gate insulating film 4. 5 is an interlayer insulating film, and 6 is a p-type region, which is a second control gate. Source electrode 22 is electrically connected to p-type region 6 and source region 2. If the impurity concentration of the p-type region is high, the build-in depletion layer is mostly developed in the n-type drain region, and the channel region (between two types of gates) is interfered with the depletion layer in which the gate electrode develops even outside the above limits. Drain region) can be electrically cut off.

Further, as shown in FIG. 5B, the control gate is connected to another terminal 66.
To apply a negative fixed potential.

FIG. 5 (c) shows a method of forming the control gate.
The most common method is to selectively ion-implant and diffuse p-type impurities between the insulating gates by a photo process to form the structure shown in FIG. 5 (a). In Fig. 5, 10
0 indicates a resist, and 600 indicates a region into which p-type impurities have been ion-implanted. As another method, a groove is formed in a specific region between the first insulated gates as shown in FIG. 5D by using a photo process, and a p-type impurity is diffused inside the groove. There is also. Alternatively, a method in which a metal is buried as it is to form a Schottky junction can be considered.

(Problems to be Solved by the Invention) However, the above method has problems in the following two points. Firstly, if the alignment of the photomask for forming the second control gate (hereinafter, referred to as “second gate”) is misaligned due to a problem relating to the alignment accuracy of the photo process,
The threshold values of the left and right channels sandwiching the second gate differ. This is not desirable in terms of device characteristics.

Second, there is a problem in miniaturizing a pattern in order to increase the current capacity of the device. In view of the first problem, the size of the channel region is set to 5 times the alignment accuracy of the photo device.
It needs to be set to about 10 times. This is unavoidable if a photo process is used to form the second gate. For example, assuming that a photo device having a minimum formable pattern size of 3 μm and an alignment accuracy of 0.5 μm is used, the minimum unit size of the device structure is about 6 to 8 μm, which limits the pattern reduction.

The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a semiconductor device which realizes appropriate miniaturization.

[Configuration of the invention]

(Means for Solving the Problems) The present invention has been made to solve such a problem. After forming an insulated gate for driving, the semiconductor substrate surface is etched to partially expose the side wall of the gate. This is a manufacturing method in which a so-called side wall made of an insulating film or a polycrystalline semiconductor film is formed on an exposed side wall, and the semiconductor substrate is vertically etched using the side wall as a mask, and thereafter various control gates are formed.

(Operation) According to the above method, the distance between the insulating gate and the control gate is extremely short, and a device structure with almost no variation can be formed. The thickness of the channel is controlled by the thickness of the film deposited before forming the sidewall. The practical value of the deposited film thickness is about 500 ° to 1 μm. The width of the channel to be formed is also in this range. However, even when the impurity concentration of the drain region is low, the channel width is not inconvenient because the channel width is small. Therefore, this method is used even when the upper limit of the channel width H is large. Can adapt.

Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.

First, as shown in FIG. 1A, a U-shaped insulated gate 4 is formed on the surface of an n ⁻ type semiconductor substrate 1.

Next, as shown in FIG. 1 (b), the semiconductor surface is etched by 5 to 6000 mm, a part of the side wall of the U-shaped insulated gate 4 is exposed, and a mask material, for example, a 5000 mm PSG film is deposited on the blanket.

When this PSG film is etched by reactive ion etching or the like, PSG remains only on the exposed side walls of the U-shaped gate as shown in FIG. 1C (number 200 in the figure).

If some heat treatment is performed at this stage, the high-concentration impurity of PSG diffuses into the semiconductor substrate in contact with it, and a source region can be formed. Of course, the PSG can be replaced with another mask material, and the source region can be formed in another step.

When the substrate is dug using the sidewalls as a mask, the result is as shown in FIG. 1 (d).

The simplest method of realizing the control gate is to bury a metal for Schottky connection with the drain region in this groove as shown in FIG. In this case, the width of the channel is 5000Å, and according to the above equation,
N _D can be increased up to a concentration of approximately 1 × 10 ¹⁶ cm ^-3.

Assuming that the minimum value of the pattern in this structure is realized by a photo device having a minimum formable pattern size of 3 μm and an alignment accuracy of 0.5 μm as in the above-described example, the photo process has the same relationship as when forming the drive gate. In addition, since the second gate is formed by the self-align method, the first insulating gate can be formed with the minimum pattern. Therefore, the minimum unit of the device structure is 3 μm.

FIG. 2 shows a second embodiment of the present invention. In the first embodiment, a p-type impurity region is formed inside the trench by vapor phase diffusion or the like before embedding metal in the trench, and then a control gate is formed. This is an example of embedding an electrode for use.

FIG. 3 shows a third embodiment of the present invention, in which a second insulating gate is formed in a groove. In this case, the mask material 200 is n
⁺ Polycrystalline silicon makes it easier to conduct the source.

〔The invention's effect〕

As described above, according to the present invention, after forming a driving insulated gate, the surface of the semiconductor substrate is etched to partially expose the side wall of the gate, and the so-called insulating film or polycrystalline semiconductor film is formed on the exposed side wall. Since side walls are formed, and the semiconductor substrate is vertically etched using the side walls as a mask, and thereafter various control gates are formed, the distance between the insulating gate and the control gate is extremely short, and most of the variation Device structure can be formed, and appropriate miniaturization can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 shows a second embodiment of the present invention, FIG. 3 shows a third embodiment of the present invention, FIG. 4 shows a first conventional example, and FIG. FIG. DESCRIPTION OF SYMBOLS 1 ... n ^- type drain region 2 ... n ⁺ source region 3 ... gate electrode 4 ... gate insulating film 5 ... interlayer insulating film 6 ... p-type impurity region 11 ... drain electrode 22 ... source electrode 66 ... Gate electrode for control gate 100... Resist 200... Mask material 204... Gate insulating film of second insulating gate 600.

Claims (5)

(57) [Claims] A step of burying an insulated gate electrode facing one main surface of a semiconductor substrate of a first conductivity type; and a step of etching a surface of the semiconductor substrate to expose a part of a side wall of the insulated gate. Forming a mask material only on the exposed side walls of the insulated gate, and forming a groove by substantially vertically etching the surface of the semiconductor substrate using the insulated gate and the mask material as a mask. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a semiconductor region of a second conductivity type on an inner wall of said groove. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of burying a metal capable of forming a Schottky junction with said semiconductor substrate in said groove. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a second insulating gate in said trench. 5. A semiconductor substrate in which an insulating film or a polycrystalline semiconductor or an amorphous semiconductor containing impurities of the same conductivity type as the semiconductor substrate is used as the mask material, and the semiconductor substrate comes into contact with the mask material by impurity diffusion from the mask material. (1) to (4), including a step of forming a high-concentration impurity region in a portion of (1).
The manufacturing method of the semiconductor device described in the above.