JPS63151083A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPS63151083A JPS63151083A JP61297712A JP29771286A JPS63151083A JP S63151083 A JPS63151083 A JP S63151083A JP 61297712 A JP61297712 A JP 61297712A JP 29771286 A JP29771286 A JP 29771286A JP S63151083 A JPS63151083 A JP S63151083A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor device
- film semiconductor
- gate wiring
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 8
- 239000010453 quartz Substances 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 14
- 230000001681 protective effect Effects 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- -1 phosphorus ions Chemical class 0.000 abstract description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は，液晶ディスプレイ装置駆動用に用いて好適な
薄膜半導体装置に係り，特に、オフ特性を改善した薄膜
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film semiconductor device suitable for use in driving a liquid crystal display device, and more particularly to a thin film semiconductor device with improved off-characteristics.
透明絶縁基板上に形成されたＭＣ）Ｓ型薄膜トランジス
タは，液晶ディスプレイ装置駆動用として重要である。MC) S-type thin film transistors formed on transparent insulating substrates are important for driving liquid crystal display devices.
この種技術に関する従来技術として、例えば、特開昭５
８−１７１８６０号公報等に記載された技術が知られて
おり，また、応用例として，日本学術振興会，アモルフ
ァス材料１４７委員会、第７回研究会資料，第２４頁〜
第２９頁（昭和６０年３月１９日）に記載された技術が
知られている。As a prior art related to this type of technology, for example, Japanese Patent Application Laid-open No. 5
The technology described in Publication No. 8-171860 is known, and as an application example, the Japan Society for the Promotion of Science, Amorphous Materials 147 Committee, 7th Research Group Materials, pp. 24-
The technique described on page 29 (March 19, 1985) is known.
このような従来技術による薄膜半導体装置の構成を図面
により説明する。The structure of such a thin film semiconductor device according to the prior art will be explained with reference to the drawings.
第５図１ａｌは従来技術による薄膜半導体装置の平面図
，第５図１ａｌはそのＨ−｝１’断面図である。第５図
１ａｌ， （ｂｌにおいて、１は石英基板，２は多結晶
７リコン、３はゲート酸化膜、４はゲート配線、５は保
護膜、６は透明電極、７は信号配線である。FIG. 5 1al is a plan view of a thin film semiconductor device according to the prior art, and FIG. 5 1al is a sectional view taken along line H-}1'. In FIGS. 5A and 5B, 1 is a quartz substrate, 2 is a polycrystalline silicon, 3 is a gate oxide film, 4 is a gate wiring, 5 is a protective film, 6 is a transparent electrode, and 7 is a signal wiring.
従来技術による薄膜半導体装置は、石英基板１上に直交
するように交叉して配置されるそれぞれ複数本の信号配
線７とゲート電極を兼ねるゲート配線４の交叉部分に複
数個直列接続したＭＯＳＦＥＴ等の薄膜半導体素子を設
けて構成されろ。また。A thin film semiconductor device according to the prior art includes a plurality of MOSFETs and the like connected in series at the intersections of a plurality of signal lines 7 and a gate line 4 which also serves as a gate electrode, which are arranged orthogonally on a quartz substrate 1. It is configured by providing a thin film semiconductor element. Also.
信号配線７とゲート配線４に囲まれた部分には、前記Ｍ
Ｏ８ＦＥＴのソースＳ（またはドレインＤ）に接続され
た液晶ディスプレイ装置の画素となる透明電極６が構成
される。そして、この薄膜半導体装置は、次のようにし
て製造される。In the part surrounded by the signal wiring 7 and the gate wiring 4, the M
A transparent electrode 6, which becomes a pixel of a liquid crystal display device, is connected to the source S (or drain D) of the O8FET. This thin film semiconductor device is manufactured as follows.
（１１石英基板ｌ上に薄膜半導体素子を構成する多結晶
シリコン２を形成し、島状に加工した後、ゲート酸化＠
３を形成する。(11 After forming polycrystalline silicon 2 constituting a thin film semiconductor element on a quartz substrate l and processing it into an island shape, gate oxidation@
form 3.
（２） このゲート酸化膜３の上にゲート電極を兼ね
るゲート配線４を形成する。このゲート配線４によるゲ
ート電極は、第５図（ａｌ、 （ｂｌに示す例では。(2) A gate wiring 4 which also serves as a gate electrode is formed on this gate oxide film 3. The gate electrode formed by this gate wiring 4 is as shown in FIGS.
２分割して形成される。It is formed by dividing into two parts.
（３） 島状に加工した多結晶シリコン２に、リンの
イオン注入を行い、ゲート配線４により形成されるゲー
ト電極の下部以外の部分にｎ＋領領域形成する。(3) Phosphorus ions are implanted into the polycrystalline silicon 2 processed into an island shape to form an n+ region in a portion other than the lower part of the gate electrode formed by the gate wiring 4.
（４）次に、この上に保護膜５を形成後、コンタクトホ
ールな開け、ソースＳとドレインＤを形成し、ソースＳ
ＩＣ画素用の透明電極６を、ドレインＤに接続した信号
配線７を形成する。(4) Next, after forming a protective film 5 on this, a contact hole is opened, a source S and a drain D are formed, and a source S
A signal wiring 7 in which a transparent electrode 6 for an IC pixel is connected to a drain D is formed.
前述のように形成された薄膜半導体装置は、等制約に２
個のＭＯ３ＦＥＴが直列に接続された構造を有すること
になり、ソースＳとドレインＤとの間に所定の電圧を印
加した場合、この電圧は２個のＭＯ８ＦＥＴＫ分担され
て印加されることとなる。このため、２個の素子サイズ
が同じ場合個別のＭＯ８Ｆｆ！、Ｔに印加される電圧は
、第５図のソースＳとドレインＤとの間に印加される電
圧の１／２となり、ゲート電極の電圧が負となって、Ｍ
ＯＳＦＥＴがオフ状態となった場合における接合のリー
ク電流が低減されることになる。これにより、ＭＯ８Ｆ
ＥＴ素子のオン、オフ電流比が増大し、特性の優れたも
のとなる。この効果は、ゲート電極の分割数が多くなる
ほど、大きくなるが。The thin film semiconductor device formed as described above is
It has a structure in which two MO3FETs are connected in series, and when a predetermined voltage is applied between the source S and the drain D, this voltage is divided and applied to the two MO8FETK. Therefore, if two elements have the same size, individual MO8Ff! , T becomes 1/2 of the voltage applied between the source S and drain D in FIG.
The leakage current of the junction when the OSFET is in the off state is reduced. As a result, MO8F
The on/off current ratio of the ET element increases, resulting in excellent characteristics. This effect becomes larger as the number of divisions of the gate electrode increases.
こうすると、素子自体の専有面積が大きくなり。This increases the area occupied by the element itself.
液晶ディスプレイ装置の画素として働く透明電極６の有
効面積が小さくなる。The effective area of the transparent electrode 6 serving as a pixel of the liquid crystal display device becomes smaller.
前述した従来技術は１Ｍ０８ＦＥＴのオン、オフ電流比
を大きくして高性能化しようとすると、ＭＯ８ＦＨＴ自
体が大きくなってしまい１画素となる透明電極６の有効
面積を低減させてしまうという問題点があった。The above-mentioned conventional technology has a problem in that when attempting to improve the performance by increasing the on/off current ratio of the 1M08FET, the MO8FHT itself becomes large and the effective area of the transparent electrode 6 that forms one pixel is reduced. Ta.
本発明の目的は、画素の有効面積を低減させることなく
、オン、オフ電流比を大きくした高性能なＭＯＳＦＥＴ
を構成でき、液晶ディスプレイ装置の駆動用に用いて好
適な薄膜半導体装置を提供することにある。An object of the present invention is to provide a high-performance MOSFET that increases the on/off current ratio without reducing the effective area of the pixel.
It is an object of the present invention to provide a thin film semiconductor device which can be configured and is suitable for use in driving a liquid crystal display device.
本発明によれば、前記目的は、ＭＯＳＦＥＴ等の薄膜電
界効果素子を構成する多結晶７リコン領域を蛇行させて
ゲート配線の下に配置し、さらにその一部を信号配線の
下に配置することにより達成することができる。According to the present invention, the object is to meander a polycrystalline 7-recon region constituting a thin film field effect device such as a MOSFET and arrange it under a gate wiring, and further to arrange a part of it under a signal wiring. This can be achieved by
ＭＯＳＦＥＴ等の薄膜電界効果素子をゲート配線および
信号配線の下に配置することにより、画素となる領域に
占める素子の占有面積を小さくすることができ、これに
より１画素の有効面積を減少させなくて済み、また、素
子を構成する多結晶シリコン層を蛇行させることにより
、容易に素子数を増加させることができ、オン、オフ比
の大きい高性能な薄膜半導体装置を構成することができ
る。By placing a thin film field effect element such as a MOSFET under the gate wiring and signal wiring, it is possible to reduce the area occupied by the element in the area that becomes the pixel, and thereby the effective area of one pixel is not reduced. Moreover, by meandering the polycrystalline silicon layer constituting the device, the number of devices can be easily increased, and a high-performance thin film semiconductor device with a high on/off ratio can be constructed.
以下１本発明による薄膜半導体装置の実施例を図面によ
り詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thin film semiconductor device according to the present invention will be described below in detail with reference to the drawings.
第１図は本発明の第１の実施例を示すもので、第１図（
ａ）はその平面図、第１図（ｂ）はＡ −Ａ／断面図。FIG. 1 shows a first embodiment of the present invention.
a) is a plan view thereof, and FIG. 1(b) is an A-A/sectional view.
第１図１ａｌはＨ−Ｂ／断面図であり、図の符号は第５
図に示す従来技術の場合と同一である。Figure 1 1al is a cross-sectional view taken along line H-B, and the reference numerals in the figure are number 5.
This is the same as the case of the prior art shown in the figure.
第１図１ａｌ 、 Ｉｂｌ 、 Ｉｃｌに示す本発明の
第１の実施例は、多結晶クリコン層２がぼぼコ字状に蛇
行して。In the first embodiment of the present invention shown in FIG. 1, 1al, Ibl, and Icl, the polycrystalline crystal layer 2 is meandering in a U-shape.
直線状のゲート配線４の下層に配置されて構成されてお
り１次のような製造工程により作成される。It is arranged under the linear gate wiring 4 and is created by a first-order manufacturing process.
（１）石英基板１等の透明絶縁基板上に多結晶シリコン
層２を形成し、これを第１図１ａｌに示すようにほぼコ
字型に加工した後、ゲート酸化膜３を形成する。(1) A polycrystalline silicon layer 2 is formed on a transparent insulating substrate such as a quartz substrate 1, and after processing this into a substantially U-shape as shown in FIG. 1, la, a gate oxide film 3 is formed.
（２） このゲート酸化膜３の上に直線状のゲート電
極であるゲート配線４を形成する。この場合、ゲート配
線４と多結晶シリコン層２とがゲート酸化膜３を介して
重なる部分のゲート配線４が２個のゲート電極となる。(2) On this gate oxide film 3, a gate wiring 4, which is a linear gate electrode, is formed. In this case, the portion of the gate wiring 4 where the gate wiring 4 and the polycrystalline silicon layer 2 overlap with the gate oxide film 3 interposed therebetween becomes two gate electrodes.
（３）以後、従来技術と同様に、多結晶シリコン層２に
リンのイオン注入を行い、保護膜５を形成した後、コン
タクトホールを開け、ソースＳとドレインＤを形成し、
透明電極６と信号配線７を形成する。(3) Thereafter, as in the conventional technique, phosphorus ions are implanted into the polycrystalline silicon layer 2, a protective film 5 is formed, a contact hole is opened, a source S and a drain D are formed,
A transparent electrode 6 and signal wiring 7 are formed.
第１図１ａｌ −１ｂ） ｖ ｌｃ）に示された構造の
薄膜電界効果素子であるＭＯ８Ｆ’ＥＴは、ゲート配線
の下層に構成され、ゲート配線の下層を素子形成領域と
して活用している。このため、この素子が占める占有面
積を低減することができる。また、この実施例は、薄膜
半導体装置を構成している多結晶シリコン層２をコ字状
に蛇行させて、２個の直列接続されたＭＯＳＦＥＴを形
成しているので、形成されたＭＯＳＦＥＴは、オン／オ
フ電流比の高い高性能なものとなる。The MO8F'ET, which is a thin film field effect element having the structure shown in FIG. 1 (al-1b) v lc), is constructed below the gate wiring, and utilizes the lower layer of the gate wiring as an element formation region. Therefore, the area occupied by this element can be reduced. In addition, in this embodiment, the polycrystalline silicon layer 2 constituting the thin film semiconductor device is meandered in a U-shape to form two MOSFETs connected in series. This results in high performance with a high on/off current ratio.
第２図は本発明の第２の実施例を示すもので。FIG. 2 shows a second embodiment of the invention.
第２図１ａｌはその平面図、第２図１ｂｌはＣ−Ｃ／断
面図。FIG. 2 1al is a plan view thereof, and FIG. 2 1bl is a CC/sectional view thereof.
第２図１ｃＩはＬ）−Ｄ’断面図であり、図の符号は、
第５図、第１図で説明した場合と同一である。FIG. 2 1cI is a cross-sectional view along line L)-D', and the symbols in the figure are as follows:
This is the same as the case explained in FIGS. 5 and 1.
第２図に示す本発明の第２の実施例は、第１図により説
明した第１の実施例と同様に、多結晶７リコン層２がコ
字状に形成され、同様なプロセスに従って形成される。In the second embodiment of the present invention shown in FIG. 2, the polycrystalline silicon layer 2 is formed in a U-shape, similar to the first embodiment described in FIG. 1, and is formed according to a similar process. Ru.
この実施例の場合、多結晶シリコン層２の一部が信号配
線７の下層に配置されるように構成される。このため、
この実施例におけるＭＯＳＦＥＴは、そのほとんどが信
号配線７とゲート配線４の下層に配置されることになり
、液晶ディスプレイ装置の画素となる透明電極６０面積
は最大となる。In this embodiment, a portion of the polycrystalline silicon layer 2 is arranged under the signal wiring 7. For this reason,
Most of the MOSFETs in this embodiment are arranged below the signal line 7 and gate line 4, and the area of the transparent electrode 60, which becomes the pixel of the liquid crystal display device, is maximized.
第３図は本発明の第３の実施例を示すもので。FIG. 3 shows a third embodiment of the present invention.
第３図（ａｌはその平面図、第３図１ｂｌはＢ −Ｅ／
断面図、第３図１ｅｔはＦ −Ｆ／断面図であり１図の
符号は、第１、第２の実施例で説明した場合と同一であ
る。Figure 3 (al is the plan view, Figure 3 1bl is B-E/
The sectional view, FIG. 3, et is a FF/sectional view, and the reference numerals in FIG. 1 are the same as those described in the first and second embodiments.
第３図に示す本発明の第３の実施例は、第１図により説
明した第１の実施例とほとんど同様にして形成される。A third embodiment of the invention, shown in FIG. 3, is formed in much the same way as the first embodiment described in FIG.
この第３の実施例が第１の実施例と相違する点は、ゲー
ト配線４のゲート電極となる部分が、ソース、ドレイン
方向に２分割されている点である。これにより第３図に
示す第３の実施例は、短チャンネル化した４個のＭＯＳ
ＦＥＴが直列接続された構成を実現しており、薄膜半導
体装置を、オン／オフ電流比流比のさらに高い高性能な
ものとしている。The third embodiment differs from the first embodiment in that the portion of the gate wiring 4 that becomes the gate electrode is divided into two parts in the source and drain directions. As a result, the third embodiment shown in FIG. 3 consists of four short-channel MOS
A configuration in which FETs are connected in series is realized, and the thin film semiconductor device has a higher performance with an even higher on/off current ratio.
第４図は本発明の第４の実施例を示すもので。FIG. 4 shows a fourth embodiment of the present invention.
第１図１ａｌはその平面図、第２図１ｂｌはＧ−Ｇ’断
面図であり、図の符号は、他の実施例の場合と同一であ
る。FIG. 1 1al is a plan view thereof, and FIG. 2 1bl is a sectional view taken along line GG', and the reference numerals in the figures are the same as in the other embodiments.
第４図に示す本発明の実施例は、ＭＯＳＦＥＴを構成す
る多結晶シリコン層２を複数のコ字状のパターンを組合
わせて蛇行を繰返すように、ゲート配線４の下層に形成
して、３個のＭＯＳＦＥＴの直列回路を構成したもので
あり、他の実施例と同様な効果を奏するものである。In the embodiment of the present invention shown in FIG. 4, a polycrystalline silicon layer 2 constituting a MOSFET is formed under a gate wiring 4 so as to repeatedly meander by combining a plurality of U-shaped patterns. This is a series circuit of two MOSFETs, and has the same effects as the other embodiments.
前述した本発明の実施例において、石英基板の代りに、
ガラス基板、半導体上に絶縁膜を設けた基板等を利用す
ることができ、また、ＭＯ８Ｆ’ＥＴ’ｋ ！４成する
多結晶クリコン層の代りとして、単結晶シリコン層、非
晶質シリコン層、シリコン以外のｅｄｇｅ等の化合物半
導体層等を用いることができる。さらに、ゲート配線、
信号配線の材料として、多結晶シリコン、アルミ等の金
属を利用することが可能である。In the embodiment of the present invention described above, instead of the quartz substrate,
A glass substrate, a substrate with an insulating film provided on a semiconductor, etc. can be used, and MO8F'ET'k! Instead of the four-layer polycrystalline silicon layer, a single crystal silicon layer, an amorphous silicon layer, a compound semiconductor layer other than silicon such as an edge layer, etc. can be used. Furthermore, gate wiring,
Polycrystalline silicon, metals such as aluminum can be used as materials for the signal wiring.
以上説明したように、本発明によれば、ゲート配線、信
号配線等の下層に複数個を直列接続したＭＯＳＦＥＴに
よる薄膜半導体装置を構成することができ、これらの配
線外における薄膜半導体装置が占める占有面積を低減し
た、しかも装置のオン／オフ電流比の高い高性能な、液
晶ディスプレィ装置の駆動用として用いて好適な薄膜半
導体装置を提供することができる。As explained above, according to the present invention, it is possible to configure a thin film semiconductor device using MOSFETs in which a plurality of MOSFETs are connected in series in a lower layer such as a gate wiring, a signal wiring, etc., and occupy space occupied by the thin film semiconductor device outside these wirings. It is possible to provide a thin film semiconductor device suitable for use in driving a liquid crystal display device, which has a reduced area and has a high performance with a high on/off current ratio.
第３図１ａｌは本発明の第１の実施例の平面図、第１図
１ｂ） 、 ｌｃｌはその断面図、第２図１ａ）は本発
明の第２の実施例の平面図、第２図１ｂｌ、 Ｉｃ）は
その断面図。
第３図１ａｌは本発明の第３の実施例の平面図、第２図
１ｂｌ ＋Ｃ）はその断面図、第４図１３）は本発明の
第４の実施例の平面図、第４図１ｂｌはその断面図、第
５図１ａｌは従来技術の一例の平面図、第２図１ｂｌは
その断面図である。
ｌ・・・・・・石英基板、２・・・・・・多結晶シリコ
ン層、３・・・・・・ゲート酸化膜、４・・・・・・ゲ
ート配線、５・・・・・・保藤膜、６・・・・・・透明
電極、７・・・・・・信号配線。
第４図
（Ｇ）
（ｂ）FIG. 3 1al is a plan view of the first embodiment of the present invention, FIG. 1 1b), lcl is a sectional view thereof, and FIG. 2 1a) is a plan view of the second embodiment of the present invention, FIG. 1bl, Ic) is its cross-sectional view. FIG. 3 1al is a plan view of the third embodiment of the present invention, FIG. 2 1bl +C) is a sectional view thereof, and FIG. 4 13) is a plan view of the fourth embodiment of the present invention. 5 is a sectional view thereof, FIG. 5 1al is a plan view of an example of the prior art, and FIG. 2 1bl is a sectional view thereof. l...Quartz substrate, 2...Polycrystalline silicon layer, 3...Gate oxide film, 4...Gate wiring, 5... Hoto film, 6...Transparent electrode, 7...Signal wiring. Figure 4 (G) (b)
Claims (1)
直列に接続してなる薄膜半導体装置において、前記直列
に接続された薄膜電界効果素子の一部または全部が、薄
膜半導体装置間を接続するゲート配線またはソース（ま
たはドレイン）に接続された信号配線の下層に配置され
ていることを特徴とする薄膜半導体装置。 ２、前記絶縁基板が石英、ガラス等の透明基板であり、
前記薄膜半導体装置を構成する半導体材料が多結晶シリ
コン、非晶質シリコンまたは単結晶シリコンであること
を特徴とする前記特許請求の範囲第１項記載の薄膜半導
体装置。 ３、前記直列に接続された電界効果素子がゲート配線の
下層に、蛇行して配置されていることを特徴とする前記
特許請求の範囲第１項または第２項記載の薄膜半導体装
置。[Scope of Claims] 1. In a thin film semiconductor device formed by connecting a plurality of thin film field effect elements formed on an insulating substrate in series, some or all of the thin film field effect elements connected in series: A thin film semiconductor device characterized in that it is disposed below a gate wiring that connects thin film semiconductor devices or a signal wiring connected to a source (or drain). 2. The insulating substrate is a transparent substrate such as quartz or glass;
2. The thin film semiconductor device according to claim 1, wherein the semiconductor material constituting the thin film semiconductor device is polycrystalline silicon, amorphous silicon, or single crystal silicon. 3. The thin film semiconductor device according to claim 1 or 2, wherein the field effect elements connected in series are arranged in a meandering manner under a gate wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61297712A JPS63151083A (en) | 1986-12-16 | 1986-12-16 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61297712A JPS63151083A (en) | 1986-12-16 | 1986-12-16 | Thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63151083A true JPS63151083A (en) | 1988-06-23 |
Family
ID=17850188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61297712A Pending JPS63151083A (en) | 1986-12-16 | 1986-12-16 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63151083A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02189522A (en) * | 1989-01-18 | 1990-07-25 | Sharp Corp | Display electrode substrate |
| US5097297A (en) * | 1988-03-18 | 1992-03-17 | Seiko Epson Corporation | Thin film transistor |
| US5105246A (en) * | 1990-08-10 | 1992-04-14 | Xerox Corporation | Leaky low voltage thin film transistor |
| JPH0627484A (en) * | 1991-03-15 | 1994-02-04 | Semiconductor Energy Lab Co Ltd | Liquid crystal electro-optical device |
| US5289027A (en) * | 1988-12-09 | 1994-02-22 | Hughes Aircraft Company | Ultrathin submicron MOSFET with intrinsic channel |
| JP2001102595A (en) * | 1999-09-30 | 2001-04-13 | Sanyo Electric Co Ltd | Thin film transistor and display |
| US6259117B1 (en) | 1994-06-02 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display having storage capacitor associated with each pixel transistor |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| US6914642B2 (en) | 1995-02-15 | 2005-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| KR100520244B1 (en) * | 1996-05-08 | 2006-01-12 | 샤프 가부시키가이샤 | Thin-film transistor and liquid crystal display device having said thin-film transistors |
| JP2006173600A (en) * | 1995-01-03 | 2006-06-29 | Xerox Corp | Product |
| JP2021005554A (en) * | 2001-11-09 | 2021-01-14 | 株式会社半導体エネルギー研究所 | Light-emitting device |
-
1986
- 1986-12-16 JP JP61297712A patent/JPS63151083A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5097297A (en) * | 1988-03-18 | 1992-03-17 | Seiko Epson Corporation | Thin film transistor |
| US5289027A (en) * | 1988-12-09 | 1994-02-22 | Hughes Aircraft Company | Ultrathin submicron MOSFET with intrinsic channel |
| JPH02189522A (en) * | 1989-01-18 | 1990-07-25 | Sharp Corp | Display electrode substrate |
| US5105246A (en) * | 1990-08-10 | 1992-04-14 | Xerox Corporation | Leaky low voltage thin film transistor |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| JPH0627484A (en) * | 1991-03-15 | 1994-02-04 | Semiconductor Energy Lab Co Ltd | Liquid crystal electro-optical device |
| US6236064B1 (en) | 1991-03-15 | 2001-05-22 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| US7148506B2 (en) | 1994-06-02 | 2006-12-12 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and electrooptical device |
| US6297518B1 (en) | 1994-06-02 | 2001-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and electrooptical device |
| US6495858B1 (en) * | 1994-06-02 | 2002-12-17 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having thin film transistors |
| US6259117B1 (en) | 1994-06-02 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display having storage capacitor associated with each pixel transistor |
| US6885027B2 (en) | 1994-06-02 | 2005-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and electrooptical device |
| US7459724B2 (en) | 1994-06-02 | 2008-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and electrooptical device |
| JP2006173600A (en) * | 1995-01-03 | 2006-06-29 | Xerox Corp | Product |
| JP2010153912A (en) * | 1995-01-03 | 2010-07-08 | Xerox Corp | Array and product |
| JP4648829B2 (en) * | 1995-01-03 | 2011-03-09 | ゼロックス コーポレイション | Product |
| US6914642B2 (en) | 1995-02-15 | 2005-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| KR100520244B1 (en) * | 1996-05-08 | 2006-01-12 | 샤프 가부시키가이샤 | Thin-film transistor and liquid crystal display device having said thin-film transistors |
| JP2001102595A (en) * | 1999-09-30 | 2001-04-13 | Sanyo Electric Co Ltd | Thin film transistor and display |
| JP2021005554A (en) * | 2001-11-09 | 2021-01-14 | 株式会社半導体エネルギー研究所 | Light-emitting device |
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