JPH0492473A - Manufacture of vertical channel insulated gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To provide an ultrahigh density by providing a rectangular protrusion- like region, and forming one or two sides of this region as channel forming regions. CONSTITUTION:A rectangular protrusion-like region 35 formed as seen from above is formed of a first photomask (1) on a semiconductor substrate. It may be formed by anisotropically etching a silicon single crystalline substrate. It is important that its corner is formed with an extremely acutely vertical surface at 90 deg. to the upper surface of the substrate. The height of the region 35 is 0.5-4mum such as 1.5mum. Then, the region 35 becomes in plane (100) at a channel forming region, and in plane (010) at a parasitic channel preventive surface. Al the sides can be reduced in stationary charge density to about 1/2 as compared with other crystal surfaces in planes (110, 111).

Description

Detailed Description of the Invention "Industrial Application Field J The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device for a semiconductor integrated circuit, particularly a 16M to 16G human level ultra-high density integrated circuit (referred to as LILSI). related to providing.

The present invention relates to a semiconductor device, particularly a vertical channel MIS type (insulated gate type) field effect semiconductor device (FET) having a microchannel type in which current flows in the vertical direction, and a channel length of 0.03 μm to 1 μm or less. This is why it is called a μ channel MIS FET).
The purpose of the present invention is to propose a method for manufacturing a composite semiconductor device by applying a self-alignment process and, for example, connecting a capacitor to the process.

In the present invention, a rectangular convex region is formed by anisotropic etching, and impurities are added to the sides of the convex region obliquely or laterally by, for example, ion implantation, and the channel forming region is formed. The present invention relates to a method of manufacturing a pair of impurity regions forming a source or drain and a train or source using a gate electrode as a mask.

The present invention further relates to a manufacturing method for controlling a threshold voltage in a channel formation region before manufacturing this gate electrode.

The present invention further relates to a method for manufacturing a vertical channel MIS FET in which the generation of parasitic channels on the side surfaces of other convex regions is prevented before or after the gate electrode is manufactured.

``Prior Art'' Conventionally, the structure of a manufacturing method for a MisFET or a capacitor connected in series thereto is as shown in FIG.
1) - On the surface, gate insulator (2).

Gate electrode (18) and source or toluin (4)
.

Formation while forming a self-line configuration in which impurities are doped by vertical ion implantation from above using the drain or source (5) as a mask with the gate electrode (18);
It was formed as a so-called LDD (a drain with a relatively low impurity concentration, that is, a lightly doped train). A rectangular or triangular portion (38), (38') of insulator is formed around the side of this gate electrode (18), and using this end as a mask, a first impurity with a high impurity concentration is formed on the outside. A region (15) and a second impurity region (14) were formed two-dimensionally to constitute a Mis FET (10). Further, connected to this first impurity region (15), a lower electrode (2+), a dielectric (22), and an upper electrode (23) were provided as a capacitor (20). Like this, MIS F
The ET (10) and the capacitor (20) were formed on the same plane on a semiconductor substrate. and lTr/Ce1l
In the case of (a memory in which one MisFET and one capacitor are connected in series to form one bit), the cell area becomes large due to this planar configuration, and there is a limit to high-density integration.

Furthermore, on the left and right sides of the gate electrode (18), there are LDDs (4),
As an auxiliary means for making (5), rectangular or triangular portions (38), (38°) are constructed of an insulating material.

The present invention relates to a method for manufacturing a structure in which this rectangular or triangular portion is not provided as an insulator but as a conductor or semiconductor gate electrode itself.

"Objective of the Present Invention" In the present invention, a rectangular convex region is provided, and one or two side surfaces of this region are used as channel forming regions. That is, the current is made to flow in the vertical direction, and the channel length is 0.03
In addition to extremely small size of ~1μm, one Mis
By reducing the size of the FET to about 1 μm to 10 μm, it is possible to make up to 16M to 16G bits (to provide an element structure for J[, Sr. Furthermore, by compounding this MisPET, inverter structure,
Another object of the present invention is to provide a memory cell structure that is connected to other elements such as capacitors.

"Structure of the Invention" In the present invention, a rectangular convex region is provided on a single crystal semiconductor substrate. This convex (100) plane or its vicinity ((
100) plane or its vicinity, i.e. ±2 from the (100) plane
The four side surfaces with a 0'20' deviation (hereinafter simply referred to as (100) plane) are simultaneously treated as (100) planes, two of these side surfaces are used as channel forming regions, and a current is passed in the vertical direction, that is, a vertical channel is formed. It was made into a mold.

In the present invention, the source and drain of the MIS FET are formed laterally in order to facilitate electrode formation in subsequent steps, thereby providing an asymmetrical MlsFET. That is, a rectangular convex single-crystal semiconductor region is provided on the entire surface of a semiconductor substrate. Using the rectangular or triangular gate electrode formed in this convex region as a mask, the end of the gate electrode is connected to the source or drain and the end of the drain or source (channel forming region) using the self-alignment method. This was used as the manufacturing standard for the contacting parts). That is, one source or drain of the MIS FET is formed on the upper part, the lower side of the gate electrode of this convex region is used as a vertical channel formation region, and the drain or source is formed on the bottom of the semiconductor substrate. Create. The source or drain and the drain or source are doped obliquely or laterally by, for example, an ion implantation method, while keeping the impurity concentration at 3×10 17 to 5×102102 O′. Then, the region with higher concentration of impurities is not at the diagonal surface of the convex region or at the bottom of the semiconductor substrate, but at the deeper inside of the semiconductor. As a result, injection of hot carriers into the gate insulator can be prevented.

It has a source or droop-in end that roughly coincides with the upper end of the gate electrode, and the inside thereof is further extended slightly toward the channel formation region to prevent the gate electrode from having an offset structure and to facilitate manufacturing. Give yourself some leeway (margin).

By doping impurities laterally or obliquely into this rectangular convex region using, for example, ion implantation, the threshold voltage of the channel formation region is controlled and a recessed channel is formed. .

This impurity concentration varies depending on the interface state density, but in an N-channel MIS FET, the threshold voltage is ±
It should be within IV and 100, 1 to + to be normally off.
Set it to 1.0■, and set it to normally on by 10, 1 to -.
It was set to 1.0■. In P-channel MIS FBT, the sign is opposite.

On the side surfaces where no channels are formed, prevention of parasitic channels is carried out in the vertical direction to prevent minute leakage due to the occurrence of parasitic channels. To prevent this parasitic channel, in an N-channel MIS FET, the boron concentration is lower than the impurity concentration of the LDD source or drain-in, and the A concentration is higher than the impurity concentration of the substrate.

In general, it is 1 x 1016-2 x 10'' cm-3.

Source or Druin and Train or Source are
In order to make it easier to make ohmic contact between the second impurity region and the first impurity region with high impurity concentration, they are provided with a flat surface so that contact holes can be made finely and accurately. .

On the other hand, even if an attempt is made to form a contact hole on the side surface, the contact hole will have a diameter of 0.1 to 0.5 μm because the manufacturing process involves exposure to ultraviolet light for photoetching, or generally irradiation from the top to the bottom. is nearly impossible to form.

The present invention eliminates this drawback.

Therefore, in the semiconductor device of the present invention, high density for configuring LILSI is achieved not by reducing the area occupied on the substrate of the conventional lateral MIS FET by scaling, but by actively providing it in the height direction. It is an object.

Examples of the present invention will be described below according to the drawings.

“Example 1j The manufacturing process of this embodiment is shown in FIG.

Two vertical channel type N-channel type Mis FETs are provided as a pair (10) and (10') using a rectangular convex region (35) of a single crystal semiconductor substrate.

Figures 2 (A) to (D) show longitudinal cross-sectional views, and Figure 2 (
E) shows a plan view. The cross section taken along line AA in FIG. 2(E) corresponds to FIGS. 2(A) to (D).

A single crystal semiconductor substrate, for example a silicon single crystal semiconductor (10
0) surface, P type lO~500Ωcm was selected. A first photomask (■ to ■ indicates a photolithography process using a photomask) is applied to this semiconductor substrate to form a rectangular shape when viewed from above, as shown in FIGS. 2(A) and (E). A convex region (35) was formed. For its fabrication, anisotropic etching of a silicon single crystal substrate may be performed. It is important that this corner portion has a very sharp vertical surface at 90° with respect to the top surface of the substrate. The height of this convex region (35) was set to 0.5 to 4 μm, for example 1.5 μm.

Then, the convex region (35) having a rectangular shape is shown in Fig. 2 (E
), the channel forming region is aligned with the (100) plane (<
loo > direction (40)), and the parasitic channel prevention surface is also the (010) plane (<010> direction (40°)).

and the fixed charge density on all sides of the other (1
10), it can be reduced to about 1/2 compared to the (111) crystal plane.

Silicon nitride that has a masking effect against oxidizing gases (33)
was formed to a thickness of about 0.1 μm. The film having a masking effect against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride. Thereafter, as shown in FIG. 2(A), a portion of the silicon nitride was removed using a second photomask (■).

After doping this removed region with a P-type impurity for forming a channel cut, a field insulator (3) of 0.5~
It is buried to a thickness of 2 μm to obtain the state shown in FIG. 2(A).

As shown in FIG. 2(B), this silicon nitride film (33) is removed and a film (2) for forming a gate insulating film is formed on the semiconductor substrate (1) having the convex region (35). did.

Channel forming regions (6), (6') were formed on at least the side surfaces of the rectangular convex region by means such as ion implantation before or after forming the gate insulating film (2). That is, the channel forming regions (6) and (6') are used to control the threshold voltage since this example is for an N-channel type MisFET, and are normally off for an enhancement type MrS FET. +0.1～
+1. OV, for example +〇, 5Vi=, majko dabure・
This was achieved by controlling the dose amount for a normally-on MIS FET of -0,1 to -1, Ov, for example, -0,5. These were used as channel formation regions, and one or both of the channel formation regions (6) and (6”) were automatically formed using a photomask. Two or three types of impurities were added twice as a buried channel type. These may be added to (6) of the convex region (35).
), impurities were actively added to the (6°) side. For example, ion implantation from the side or diagonal direction (
38), (38') was doped with boron or boron and arsenic.

This rectangular convex region (35) is a region where no channel is formed ((36), (36' in FIG. 2(E))
)), parasitic channels are likely to occur, and the source or drain (4) and drain or source (5), (
In order to prevent a slight leakage current from occurring between the substrate and the convex region, boron was added at a higher concentration than the convex region, and the channel was cut so that the off state was constantly achieved. This was accomplished by performing ion implantation from an oblique or lateral direction.

These ion implantations damage not only the substrate but also the insulating film (33) or (2), so the whole is thermally or intensely annealed to remove the semiconductor substrate (1) and the convex region (35). It became a single crystal.

This ion implantation step may be performed in the step shown in FIG. 2(A) or in the step shown in FIG. 2(B).

This silicon oxide film (2) is removed and another insulating film, such as another silicon oxide, silicon nitride, tantalum oxide, or a composite film of these, is formed to a thickness of 100 to 500 nm to form a gate insulating film (
2) may also be used.

Next, as shown in FIG. 2(B), this gate insulating film (2)
A window for use as a source or drain electrode (contact) was formed using a third photomask (■). After sufficiently cleaning the surface of the insulating film, impurities of one conductivity type, such as N-type impurities (phosphorus), are deposited on the substrate using a low pressure vapor phase method (LPCVD method) at a concentration of 1 to 10 x 10 cm. Silicon semiconductor (silicon) film doped with (7)
was formed on the entire surface to form gate electrodes and other leads to a thickness of 0.5 to 2.5 μm. This impurity doping is not done at the same time as the film is formed, but after the film (7) is subjected to the next anisotropic etching process to leave the gate portions (8) and (8'), and then the film is doped using a diffusion method or The injection method may also be used.

This film (7) is not a silicon semiconductor doped with impurities, but may be a conductor such as a metal or an intermetallic compound. Furthermore, P or N+ type semiconductors and metals or metal compounds, especially Mo, W or their silicides (MoSi2.W
It may also be a multilayer film with Si□).

In this way, Figure 2 (B) was obtained.

Next, as shown in FIG. 2(C), a photoresist (for example, O
MR-83 (manufactured by Tokyo Ohka) (■) was selectively coated, and then anisotropic etching was performed. Regarding this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, rather than the conventional isotropic etching method using a solution. 2.45
A reactive gas for etching, such as nitrogen fluoride (NF), carbon fluoride (CF), is removed by microwave using GH2.
, ) is chemically activated, and the degree of vacuum is further reduced to 0.1.
-0.001torr especially 0.005~01O1torr
A fluorine shower made into plasma was flowed vertically from the top surface of the substrate in an atmosphere with a vacuum degree of 1.5 mm, and a bias was applied to the substrate to perform low-temperature etching to completely eliminate side etching.

As a result, when the planar part of the film (7) on which no photoresist is formed is completely removed, the convex region (3
Coating (8) on the side surface portion which is the corner portion of 5).

(8") has a vertical rectangular or triangular gate electrode (18) around the side because the effective thickness is thick when viewed from above.
, (18') remained. Further, the first impurity region (5), (5') of the drain or source (5')
Contact (11) (corresponding to (I5) in Figure 2 (D))
In this example, the lead (12) was of N+ type and could be left as an electrode lead. Gate electrode (1
8), (18°) does not exist over the upper surface of the convex region (35), and its width is not determined by photolithography, but depends on the thickness of the side surface of the coating (7) and the anisotropic etching. It can be determined by the degree.

All of these are then oxidized to form a silicon oxide insulating film (47).
the convex region, the bottom of the semiconductor substrate and the gate electrode (1
8), formed on the surface of (18') to a thickness of 300 to 2000.

Next is this rectangular or triangular gate electrode (18).

Using (18") as a mask, impurities are doped from an oblique direction as shown in (37) and (37°). When using the in-in implantation method, since it is an N-channel type, arsenic
0.5-5 x 10”c at 100KeV accelerating voltage
The convex region (35 ) has a source or drain (4), whose end (44") roughly coincides with the end (44) of the gate electrode, and whose inner part (44") is deeper than this end (44").
°°) is formed at a position closer to the drain or source when viewed from the channel formation region (6°). A source or drain (4) is thus formed.

On the other hand, the end (48°) of the drain or source (5') is approximately aligned with the end (48) of the other gate electrode (18").
) is formed deeper than that location (closer to the source or drain) inside the drain or source (
48”) is formed.

Thus, the source or drain (4), drain or source (5), (5'') is connected to the gate electrode (18), (
18''), its position is determined by self-alignment (self-alignment), and the positioning is particularly performed by ion implantation from an oblique direction.

The gate electrode (18') is extended as a lead (38°) as shown in FIG. 2(E), and the other gate electrode (18) is connected to the contact (11) through the lead (12). ing.

In FIG. 2(D), in order to create a region with high impurity concentration from above, first impurity regions (15), (15″),
A second impurity region (I4) may be formed to make ohmic contact. However, these impurity regions are sos or druiin (4), druiin or source (5).

When forming (5'), the accelerating voltage is varied, and a low dose is added at a high accelerating voltage, and a high dose is added at a strong accelerating voltage, for example, I
3 x 10"cm-' at °KeV, 2 at 30KeV
It can be formed all at once by doping with X 10"cm-".

In FIG. 2(C), the rectangular or almost triangular gate electrode (18) (18°) has a width of 0.1
Although the layer is as thin as ~Iμm, the layer can be used as a lead (38), (38”) on top of the field insulator depending on design needs.
), and the width of the lead is set as wide as 1 to 10 μm, and other Mis FETs provided on the same substrate are
Needless to say, it may be electrically connected to an electrode lead, or to other capacitors, resistors, etc.

The drawing shows selective growth of tungsten (24), (13)
and aluminum leads (24'), (12')
°), (38”) were formed and multilayer wiring was performed.

In Figures 2 (D) and (E), the inverter is connected to the power supply side (38"), load (10), output (24), (2
4”), driver (10’), ground side (12), (1
After this, an interlayer insulating film is formed on the entire surface, the exposed side is connected to the second impurity region (14), and a multilayer wiring is applied to the electrode (12'') to conduct the current. Just connect them.

The channel length as a MIS FET is the end (44) or (441) of the source or drain (4) and the end (48") or (48") of the drain or source (5), (5"). It can be determined by the difference between

In this way, the source and drain could be made into a vertical channel type, so-called vertical and horizontal type MisFET, while making it easy to make contact with the outside on the plane above the convex region and the bottom surface of the substrate. Therefore, it is easier to form electrodes (contacts) for the source and drain, and the channel length is as small as 0.1 to 1 μm, and the length can be controlled more precisely for the self-line process by adding impurities from an oblique direction. Manufacturing became possible.

As is clear from the above embodiments, the present invention provides vertical rectangular or triangular gate electrodes (18), (18'
) is adjacent to the convex region to increase the mechanical strength, while using a (100) plane in the channel forming region (6), (6°) to improve the interface state (positive effect due to the presence of silicon dangling bonds). (due to the generation of electric charge).

Also, the other side of the rectangular convex area ((3) in FIG. 2(E))
6), (36'')), the side surfaces were also (100) planes in order to prevent the generation of parasitic channels, and efforts were also made here to minimize the generation of positive fixed charges.

In addition, boron is added here (36) and (36) in Figure 2 (E).
°) to form channel cuts.

In this way, it is possible to produce a vertical and horizontal microchannel (μ-channel) type MIS FET that has a precisely controlled channel length and that reduces the area covered by the entire transistor substrate.

In FIG. 1, two Mis FETs in a rectangular convex region are formed as N-channel type, or another Mis FET is formed as P-channel type in the other part separated by a field insulator. The present invention can be further promoted by using LSI or VLSI as MIS structure (complementary structure).

Embodiment 2" FIG. 3(A) shows another embodiment to which the present invention is applied. The corresponding electric circuit is shown in FIG. 3(C).

FIG. 3(A) shows two MIS FETs using Example 1.
(10), (10°) and two capacitors (10),
(10”) are connected in series, ITr/C
Two e1l's are provided in pairs. That is, the convex region (35) has channel forming regions (6), (6”).
It has a source or drain (4) and a highly doped second impurity region (14) above it. In addition, a field insulator (3
), and the first impurity region (15), (15°)
and drain or source on the outside (5), (5°)
, two MrS FETs (1
0).

(10') was constructed. N+ to make this ohmic contact
(11) connected to the first region (15), (15”) of
(11°), capacitor (20), (20°) lower electrode (21), (21°), dielectric (22),
(22'), and further above that the upper electrode (23), (23
”), thereby capacitors (20), (2
0″).

In FIG. 3(A), (14) is a bit line, and (
18), ITr/Ce with (18') as the word line
The memory system has a structure in which two l I's form a pair. With such a structure, the convex region (35) is divided into two M
IS FET (10).

(10”), and dielectric (22”).
).

(22') can be made of a material with a high dielectric constant different from that of the gate insulating film, such as tantalum oxide, titanium oxide, silicon nitride, or barium titanate. It also has the feature of a stacked memory cell in which these dielectrics and electrodes can be stacked on top of each other to increase the overall capacitance.

In this example, gate electrodes (18), (18
The outer periphery of the first impurity region (15) is insulated by an oxide interlayer insulator (17), the thickness of which is 0.1 to 1.0 μm.

(15°) and the lower electrode (21) of the capacitor (20), (20').

The connection with (21') is achieved by selective growth of tungsten (
13).

An electrode (contact) was formed using (13'). For this reason, the lower electrodes (21), (21°) were made of tungsten silicide.

As described above, when the MIS FET of the present invention is used, the contact can be connected to the drain or source or the first impurity region and the depth of focus of the stepper can be kept constant even if the depth of focus is shallow, and precision doping due to out of focus can be prevented. can. And it can be obtained while having a sufficient area. That is, the first impurity regions (15) (15°) may be formed within the range of mask alignment accuracy when drilling holes for electrodes. If the accuracy is good, the area required for this drain or source can be reduced. The channel length could be made precisely as shown in Example 1, regardless of this contact formation region and without increasing the size of the MiS FET as seen from the substrate.

An interlayer insulator such as polyimide may be formed, and the third conductor wiring may be formed on the upper surface thereof.

In addition, we were able to form cells with extremely small area and high density. For manufacturing steps not shown in this Example, the Example] was used.

Embodiment 31 This embodiment is shown in a longitudinal sectional view in FIG. 3(B). This is another embodiment of the memory cell, and a corresponding circuit diagram is shown in FIG. 3(C).

As is clear from the drawing, a convex region (35) is provided on the surface of the semiconductor substrate, and a gate insulating film (2) is formed around the side thereof and at the corner of the bottom of the substrate.

(2゛) and further gate electrodes (18), (18
') are formed in pairs. A drain or source (5), (5') and a source or drain (4) were formed by ion implantation using a part of this gate electrode made of silicon as a mask. Furthermore, in order to form a channel as a recessed channel type, boron-doped (46)
(46'), arsenic-doped recessed channel (6),
(6") is provided by the self-line method in order to precisely define the channel length (6), (6"). In this way, μ-channel MIS FET (10), (10°
) were provided in a structure forming two pairs.

Next, since the contact openings (9), (9'') provided in this first impurity region (15), (15°) are provided in the same manner as in Example 1, this allows The side electrodes (20), (20'') were provided, for example, by forming doped silicon to a thickness of 0.1 to 1 μm. Tantalum oxide M (22) was added to this upper surface by sputtering.
(22°) was formed to a thickness of 100 to 500 people. In addition, silicon nitride and silicon oxide shown in Example 2 may be used. They were made by nitriding or oxidizing the lower electrode. Thereafter, counter electrodes (23), (23)') were provided on this surface using metal or semiconductor, and after photoetching, capacitors (20), (20'') were formed.

Thus, the upper electrode (23), (23°) of the capacitor (20), (20°) and the dielectric (22), (2
2') and the lower electrodes (21), (21'') could be made as a stacked memory cell.
an upper or convex region (35) and a gate electrode (18),
(18°), and when viewed from the entire semiconductor substrate, everything except the contact portion appears as if it were a capacitor, thereby increasing the density of the cell area. A multilayer wiring (24') is provided as a word line on the interlayer insulating film (17) via a contact (24) in the second impurity region (14), and a gate electrode (18>
, (18') as a bit line to form a pair of vertical channel type, source and drain horizontal arrangement type MrSFETs in a self-aligned manner.
It was effective in miniaturizing, increasing density, and improving reliability.

In this embodiment as well, similar to the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24') and the word line is the gate electrode (24').
8) and (18') could be configured as part of the ITr/cell memory system.

Furthermore, since these are integrated N-channel MiS FETs, they have a plurality of convex regions on the same substrate, and some of them can be used as complementary type (
It is effective to use a complementary (complementary) integrated circuit.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to configure a floating gate type nonvolatile memory.

In the above three embodiments, the material constituting the first region and the vertical rectangular or approximately triangular gate electrode (1
The material constituting 8) is mainly a material having the same main component as the substrate doped with an impurity having a P+ or N+ conductivity type, such as silicon.

However, they are mixtures or compounds of silicon and Mo, W, Ti (MoSi, WSi2.Ti5i2
), or a multilayer structure of intrinsic, P+ type or N+ type semiconductors, or a semiconductor such as silicon and Mo
, W, platinum, or a compound thereof may have a multilayer structure.

In the present invention, the semiconductor substrate is mainly made of single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

In addition, the channel formation region is a MISFET that uses surface diffusion.
Instead, it may be a recessed channel type.

Alternatively, a method using majority carriers may be used.

These are based on the method of controlling the structure of the channel portion under the gate insulating film.

``Effects'' As is clear from the above embodiments, the present invention achieves precision by doping impurities obliquely or laterally and forming the source or drain and the drain or source in a self-line manner using the gate electrode. The source and drain could be formed with control. The gate electrode has a mechanically reinforced structure in which its side portion leans against the convex first region, in an effort to improve reliability. The threshold voltage of the channel forming region has a structure in which impurities such as boron are doped into the upper part of the semiconductor diagonally or laterally, and the frequency is determined by its structural characteristics and the channel length of 0.1 to 1 μm. Very short channel (μ
The major feature is that MIS FET (channel) can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of the drawing]

FIG. 1 shows a longitudinal cross-sectional view of a conventionally known SFET. FIG. 2 is a longitudinal sectional view showing the manufacturing process and structure of an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which a pair of ITr/Cel memories are provided. l...Semiconductor substrate 3...Field insulator 5.5'...Drain or source 4...Source or drain 6.6'...Channel forming regions 15, 15'...・First impurity region 14... Second impurity region 18, 18'... Gate electrode 10, Icl"... Insulated gate field effect transistor (MIs FET) 20, 20... Capacitor ■~■...Buttering treatment using a photomask 37, 37''...Direction of ion implantation 38, 38°...Direction of ion implantation Fig. 1

Claims (1)

[Claims] 1. forming a convex region on a semiconductor substrate of one conductivity type, forming a gate insulating film on the side surface of the convex region, and forming the convex semiconductor substrate on the gate insulating film; a step of forming a film for configuring a gate electrode in a corner portion of the film, a step of performing anisotropic etching on the film to form a rectangular or triangular gate electrode in the corner portion, and a step of masking the gate electrode. forming a drain or source on the bottom of the semiconductor substrate by adding impurities obliquely to the semiconductor substrate using the gate electrode as a mask, and forming a source or drain on the top of the convex region; 1. A method for manufacturing a vertical channel insulated gate field effect semiconductor device, characterized in that it has the following characteristics: