JP3190255B2 - Insulated gate field effect transistor and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to providing an insulating gate type field effect semiconductor device of an ultra-high-density integrated circuit (referred to as ULSI) of a 16M to 16Gbit level.

The present invention relates to a semiconductor device, in particular, a vertical channel type MIS having a microchannel type in which current flows in the vertical direction.
(Insulating gate type) field effect semiconductor device (FET) (hereinafter referred to as a μ-channel MIS FET because the channel length is 0.03 to 1 μm, which is 1 μm or less). In addition to applying an align (self-alignment) process, the present invention proposes a composite semiconductor device in which a capacitor is connected to the process.

[0003] The present invention relates to a vertical channel type MISFET having a rectangular convex region formed by performing anisotropic etching and having a channel through which current flows in a vertical direction on a side surface of the convex region.

[0004] The present invention further relates to a semiconductor device in which a threshold voltage is controlled in a channel forming region.

[0005] The present invention further relates to a vertical channel type MISFET in which the generation of a parasitic channel on the side surface of another convex region is prevented before or after forming a gate electrode.

[0006]

2. Description of the Related Art Conventionally, as shown in FIG. 1, a method of fabricating a MIS FET or a capacitor connected in series with the MIS FET includes a semiconductor substrate (1) on which a field insulator (2) is selectively provided. -On the surface, a gate insulator (2) and a gate electrode (1
8) and source or drain (4), drain or source
Using the gate electrode (18) as a mask, the gate electrode (18) is used as a mask to form a self-aligned structure in which impurities are doped by ion implantation in the vertical direction from above, so-called LDD (a drain having a relatively low impurity concentration, i.e., a light Doped drain)
Formed.

A rectangular or triangular portion (38), (38 ') of an insulator is formed around the side of the gate electrode (18). The first impurity region (15) and the second impurity region (14) were formed in a plane to form the MIS FET (10). Further, the lower electrode (2) is connected to the first impurity region (15) and serves as a capacitor (20).
1), a dielectric (22), and an upper electrode (23) were provided.

[0008]

[Problems to be Solved by the Invention] As described above, the MIS FET
(10) The capacitor (20) is formed on a semiconductor substrate by forming the same plane. In the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to constitute a 1-bit memory), this planar configuration requires a large cell area and limits the high-density integration. Was.

On the left and right sides of the gate electrode (18), LDD (4),
As an auxiliary means for producing (5), rectangular or triangular portions (38) and (38 ') are made of an insulator. The present invention relates to a method for fabricating a structure in which the rectangular or triangular portion is provided not as an insulator but as a conductor or semiconductor gate electrode itself.

[Object of the Invention] In the present invention, a rectangular convex region is provided, and one or two side surfaces of this region are used as a channel forming region. That is, current flows in the vertical direction, the channel length is extremely small, 0.03 to 1 μm, and the size of one MISFET is 1 μm to 10 μm.
An object of the present invention is to provide an element structure for ULSI that can be manufactured from 16M to 16G bits by reducing the size to about □.
It is another object of the present invention to provide an inverter structure by combining the MIS FET and a memory cell structure connected to another element such as a capacitor.

[0011]

According to the present invention, a rectangular convex region is provided on a single crystal semiconductor substrate. This convex (1
(00) plane or its vicinity ((100) plane or its vicinity, namely (10
(The deviation within ± 10 ° from the (0) plane is hereinafter simply referred to as the (100) plane.) Each of the four sides is defined as a (100) plane at the same time. , That is, a vertical channel type.

In the present invention, the source in the MIS FET is
The purpose of the present invention is to provide an asymmetrical MISFET by forming the source and drain laterally to facilitate electrode formation in the subsequent process. That is, a rectangular convex single crystal semiconductor region is provided on the main surface of the semiconductor substrate.

Using the rectangular or triangular gate electrode formed in the convex region as a mask, a self-aligned (self-alignment) system, that is, the end of the gate electrode is a source or drain and a drain or source or drain. The end (the portion in contact with the channel forming region) was used as a standard for manufacturing. That is,
The source or drain of one of the MIS FETs is formed on the upper part, the lower side of the gate electrode in this convex region is formed as a vertical channel forming region, and the drain or the source is formed on the bottom of the semiconductor substrate. -Make a wire.

The source or drain and the drain or source are added in an oblique direction or a lateral direction while the impurity concentration is set to 3 × 10 ^{17 to} 5 × 10 ²⁰ cm ^-3 by, for example, ion implantation. do. Then, the region with a higher impurity concentration is not inside the oblique surface of the convex region or the bottom of the semiconductor substrate, but inside the semiconductor deeper than that. As a result, injection of hot carriers into the gate insulator can be prevented.

The source electrode substantially coincides with the upper end of the gate electrode.
The gate and drain ends are provided a little larger and larger on the side of the channel forming region to prevent the gate electrode from having an offset structure and to provide a margin for production (margin). By adding an impurity to the rectangular convex region from the lateral or oblique direction by using, for example, an ion implantation method, the threshold voltage of the channel forming region was controlled, and the embedding channel was formed.

The impurity concentration varies depending on the interface state density. However, in the case of an N-channel MISFET, the threshold voltage is set to within ± 1 V, and +0.1 to + V for normally-off.
+ 1.0V and -0.1 to -1.0V to turn on normally
And The opposite sign is used in the P-channel MIS FET.

In the aspect where the channel is not formed, the generation of the parasitic channel is prevented in the vertical direction so that the minute leak due to the generation of the parasitic channel does not flow. In order to prevent this parasitic channel, in the N-channel MISFET, boron is set to a concentration lower than the impurity concentration of the source or drain for LDD and higher than the impurity concentration of the substrate. Generally, it is 1 × 10 ¹⁶ to 2 × 10 ¹⁸ cm ⁻³ .

The source or drain and the drain or source are provided with contact holes for making the second impurity region and the first impurity region having a high impurity concentration easily in ohmic contact with an external electrode. Is provided with a flat surface so that a hole can be finely and precisely formed.

Conversely, even if an attempt is made to form a contact hole on the side surface, the manufacturing process is generally carried out by applying ultraviolet light for photoetching downward from above, so that 0.1 to 0.5 μm is required.
It is almost impossible to form a contact hole having a size of m □.
The present invention eliminates this disadvantage.

For this reason, in the semiconductor device of the present invention, the area occupied by the conventional horizontal MISFET in the substrate is not reduced by scaling, but is actively provided in the height direction in order to constitute a ULSI. It is intended to be fulfilled by doing so.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 2 shows a manufacturing process of this embodiment. Rectangular convex region of single crystal semiconductor substrate (35)
And two vertical channel type N-channel MISFETs are provided as pairs (10) and (10 ').

FIGS. 2A to 2D are longitudinal sectional views, and FIG. 2E is a plan view. The cross section taken along the line AA 'in FIG. 2E corresponds to FIGS. 2A to 2D.

A single-crystal semiconductor substrate, for example, a silicon single-crystal semiconductor (100) surface, P-type 10-500 Ωcm was selected. As shown in FIGS. 2A and 2E, the semiconductor substrate is formed with a first photomask (shows a photolithography process using a photomask) on the semiconductor substrate. An area (35) was formed. The silicon single crystal substrate may be manufactured by anisotropic etching. It is important that the corner has a very sharp vertical surface at 90 ° to the upper surface of the substrate. The height of the convex area (35) is 0.5 to 4 μm.
m, for example, 1.5 μm.

Then, as shown in FIG. 2 (E), the convex region (35) having a rectangular shape has a channel forming region (100) plane (<
100> direction (40)) and the parasitic channel prevention surface is also (010)
Plane (<010> direction (40 ')).

In all of these aspects, the fixed charge density can be reduced to about half of that of other (110) and (111) crystal planes.

A silicon nitride (33) having a masking effect on an oxidizing gas was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask ().

After doping a P-type impurity for forming a channel cut into the removed region, a field insulator (3) is formed.
Is embedded in a thickness of 0.5 to 2 .mu.m to obtain the state shown in FIG.

As shown in FIG. 2B, the silicon nitride film (33)
Then, a film (2) for forming a gate insulating film was formed on the semiconductor substrate (1) having the convex region (35).

The channel forming regions (6) and (6 ') are formed as gate insulating films.
Before or after the formation of (2), it was formed on at least the side surface of the rectangular convex region by means such as ion implantation. That is, the channel forming regions (6) and (6 ') control the threshold voltage, since this embodiment is the case of the N-channel type MISFET, and have the no-channel for the enhancement type MISFET. Controls the dose amount to +0.1 to + 1.0V for normally-off, for example + 0.5V, and -0.1 to -1.0V for normally-on for depletion type MIS FET, for example -0.5V. Was fulfilled.

These were used as channel forming regions, and one or both of the channel forming regions (6) and (6 ') were automatically formed using a photomask. The addition of two or three types of impurities may be performed twice as the embedding channel type. These positively added impurities to the side surfaces on the (6) and (6 ′) sides of the convex region (35). For example, lateral or oblique ion implantation (38), (38 ') was doped with boron or boron and arsenic.

In the rectangular convex region (35) where the channel is not formed ((36) and (36 ') in FIG. 2 (E)), a parasitic channel is liable to occur, and the source or drain is formed.
A small leakage between (4) and the drain or source (5), (5 ')
Boron was added at a higher concentration than the substrate, that is, the convex region, so as to prevent the occurrence of a blocking current, and the channel was cut so that the off state was constantly achieved. That is, the ion implantation was performed obliquely or laterally with respect to the plane on the substrate.

The ion implantation causes damage not only to the substrate but also to the insulating film (33) or (2). Region (35) was single crystallized.

This ion implantation step may be performed in the step of FIG. 2A or the step of FIG.

The silicon oxide film (2) is removed and another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film ( 2)

Next, as shown in FIG. 2B, a window for use as a source or drain electrode (contact) was formed in the gate insulating film (2) using a third photomask (). After the surface of the insulating film is sufficiently cleaned, a conductive type impurity, for example, an N type impurity (phosphorus) is deposited on the substrate by a low pressure vapor phase method (LPCVD method) at 1 to 10 × 10 ²⁰ cm ^−3. To the concentration of
0.5 to 2.5 mm of silicon semiconductor (silicon) coating (7)
A gate electrode and other leads were formed on the entire surface to a thickness of μm. This impurity doping is not performed simultaneously with the film formation, but is diffused after the following anisotropic etching is performed on the film (7) so as to leave the portions (8) and (8 ') serving as gates to remain as gates. It may be performed by a method or an injection method.

The coating (7) may be a conductor such as a metal or an intermetallic compound instead of a silicon semiconductor doped with impurities. Further, a multilayer film of a P ⁺ or N ⁺ type semiconductor and a metal or a metal compound, particularly Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ) may be used.

Thus, FIG. 2B is obtained.

Next, as shown in FIG. 2 (C), a photoresist (
For example, OMR-83 (manufactured by Tokyo Ohka) () was selectively coated, and then anisotropic etching was performed. For this etching, it is important to use an anisotropic etching method with very little or no side etch and taper etch, instead of an isotropic etching method using a conventionally used solution.

Specifically, a reactive gas for etching, for example, nitrogen fluoride (N
F ₃ ) and carbon fluoride (CF ₄ ) are chemically activated, and the degree of vacuum is increased from 0.1 to 0.001 torr, especially from 0.005 to 0.01 torr. Then, a bias was applied to the substrate, and an effort was made to eliminate side etching as a low-temperature etching.

As a result, when the planar portion where the photoresist is not formed is completely removed from the coating (7), the coating (8) on the side surface which is the corner of the convex region (35) is obtained. , (8 ')
Since the effective thickness was large when viewed from above, the gate electrodes (18) and (18 ′) were left around the sides as vertical rectangular or triangular gate electrodes. Further, a contact (11) in the first impurity region (corresponding to (15) in FIG. 2D) of the drain or source (5), (5 ')
And its lead (12) could be left as an electrode lead of the N ⁺ type in this embodiment. Gate electrode (18), (18 ')
Does not exist over the upper surface of the convex region (35), and its width is not determined by photolithography, but can be determined by the thickness of the side surface of the coating (7) and the degree of anisotropic etching. .

Thereafter, the whole is oxidized to form a silicon oxide insulating film (47) on the convex region, the bottom of the semiconductor substrate and the surfaces of the gate electrodes (18) and (18 ') to a thickness of 300 to 2000 mm. did. Next, this rectangular or triangular gate electrode (18), (1
As shown in (37) and (37 '), impurities are added obliquely using 8') as a mask. When using the in-implantation method, arsenic is accelerated to 0.3 at an accelerating voltage of 30 to 100 KeV because of the N-channel type.
It was added to a concentration of 5-5 × 10 ¹⁵ cm ^−2, for example 1 × 10 ¹⁵ cm ⁻² .

Then, using the end portions (44) of the gate electrodes (18), (18 ') or the insulating film (47) thereon as a mask, a convex region (35) is formed.
Has a source or drain (4) at its end (4
4 ′) roughly matches the end (44) of the gate electrode, and the inside (44 ″) is closer to the channel forming region than this end (44 ′).
It is formed at a position close to the drain or source as viewed from (6 '). Thus, a source or drain (4) is formed.

On the other hand, the end (48 ') of the drain or source (5') is formed substantially in line with the end (48) of the other gate electrode (18 '), and is deeper than that position. (Position close to source or drain) Inside drain or source (48 '')
Is formed.

Thus, the source or drain (4), the drain or source (5), (5 ') is self-aligned (self-aligned) by the ends of the gate electrodes (18, 18'). It has a feature that the position is determined, and positioning is particularly performed by ion implantation from an oblique direction.

The gate electrode (18 ') is extended as a lead (38') as shown in FIG.
(18) connects the lead (12) to the contact (11).

In FIG. 2D, in order to form a region having a higher impurity concentration than the upper region, the first impurity regions (15), (15 '),
May be formed to make ohmic contact. However, these impurity regions vary the acceleration voltage when forming the source or drain (4) and the drain or source (5) or (5 '), and reduce the dose at a high acceleration voltage. Added to a high dose region with a strong acceleration voltage, for example, 1 × at 100 KeV.
10 ¹⁴ cm ^-2 , 3 × 10 ¹⁴ cm ^-2 at 50 KeV, 2 × 10 ¹⁴ cm at 30 KeV
It can be formed at a time by changing to ^-2 .

In FIG. 2C, rectangular or substantially triangular gate electrodes (18) and (18 ') have a lower end portion having a width of 0.1 to 1 μm.
m, but the layers can be extended as leads (38), (38 ') on the field insulator as required by the design, and the width of the leads can be 1 to Needless to say, it may be provided as wide as 10 μm and connected to electrode leads of other MIS FETs provided on the same substrate, or electrically connected to other capacitors, resistors and the like.

In the drawing, the selective growth of tungsten (24), (1
3) and lead aluminum (24 '), (12'), (38 '')
Was formed and multilayer wiring was performed.

In FIGS. 2D and 2E, the inverters, namely, the power supply side (38 ''), the load (10), the outputs (24) and (24 '), and the driver (1) are provided.
0 '), and constitute the grounding side (12), (12'). After these steps, an interlayer insulating film may be formed on the whole, the output may be connected to the second impurity region (14), and the current may be connected to the electrode (12 ') by applying a multilayer wiring.

The channel length of the MISFET is the end (44) of the source or drain (4) or (44 '') and the end (48) of the drain or source (5), (5 '). ') Or (48'').

Thus, the source and the drain are formed in a vertical channel type so-called vertical / horizontal type MISFET while making the upper surface of the convex region and the plane of the substrate bottom face easy to contact with the outside.
And could be. Therefore, it is easy to form an electrode (contact) for the source and drain, and the channel length is as small as 0.1 to 1 μm, and the length is reduced for the self-alignment process by adding impurities obliquely.
More precise controlled production became possible.

As is clear from the above embodiments, the present invention provides a vertical rectangular or triangular gate electrode (18), (18 ').
In addition to increasing the mechanical strength adjacent to the convex region, the (100) plane is used for the channel forming regions (6) and (6 ') to make the interface state (positive due to the existence of dangling bonds in silicon). (By generation of electric charge)
Was reduced.

Another side surface of the rectangular convex region (FIG. 2)
In (E) (36), (36 ')), the side surface was also set to the (100) surface so as to prevent the generation of the parasitic channel, and the endeavor was again made to minimize the generation of positive fixed charges. Boron was added here as shown in (36) and (36 ') of FIG. 2 (E) to form a channel cut.

Thus, a vertical / horizontal micro-channel (μ channel) type MIS FE having a precisely controlled channel length and a small area of the transistor substrate.
T can be made.

FIG. 1 shows two MIS FEs in a rectangular convex area.
Although T is formed as an N-channel type, another MIS FET is formed as a P-channel type at another portion separated by a field insulator, and an LSI, a MIS structure (complementary structure) is formed.
VLSI can further promote the present invention.

Embodiment 2 FIG. 3A shows another embodiment to which the present invention is applied. The corresponding electric circuit is shown in FIG. FIG. 3A shows two MIS FETs (1
0), (10 ′) and two capacitors (10), (10 ′) are respectively connected in series, and two 1Tr / Cells are provided. That is, the channel-forming region (6),
(6 '), on which a source or drain (4) and a high-concentration second impurity region (14) are provided.

Further, a field insulator (3) is provided on the periphery of the bottom of the semiconductor substrate (1) to provide a first impurity region (1).
(5), (15 ') and the drain or source outside (5), (5'),
Gate electrode (18), (18 '), gate insulating film (2), (2')
Two MIS FETs (10) and (10 ') were constructed. The lower electrodes (21) of the capacitors (20) and (20 ') are connected (11) and (11') to the N ⁺ first regions (15) and (15 ') to make this ohmic contact. , (21 ′), dielectrics (22), (22 ′), and upper electrodes (23), (23 ′) provided thereon, thereby forming capacitors (20), (20 ′).

In FIG. 3A, (14) is a bit line, and a memory system having a structure in which two 1Tr / Cells are paired using (18) and (18 ') as word lines. With such a structure, the convex region (35) can be used in common for the two MIS FETs (10) and (10 '), and the dielectrics (22) and (22') are different from the gate insulating film. Different high dielectric constant materials can be used, such as tantalum oxide, titanium oxide, silicon nitride, barium titanate. Also, there is a feature of a stacked memory cell in which these dielectrics and electrodes can be stacked on each other to increase the overall capacitance.

In this embodiment, the gate electrode (18),
The outer periphery of (18 ') is insulated by the oxide interlayer insulator (17), but its thickness is 0.1 to 1.0 μm, and the first impurity regions (15), (15') The connection with the lower electrodes (21) and (21 ') of the capacitors (20) and (20') formed electrodes (contacts) by selective growth of tungsten (13) and (13 ').
For this reason, the lower electrodes (21) and (21 ′) are made of tungsten silicide.

As described above, when the MISFET of the present invention is used, the contact can be kept constant even when the depth of focus of the stepper is shallow by connecting to the drain or source or the first impurity region. Precise addition can be prevented. And it is possible to obtain while having a sufficient area. That is, the first impurity regions (15) and (15 ') may be formed within the range of the mask alignment accuracy when making the holes for the electrodes. If the accuracy is good, the area required as the drain or source can be reduced. The channel length could be made precisely as shown in Example 1 irrespective of the contact formation region and without increasing the size of the MIS FET as viewed from above the substrate.

An interlayer insulator such as polyimide may be formed, and a third conductor wiring may be formed on the upper surface thereof.

The cell area was extremely small and could be formed at high density. Example 1 was used for manufacturing steps not shown in this example.

Embodiment 3 FIG. 3B is a longitudinal sectional view of this embodiment. FIG. 3C shows another embodiment of the memory cell, and a corresponding circuit diagram.

As is apparent from the drawing, a convex region (35) is provided on the surface of the semiconductor substrate, and the gate insulating films (2), (2) are formed on the corner between the side and the bottom of the substrate. '), And the gate electrodes (18) and (18') are formed as a pair. With a part of the gate electrode such as silicon as a mask, the drain or source (5),
(5 '), source or drain (4) were formed.

Further, in order to form a channel as an embedding channel type, the boron doping (46), (46 '), and the arsenic doping embedding channels (6), (6') have the channel length (6). ) And (6 ') are provided by the self-alignment method for precise control. Thus, the μ-channel MIS FETs (10) and (10 ′) are provided in a structure forming two pairs.

Next, the contact openings (9) and (9 ') provided in the first impurity regions (15) and (15') are provided in the same manner as in the first embodiment. Lower body electrode (2
0) and (20 ') are provided, for example, by forming doped silicon to a thickness of 0.1 to 1 μm. On this upper surface, tantalum oxide films (22) and (22 ') were formed to a thickness of 100 to 500 mm by sputtering. In addition, silicon nitride or silicon oxide described in the second embodiment may be used. It was made by nitriding or oxidizing the lower electrode. After this, counter electrodes (23), (23) ′) are provided on the surface by metal or semiconductor, and after photo-etching,
Capacitors (20) and (20 ') were used.

Thus, the upper electrodes (23) and (23 ') of the capacitors (20) and (20') and the dielectrics (22) and (22 ') and the lower electrodes (2
1), (21 ') could be made as a stacked (stacked) memory cell. In addition, this capacitor is connected to the field insulating film (3) or the convex region (35) and the gate electrode (1).
8) and (18 '), and the cell area could be increased so that the entire semiconductor substrate could be seen as a capacitor except for the contact portion as a whole.

A multilayer wiring (24 ') is provided as a word line on the interlayer insulating film (17) through the contact (24) in the second impurity region (14), and the gate electrodes (18), (18') are formed. ) As a bit line, forming a pair of vertical channel type, source and drain laterally arranged MISFETs in a self-aligned manner can reduce the size, increase the density, and improve the reliability. Was effective.

In this embodiment, as in the second embodiment, a material having a high dielectric constant such as tantalum oxide can be used as the dielectric material, and the bit line is formed in the region (24 ') and the word line is formed in the gate. It can be configured as a part of a 1Tr / cell memory system that makes a pair with the electrodes (18) and (18 ').

Also, since these are integrated N-channel MISFETs, they have a plurality of convex regions on the same substrate, some of which are complementary as P-channel MISFETs (
It is effective to use a (complementary) integrated circuit.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to constitute a floating gate type nonvolatile memory.

In the above three embodiments, the material forming the first region and the material forming the vertical rectangular or substantially triangular gate electrode (18) have a P ⁺ or N ⁺ conductivity type. The description is centered on a material having the same main component as that of the substrate doped with impurities, for example, silicon.

However, they may be a mixture or a compound (MoSi ₂ , WSi ₂ , TiSi ₂ ) of silicon and Mo, W, Ti, or may be an intrinsic, P ⁺ -type or N ⁺ -type semiconductor having a multilayer structure. However, it goes without saying that a multilayer structure of a semiconductor such as silicon and Mo, W, platinum or a compound thereof may be provided.

In the present invention, single-crystal silicon is mainly used for the semiconductor substrate. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous or semi-amorphous semiconductor.

The channel forming region uses surface diffusion.
Instead of the MIS FET, it may be an embossed channel type. Further, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[0077]

As is clear from the above embodiments, the present invention adds a dopant from an oblique direction or a lateral direction to increase the channel length by the gate electrode so that the source or drain and the drain or source are self-aligned. Thus, the source and the drain could be formed by precise control.

Further, by making the convex side surface on which the channel is formed a (100) plane, the generation of interface charges is reduced, and anisotropic etching can be easily performed.

The gate electrode has a structure that is mechanically reinforced so that the side portion of the gate electrode hangs over the first convex region, and the reliability is improved.

The threshold voltage of the channel forming region has a structure in which an impurity such as boron is doped on the upper part of the semiconductor obliquely or laterally, and has a structural characteristic of 0.1 to 1 μm. It has a great feature that an extremely short channel (μ channel) MISFET having a frequency response speed of 1 to 10 GHz depending on the channel length can be implemented without using a technique such as electron beam exposure as an absolute requirement.

[Brief description of the drawings]

FIG. 1 shows a longitudinal sectional view of a conventionally known MIS FET.

FIG. 2 is a longitudinal sectional view showing a manufacturing process and a structure according to an embodiment of the present invention.

FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which 1Tr / Cell memories are provided in a pair.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... Field insulator 4 ... Source or drain 5, 5 '... Drain or source 6, 6' ... Channel formation region 10,10 '・ ・ ・ Insulated gate field effect transistor (MIS F
ET) 14 second impurity region 15, 15 'first impurity region 18, 18' gate electrode 20, 20 'capacitor ... pattern by photomask -37, 37 '... direction of ion implantation 38, 38' ... direction of ion implantation

Claims (16)

(57) [Claims] 1. A were eclipsed set on the surface of the semi-conductor substrate, a protruding region that having a first side and a pair of parallel second side each other pair are parallel to each other physician, a gate insulating film setting said pair of first respective gate sites provided on the electrode side through to said not to overlap with the convex region of the semiconductor substrate region
A vignetting first impurity regions, have a second impurity region having the same conductivity type as said first impurity region provided in the upper portion of the convex region, a first side surface of the pair Each of the first impurities
A channel provided between the region and the second impurity region
A forming region, wherein each of the pair of second side surfaces has the first impurity
An insulated gate field effect transistor to which an impurity of a conductivity type opposite to that of a region is added. 2. The semiconductor device according to claim 1, further comprising:
A pair of first sides and a pair of second sides parallel to each other
Each of the pair of first side surfaces via a convex region having a surface and a gate insulating film.
And a gate electrode provided in a region not overlapping with the convex region in the semiconductor substrate.
A first impurity region, and a first impurity region provided above the convex region.
A second impurity region having the same conductivity type as that of the second impurity region; and a second impurity region provided above the second impurity region,
A second impurity region having the same conductivity type as that of the pure region, and
A third impurity region having a higher impurity concentration than the first impurity region;
The first impurity region provided above the impurity region of
And the same conductivity type as that of the first impurity region.
A fourth impurity region having a high impurity concentration, wherein each of the pair of first side surfaces has the first impurity region.
Channels provided between said region second impurity object region
A forming region, wherein each of the pair of second side surfaces has the first impurity
The feature is that the impurity of the conductivity type opposite to that of the region is added
Insulated gate field effect transistor. 3. The method according to claim 1, wherein
The impurity concentration of the second side surface of the pair is the first impurity region.
Alternatively, the impurity concentration of the second impurity region and the semiconductor
Characterized by a value between the impurity concentration of the body substrate
Insulated gate field effect transistor. Wherein any one smell of claims 1 to 3
The impurity concentration of the pair of second side surfaces is 1 × 10 ¹⁶
Insulating gate having a size of 2 × 10 ¹⁸ cm ^-3
Type field effect transistor. Any Te one odor <br/> of 5. A method according to claim 1 to claim 4, wherein the gate electrodes are above the first non-pure product area
Insulated gate field effect transistor characterized by the following:
Ta. 6. Any one smell of claims 1 to 5
And the pair of first side surfaces and the pair of second side surfaces
Is an (100) crystal plane,
G field effect transistor. 7. The method according to claim 2, wherein :
Of the gate electrode farthest from the gate insulating film.
The end face is aligned with the end face of the fourth impurity region.
Characterized by an insulating gate type field effect transistor. 8. The method according to claim 1, wherein
Of the pair of first gate electrodes
On each of the sides and electrically connected to each other
And a semiconductor integrated circuit. 9. An insulated gate field effect transistor and a capacitor.
A semiconductor integrated circuit having a capacitor , wherein the insulated gate field effect transistor is provided on a surface of a semiconductor substrate and has a pair of first
Having a side surface and a pair of second side surfaces parallel to each other
Region and each of the pair of first side surfaces via a gate insulating film.
And a gate electrode provided in a region not overlapping with the convex region in the semiconductor substrate.
A first impurity region, and a first impurity region provided above the convex region.
Same electrically and a second impurity region having a conductivity type, each of the first side surface of said pair, said first impurity and
A channel provided between the region and the second impurity region
A forming region, wherein each of the pair of second side surfaces has the first impurity
An impurity having a conductivity type opposite to that of the region is added, and the capacitor is connected to the first impurity region.
A lower electrode, an upper electrode, the lower electrode, and the upper electrode
Has a dielectric provided between the second impurity region is connected to the bit line, the Gay
The gate electrode is connected to a word line.
Conductor integrated circuit. 10. A semiconductor integrated circuit having an insulated gate field effect transistor and <br/> capacitor, said insulated gate field effect transistor is provided on the surface of the semi-conductor substrate, a pair of mutually parallel first 1
And a convex region having a pair of second side surfaces parallel to each other, and each of the pair of first side surfaces via a gate insulating film.
And a gate electrode provided in a region not overlapping with the convex region in the semiconductor substrate .
A first impurity region kicked, and the second impurity regions having the same conductivity type as said first impurity region provided in the upper portion of the convex region is provided in an upper portion of the second impurity region A third impurity region having the same conductivity type as that of the second impurity region and having an impurity concentration higher than that of the second impurity region; and a third impurity region provided above the first impurity region. 1 failure
The same conductivity type as the pure region and the first impurity region
A fourth impurity region having an impurity concentration higher than that of the first impurity region.
A channel provided between the region and the second impurity region
A forming region, wherein each of the pair of second side surfaces has the first impurity
It is added region and opposite conductivity type impurities, before Kiko capacitor is connected to the fourth impurity regions
A lower electrode , an upper electrode, and a dielectric provided between the lower electrode and the upper electrode ; the third impurity region is connected to a bit line; and the gate electrode is connected to a word line. Is characterized by being half
Conductor integrated circuit . 11. The method of claim 9 or claim 10, before <br/> SL impurity concentration of the pair of second aspect, wherein the impurity concentration of the semiconductor substrate and the first impurity region or the second impurity A semiconductor integrated circuit having a value between the impurity concentration of the region and the impurity concentration of the region. 12. The method according to claim 9 , wherein the impurity concentration on the pair of second side surfaces is 1 × 1.
Semiconductor characterized by having a density of 0 ^{16 to} 2 × 10 ¹⁸ cm ⁻³
Integrated circuit . 13. The method according to claim 9, wherein:
Wherein the gate electrode is located above the first impurity region.
A semiconductor integrated circuit. 14. The method according to claim 9, wherein:
The pair of first side surfaces and the pair of second side surfaces
The semiconductor is characterized in that the plane is a (100) crystal plane
Integrated circuit. 15. The method according to claim 10, wherein :
, The gate farthest from the gate insulating film
The end face of the electrode is aligned with the end face of the fourth impurity region.
A semiconductor integrated circuit characterized by the above. 16. The method according to claim 9, wherein:
Wherein the insulated gate field effect transistor is
Provided on each of the pair of first side surfaces, and electrically connected to each other.
A semiconductor integrated circuit, wherein the semiconductor integrated circuit is electrically connected.