JPH09162403A - Insulated gate field-effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a leak current from flowing between a first impurity region and a second impurity region, by making a pair of field-effect semiconductor devices independent of each other, and adding impurities into the second flanks of the pair. SOLUTION: A rectangular projecting region 35 is made, using a first photomask 1, for a semiconductor substrate, and the two of N-channel MIS FET's are provided as a pair 10 and 10'. The flanks on the side of 6 and 6' of the projecting region 35 are doped laterally or obliquely with ions 38 and 38' of boron or boron and arsenic. In the regions 36 and 36' where channels are not made of the rectangular projecting region 35, parasitic regions get to arise easily, and between the source or drain 4 and drain or sources 5 and 5, feeble leak currents are generated. Accordingly, leak currents can be prevented from flowing by adding boron into concentration higher than the substrate, that is, the projecting region, and cutting the channel each time the off state is accomplished.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to providing an insulating gate type field effect semiconductor device of an ultra-high density integrated circuit (ULSI) of 16M to 16G bit level.

The present invention relates to a semiconductor device, particularly a vertical channel MIS having a micro channel type in which a current flows in the vertical direction.
Type (insulating gate type) field effect semiconductor device (FET) (hereinafter referred to as μ channel MIS FET since the channel length is 0.03 to 1 μm with a channel length of 1 μm or less), even if it is a micro channel as described above. This is to propose a semiconductor device in which an align (self-alignment) process is applied and, for example, a capacitor is connected to it to form a composite.

The present invention relates to a vertical channel type MIS FET having a rectangular convex region provided by anisotropic etching, and having a channel for passing a current in the vertical direction on the side surface of the convex region.

The present invention further relates to a semiconductor device having a controlled threshold voltage in the channel formation region.

The present invention further relates to a vertical channel type MIS FET which prevents generation of a parasitic channel on the side surface of another convex region before or after forming the gate electrode.

[0006]

2. Description of the Related Art Conventionally, as shown in FIG. 1, the structure of a method for manufacturing a MIS FET or a capacitor connected in series to a MIS FET is a semiconductor substrate (1) on which a field insulator (2) is selectively provided.ー On the surface, gate insulator (2), gate electrode (1
8) and source or drain (4), drain or source
The so-called LDD (drain with a relatively low impurity concentration, that is, the write Doped drain)
Formed as.

Around the side of the gate electrode (18), rectangular or triangular portions (38) and (38 ') of an insulator are formed, and this end is used as a mask to form a high impurity concentration first outside. The first impurity region (15) and the second impurity region (14) were formed in a plane to form a MIS FET (10). In addition, the lower electrode (2) is connected to the first impurity region (15) as a capacitor (20).
1), the dielectric (22) and the upper electrode (23) were provided.

[0008]

[Problems to be Solved by the Invention] Thus, MIS FET
The capacitor (20) and the capacitor (20) are formed on the semiconductor substrate in the same plane. In the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to form a 1-bit memory), this planar configuration increases the cell area and limits high-density integration. It was

On the left and right of the gate electrode (18), LDD (4),
As an auxiliary means for making (5), rectangular or triangular parts (38) and (38 ') are made of an insulator. The present invention relates to a method for fabricating a structure in which the rectangular or triangular portion is provided not as an insulator but as a conductor or semiconductor gate electrode itself.

"Object of the Invention" In the present invention, a rectangular convex region is provided, and one or two side surfaces of this region are used as a channel formation region. That is, the current is made to flow in the vertical direction, the channel length is made extremely small at 0.03 to 1 μm, and the size of one MIS FET is 1 μm □ to 10 μm.
It is to provide a device structure for ULSI that can be made up to 16M to 16G bits by making it as small as □.
Another object of the present invention is to provide an inverter structure by combining these MIS FETs and a memory cell structure connected to other elements such as capacitors.

[0011]

According to the present invention, a rectangular convex region is provided on a single crystal semiconductor substrate. This convex (1
(00) plane or its vicinity ((100) plane or its vicinity, that is, (10
The deviations within ± 10 ° from the (0) plane are simply referred to as (100) planes below. Each of the four side surfaces is simultaneously defined as the (100) plane, and two of these side surfaces are used as the channel formation region, and the current is applied in the vertical direction. Flow, that is, a vertical channel type.

In the present invention, the source in the MIS FET is
In order to facilitate the formation of electrodes in the subsequent steps, the drain and the drain are formed laterally to provide an asymmetric MIS FET. That is, a rectangular convex single crystal semiconductor region is provided on the main surface of the semiconductor substrate.

Using the rectangular or triangular gate electrode formed in this convex region as a mask, the end of the gate electrode is formed into a source or drain and a drain or source by a self-alignment method. It was used as a standard for manufacturing the end portion (portion in contact with the channel formation region). That is,
One of the sources or drains of the MIS FET is formed above it, the side of the convex region below the gate electrode is the vertical channel formation region, and the bottom of the semiconductor substrate is the drain or source. -Make a cloth.

These sources or drains and the drains or sources are added in an oblique direction or a lateral direction while the impurity concentration is set to 3 × 10 ^{17 to} 5 × 10 ²⁰ cm ^-3 by, for example, an ion implantation method. do. Then, the region with a higher impurity concentration is not inside the oblique surface of the convex region or the bottom of the semiconductor substrate, but inside the semiconductor deeper than that. As a result, injection of hot carriers into the gate insulator can be prevented.

The source electrode is substantially aligned with the upper end of the gate electrode, and
It has an end portion of a drain or a drain, and the inside thereof is provided slightly larger on the channel formation region side to prevent the gate electrode from having an offset structure and to give a margin to the manufacturing. Impurities were laterally or obliquely added to this rectangular convex region by, for example, an ion implantation method to control the threshold voltage of the channel forming region and form a recessed channel.

This impurity concentration varies depending on the interface state density, but in the N-channel MIS FET, the threshold voltage is kept within ± 1 V, and in order to be normally off, + 0.1-.
+ 1.0V, -0.1 to -1.0V to turn on normally
And The opposite sign is used in the P-channel MIS FET.

On the side where the channel is not formed, the generation of the parasitic channel is prevented in the vertical direction so that the minute leak due to the generation of the parasitic channel does not flow. In order to prevent this parasitic channel, boron is used in the N-channel MIS FET at a concentration lower than the impurity concentration of the LDD source or drain and higher than that of the substrate. Generally, it is 1 × 10 ¹⁶ to 2 × 10 ¹⁸ cm ⁻³ .

The source or drain and the drain or source have holes for contact in order to facilitate the ohmic contact between the second impurity region and the first impurity region having a high impurity concentration with an external electrode. Is provided with a flat surface so that the holes can be finely and accurately opened.

On the contrary, even if a contact hole is to be formed on the side surface, in the manufacture, the exposure of ultraviolet light for photoetching is generally performed from the upper side to the lower side, so that it is 0.1 to 0.5 μm.
It is almost impossible to form a contact hole with a size of m □.
The present invention eliminates this drawback.

Therefore, in the semiconductor device of the present invention, the densification for constructing the ULSI is not provided by scaling the area occupied by the substrate of the conventional lateral MIS FET by scaling, but is actively provided in the height direction. The purpose is to fulfill it.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

"Embodiment 1" This embodiment shows the manufacturing process thereof in FIG. Rectangular convex area of single crystal semiconductor substrate (35)
Is used to provide two vertical channel N-channel MIS FETs as a pair (10), (10 ').

2A to 2D are vertical sectional views thereof, and FIG. 2E is a plan view thereof. The cross section AA 'of FIG. 2 (E) corresponds to FIGS. 2 (A) to (D).

A single crystal semiconductor substrate, for example, a silicon single crystal semiconductor (100) plane, P-type 10 to 500 Ωcm was selected. For this semiconductor substrate, using a first photomask (-indicates a photolithography process using the photomask), as shown in FIGS. 2A and 2E, a rectangular convex shape is seen from above. Region (35) was formed. The silicon single crystal substrate may be manufactured by anisotropic etching. It is important that this corner has an extremely sharp vertical surface at 90 ° to the top surface of the substrate. The height of this convex area (35) is 0.5-4 μ
m, for example, 1.5 μm.

Then, as shown in FIG. 2 (E), the convex region (35) having a rectangle has a channel forming region on the (100) plane (<
100> direction (40)) and also the parasitic channel prevention surface (010)
The surface (<010> direction (40 ')).

The fixed charge density on all of these sides can be reduced to about 1/2 of that of other (110) and (111) crystal planes.

Silicon nitride (33) having a masking action against oxidizing gas was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. After that, as shown in FIG. 2A, the silicon nitride was partially removed by the second photomask ().

After the P-type impurity for forming a channel cut is doped in the removed region, a field insulator (3) is formed.
Embedded in a thickness of 0.5 to 2 μm to obtain the state of FIG. 2 (A).

As shown in FIG. 2B, this silicon nitride film (33)
Then, a film (2) for forming a gate insulating film was formed on the semiconductor substrate (1) having the convex region (35).

The channel forming regions (6) and (6 ′) are formed into a gate insulating film.
Before or after the formation of (2), it was formed on at least the side surface of the rectangular convex region by a method such as an ion implantation method. That is, since the channel forming regions (6) and (6 ') are the case of the N channel type MIS FET in this embodiment, the threshold voltage is controlled, and the channel forming regions (6') and (6 ') are not necessary for the enhancement type MIS FET. Controls the dose amount to +0.1 to + 1.0V for mull-off, for example + 0.5V, and -0.1 to -1.0V for normally-on for depletion type MIS FET, for example -0.5V. And fulfilled.

These were used as channel formation regions, and one or both of the channel formation regions (6) and (6 ′) were automatically formed using a photomask. Two or three types of impurities may be added twice as a filling channel type. In these, impurities were positively added to the side surfaces of the convex region (35) on the (6) and (6 ′) sides. For example, ion implantation (38), (38 ') from the lateral or oblique direction was doped with boron or boron and arsenic.

In this rectangular convex region (35) where no channel is formed ((36), (36 ') in FIG. 2 (E)), a parasitic channel is easily generated, and a source or drain is formed.
Between the (4) and the drain or source (5), (5 ')
In order not to generate a negative current, boron was added at a higher concentration than that of the substrate, that is, the convex region, and the channel was cut so that the off state was always achieved. That is, the ion implantation was performed obliquely or laterally with respect to the plane on the substrate.

These ion implantations not only damage the substrate but also the insulating film (33) or (2), so that the whole of them is annealed by heat or intense light, and the semiconductor substrate (1) Region (35) was single crystallized.

This ion implantation step may be carried out in the step shown in FIG. 2A or the step shown in FIG. 2B.

The silicon oxide film (2) is removed to form another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide, or a composite film thereof with a thickness of 100 to 500 Å, and a gate insulating film ( 2) May be.

Next, as shown in FIG. 2B, a window for forming a source or drain electrode (contact) was formed in the gate insulating film (2) by a third photomask (). After the surface of the insulating film is sufficiently cleaned, a low pressure vapor phase method (LPCVD method) is applied to the substrate so that conductivity type impurities, for example, N type impurities (phosphorus) are 1 to 10 × 10 ²⁰ cm ^−3. To the concentration of
Coated silicon semiconductor (silicon) coating (7) 0.5 to 2.5
It was formed on the entire surface to form a gate electrode and other leads with a thickness of μm. This impurity doping is not performed at the same time as the film formation, but is subjected to the following anisotropic etching to leave the portions (8) and (8 ') that will become the gates, and after this film (7) is diffused. Method or injection method.

The coating (7) may be a conductor such as a metal or an intermetallic compound, instead of the impurity-doped silicon semiconductor. Further, it may be a multilayer film of a P ⁺ or N ⁺ type semiconductor and a metal or a metal compound, particularly Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ).

Thus, FIG. 2 (B) was obtained.

Next, as shown in FIG. 2 (C), a photoresist (
For example, OMR-83 manufactured by Tokyo Ohka Co., Ltd.) was used for selective coating, and then anisotropic etching was performed. With respect to this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, instead of an isotropic etching method using a conventionally used solution.

Specifically, by using a microwave of 2.45 GHz, a reactive gas for etching, such as nitrogen fluoride (N
F ₃ ), carbon fluoride (CF ₄ ) are chemically activated, and the fluorine shower which is plasmatized in an atmosphere with a vacuum degree of 0.1 to 0.001 torr, especially 0.005 to 0.01 torr is perpendicular to the upper surface of the substrate. It was made to flow in the same direction and bias was applied to the substrate to make side etching as low temperature etching.

As a result, when the flat surface portion of the coating film (7) on which the photoresist is not formed is completely removed, the coating film (8) on the side surface which is the corner portion of the convex region (35). , (8 ') is
Since the effective thickness is thicker when viewed from above, it remained as vertical rectangular or triangular gate electrodes (18) and (18 ') around the sides. Furthermore, the contact (11) of the first impurity region of the drain or source (5), (5 ') (corresponding to (15) in Fig. 2D).
And its lead (12) were N ⁺ -type in this example and could be left as an electrode lead. Gate electrode (18), (18 ')
Does not exist over the upper surface of the convex region (35), and its width is not a width determined by photolithography, but can be determined by the thickness of the side surface of the film (7) and the degree of anisotropic etching. .

Thereafter, the whole of these is oxidized to form a silicon oxide insulating film (47) on the convex region, the bottom of the semiconductor substrate and the surfaces of the gate electrodes (18) and (18 ') to a thickness of 300 to 2000Å. did. Next, this rectangular or triangular gate electrode (18), (1
Using 8 ') as a mask, impurities are added in an oblique direction as shown in (37) and (37'). In the case of using the in-implantation method, since it is an N-channel type, arsenic can be reduced to 0.
It was added to a concentration of 5 to 5 × 10 ¹⁵ cm ^−2, for example, 1 × 10 ¹⁵ cm ⁻² .

Then, the convex regions (35) are formed by using the gate electrodes (18), (18 ') or the end portion (44) of the insulating film (47) thereon as a mask.
The upper part of the has a source or drain (4) and its end (4
4 ') roughly coincides with the edge (44) of the gate electrode, and the inside (44'') is the channel forming region more than this edge (44').
It is formed at a position close to the drain or the source when viewed from (6 '). Thus a source or drain (4) is formed.

On the other hand, the end portion (48 ') of the drain or source (5') is formed so as to substantially coincide with the end portion (48) of the other gate electrode (18 '), and is deeper than that position. (Position near source or drain) Inside drain or source (48``)
Is formed.

Thus, the source or drain (4) and the drain or source (5), (5 ') are self-aligned by the ends of the gate electrodes (18), (18'). The position is determined, and in particular, the positioning is performed by ion implantation from an oblique direction.

Then, the gate electrode (18 ') is extended as a lead (38') as shown in FIG. 2 (E), and another gate electrode (18 ') is formed.
(18) is connected to the contact (11) through the lead (12).

In FIG. 2D, the first impurity regions (15), (15 '), the second impurity regions
The impurity region (14) may be formed to make ohmic contact. However, these impurity regions change the accelerating voltage when forming the source or drain (4), the drain or source (5), (5 '), so that a low dose amount can be obtained at a high accelerating voltage. Addition to high dose region with strong accelerating voltage, eg 1 × at 100 KeV
^{10 14 cm -2, 3 × 10} 14 cm -2 at 50KeV, 2 × 10 ¹⁴ cm at 30KeV
It can be formed at once by changing the value to ^-2 .

In FIG. 2 (C), the rectangular or substantially triangular gate electrodes (18) and (18 ') have a bottom width of 0.1 to 1 .mu.m.
Although the thickness is as small as m, the layer is extended as leads (38) and (38 ') on the field insulating material according to the design needs, and the width of the lead is 1 to 1. It goes without saying that it may be as wide as 10 μm and may be connected to the electrode lead of another MIS FET provided on the same substrate, or may be electrically connected to another capacitor, resistor or the like.

In the drawing, selective growth of tungsten (24), (1
3) Conduct the aluminum lead (24 '), (12'), (38 '').
Was formed and multilayer wiring was performed.

In FIGS. 2D and 2E, the inverter, that is, the power source side (38 ''), the load (10), the outputs (24) and (24 '), the driver (1
0 ') and the ground side (12), (12'). After that, an interlayer insulating film may be formed over the entire surface, the output may be connected to the second impurity region (14), and the current may be connected to the electrode (12 ') by providing a multilayer wiring.

The channel length as a MIS FET is the end (44) of the source or drain (4), or (44 '') and the end (48) of the drain or source (5), (5 '). It can be decided by the difference between ') or (48'').

Thus, the source and the drain are vertical channel type so-called vertical and horizontal type MIS FETs, while facilitating contact with the outside above the convex region and the bottom surface of the substrate.
And could be. Therefore, it is easy to form an electrode (contact) with respect to the source and drain, and the channel length is as small as 0.1 to 1 μm.
More precise control manufacturing became possible.

As is apparent from the above embodiments, the present invention is directed to the vertical rectangular or triangular gate electrodes (18) and (18 ').
Is adjacent to the convex region and the mechanical strength is increased, but the interface state (positive due to the presence of dangling bonds of silicon is used by using the (100) plane in the channel formation regions (6) and (6 '). (Due to the generation of electric charge)
Was reduced.

The other side surface of the rectangular convex region (see FIG. 2)
In (36) and (36 ')) of (E), the side surface of the (36) and (36') was also the (100) plane so that the generation of positive fixed charges was minimized. Further, boron was added thereto as shown in (36) and (36 ') of FIG. 2 (E) to form a channel cut.

Thus, the vertical / horizontal micro-channel (μ-channel) MIS FE has a precisely controlled channel length and reduces the area of the entire transistor substrate.
You can make T.

FIG. 1 shows two MIS FEs in a rectangular convex area.
Although T is formed as an N-channel type, another MIS FET is formed as a P-channel type in the other part separated by a field insulator, and an MIS structure (complementary structure) is formed as an LSI,
VLSI can further facilitate the present invention.

[Second Embodiment] FIG. 3A shows another embodiment to which the present invention is applied. The corresponding electric circuit is shown in Fig. 3 (C). FIG. 3A shows that two MIS FETs (1
0), (10 ') and two capacitors (10), (10') are respectively connected in series, and two 1Tr / Cells are provided as a pair. That is, in the convex region (35), the channel formation region (6),
(6 '), and the source or drain (4) and the high-concentration second impurity region (14) are formed on the upper part thereof.

Further, a field insulator (3) is provided on the periphery of the bottom of the semiconductor substrate (1), and the first impurity region (1
5), (15 ') and the drain or source (5), (5'),
As the gate electrodes (18), (18 '), the gate insulating films (2), (2'),
Two MIS FETs (10) and (10 ') were constructed. The lower electrodes (21) of the capacitors (20), (20 ') are connected (11), (11') to the first regions (15), (15 ') of N ⁺ that make this ohmic contact. , (21 ′), dielectrics (22) and (22 ′), and upper electrodes (23) and (23 ′) are further provided thereon, thereby forming capacitors (20) and (20 ′).

In FIG. 3A, (14) is a bit line, and (18) and (18 ') are word lines, and a memory system having a structure in which two pairs of 1Tr / Cell are paired is provided. With this structure, the convex region (35) can be shared by the two MIS FETs (10) and (10 '), and the dielectrics (22) and (22') are different from the gate insulating film. It can be a different high dielectric constant material, such as tantalum oxide, titanium oxide, silicon nitride, barium titanate. Also, there is a feature of a stacked memory cell in which these dielectrics and electrodes can be stacked on each other to increase the overall capacitance.

In this embodiment, the gate electrodes (18),
The outer periphery of (18 ') is insulated by the oxide interlayer insulator (17), but its thickness is 0.1 to 1.0 μm, and the first impurity regions (15) and (15') are The connection with the lower electrodes (21) and (21 ') of the capacitors (20) and (20') formed electrodes (contacts) by selective growth of tungsten (13) and (13 ').
Therefore, the lower electrodes (21) and (21 ′) are made of tungsten silicide.

As described above, when the MIS FET of the present invention is used, the contact can be made constant by connecting it to the drain or the source or the first impurity region even if the depth of focus of the stepper is shallow, and the contact blurs. Precise addition can be prevented. And it can be obtained with a sufficient area margin. That is, the first impurity regions (15) and (15 ′) may be formed within the range of mask alignment accuracy when the holes for the electrodes are formed. If the accuracy is good, the area required as the drain or the source can be reduced. The channel length could be precisely prepared as shown in Example 1 regardless of the contact formation region and without increasing the size of the MIS FET viewed from the substrate.

An interlayer insulating material such as polyimide may be formed and the third conductor wiring may be formed on the upper surface thereof.

The cell area could be formed extremely small and high density. Example 1 was used for manufacturing steps not shown in this example.

[Embodiment 3] A longitudinal sectional view of this embodiment is shown in FIG. This is another embodiment of the memory cell, and a corresponding circuit diagram is shown in FIG.

As is apparent from the drawing, a convex region (35) is provided on the surface of the semiconductor substrate, and the gate insulating films (2), (2) are provided at the corners around the side and the bottom of the substrate. ') Are provided, and the gate electrodes (18) and (18') are further formed in a pair. By using a part of the gate electrode such as silicon as a mask, the drain or source (5),
(5 '), source or drain (4) was formed.

Further, in order to form a channel as a recessed channel type, boron doped (46), (46 '), arsenic doped recessed channels (6), (6') are changed to their channel length (6 ) And (6 ') are precisely controlled by the self-alignment method. In this way, the μ channel MIS FETs (10) and (10 ′) are provided in a structure of two pairs.

Next, the contact openings (9), (9 ') provided in the first impurity regions (15), (15') are provided in the same manner as in the first embodiment. Lower body electrode (2
0) and (20 ′) are formed by forming doped silicon to a thickness of 0.1 to 1 μm. Tantalum oxide films (22) and (22 ') were formed on the upper surface by sputtering to a thickness of 100 to 500 Å. In addition, silicon nitride or silicon oxide described in the second embodiment may be used. It was made by nitriding or oxidizing the lower electrode. After this, the counter electrode (23), (23) ') is provided on this surface by metal or semiconductor, and after photoetching this,
The capacitors (20) and (20 ') were used.

Thus, the upper electrodes (23), (23 ') of the capacitors (20), (20') and the dielectrics (22), (22 ') and the lower electrodes (2
We were able to fabricate 1) and (21 ') as stacked memory cells. In addition, this capacitor is formed on the field insulating film (3) or in the convex region (35) and the gate electrode (1
8), (18 ') can be provided over the entire area of the semiconductor substrate, and the cell area can be made high so that it can be seen as a capacitor except for the contact portion when viewed from the entire semiconductor substrate.

A multilayer wiring (24 ') is provided on the second impurity region (14) via a contact (24) on the interlayer insulating film (17) as a word line, and the gate electrodes (18), (18') are formed. ) Is used as a bit line to form a pair of vertical channel type, source, and lateral drain type MIS FETs in a self-aligned manner, which contributes to miniaturization, higher density, and improved reliability. It was effective.

Also in this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24 ') and the word line is the gate. It could be constructed as a part of a 1Tr / cell memory system which is paired with electrodes (18) and (18 ').

Since these are integrated N-channel MIS FETs, they have a plurality of convex regions on the same substrate, and some of them are complementary (P-channel MIS FETs).
Complementary type) It is effective to use an integrated circuit.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to form a floating gate type nonvolatile memory.

In the above three embodiments, the material forming the first region and the material forming the vertical rectangular or substantially triangular gate electrode (18) are of the P ⁺ or N ⁺ type conductivity type. The material having the same main component as that of the substrate having the impurity doped therein, for example, silicon is mainly described.

However, they may be a mixture or compound (MoSi ₂ , WSi ₂ , TiSi ₂ ) of silicon and Mo, W, Ti, and may have an intrinsic, P ⁺ -type or N ⁺ -type semiconductor in a multilayer structure. However, it goes without saying that it may have a multilayer structure of a semiconductor such as silicon and Mo, W, platinum or a compound thereof.

In the present invention, the semiconductor substrate is mainly made of single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or may be a polycrystalline, amorphous or semi-amorphous semiconductor.

Further, surface diffusion is used for the channel formation region.
Instead of the MIS FET, the embedded channel type may be used. Alternatively, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[0077]

As is apparent from the above embodiments, according to the present invention, impurities are added obliquely or laterally to adjust the channel length by the gate electrode to the source or drain and the drain or source in a self-aligned manner. It was possible to form a source and a drain by performing precise control by forming the source and the drain.

Further, by making the convex side surface on which the channel is formed the (100) plane, generation of interfacial charge is reduced and anisotropic etching can be easily performed.

The gate electrode has a structure in which the side portion of the gate electrode is in contact with the convex-shaped first region so as to be mechanically reinforced so as to improve reliability.

The threshold voltage of the channel formation region has a structure in which an impurity such as boron is provided in the upper portion of the semiconductor obliquely or laterally, and the structural characteristics thereof are 0.1 to 1 μm. It has a great feature that an extremely short channel (μ channel) MIS FET having a frequency response speed of 1 to 10 GHz depending on the channel length can be implemented without using a technique such as electron beam exposure as an absolutely necessary condition.

[Brief description of the drawings]

FIG. 1 shows a longitudinal sectional view of a conventionally known MIS FET.

FIG. 2 is a vertical cross-sectional view showing the manufacturing process and structure of the embodiment of the present invention.

FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which a pair of 1Tr / Cell memories is provided.

[Explanation of symbols]

1-semiconductor substrate 3-field insulator 4-source or drain 5,5 '... drain or source 6,6'-channel formation region 10,10 '・ ・ ・ Insulated gate type field effect transistor (MIS F
ET) 14 ... second impurity region 15,15 '... first impurity region 18,18' ... gate electrode 20,20 '... capacitor 〜 ・ ・ ・ photomask pattern -Pulling treatment 37,37 '... Ion implantation direction 38,38' ... Ion implantation direction

Claims (16)

[Claims] 1. A single crystal semiconductor substrate, which is provided upright on the surface of the semiconductor substrate, and which is substantially (1
00) A rectangular parallelepiped single crystal convex region having a pair of first side faces parallel to each other and having a crystal face or a crystal face equivalent to the crystal structure of the single crystal convex region, and a pair of second side faces parallel to each other. A pair of gate electrodes provided on each of the pair of first side surfaces via a gate insulating film, and a predetermined pair of gate electrodes provided inside the semiconductor substrate and outside the convex region along the lateral direction. A pair of first impurity regions having a conductivity type, a second impurity region having the same conductivity type as the first impurity region provided on the upper surface of the convex region, the first impurity region, and the first impurity region A pair of insulated gate field effect semiconductor devices having a pair of channels provided between the pair of field effect semiconductor devices and the second impurity region, the pair of field effect semiconductor devices being independent of each other, and the first impurity region and the first impurity region. The second failure Leakage current in order to prevent the flow, wherein the the pair of second side are respectively added impurity insulated gate field effect semiconductor device between the object region. 2. The pair of first impurity regions according to claim 1, wherein each of the pair of first impurity regions includes a first low concentration impurity region and a first low concentration impurity region.
And a high-concentration impurity region of the insulating gate type field effect semiconductor device. 3. The insulated gate field effect semiconductor device according to claim 2, wherein a lower end surface of the gate electrode is located above the first low concentration impurity region. 4. The insulated gate field effect semiconductor device according to claim 2, further comprising a pair of first electrodes which are in ohmic contact with the high concentration impurity region of the first impurity region. 5. The pair of second impurity regions according to claim 1, wherein each of the pair of second impurity regions includes a second low concentration impurity region and a second low concentration impurity region.
And a high-concentration impurity region of the insulating gate type field effect semiconductor device. 6. The insulated gate field effect semiconductor device according to claim 5, wherein the upper end surfaces of the pair of gate electrodes are offset from both side surfaces of the second low concentration impurity region. 7. The insulated gate field effect semiconductor device according to claim 6, further comprising a pair of second electrodes that are in ohmic contact with the high concentration impurity regions of the second impurity regions. 8. The insulated gate field effect semiconductor device according to claim 1, wherein the pair of first impurity regions are provided at a predetermined depth inside the semiconductor substrate. 9. The insulated gate field effect semiconductor device according to claim 1, wherein the second impurity region is provided with a predetermined depth from an upper surface of the convex region in a downward direction. 10. The insulated gate field effect semiconductor device according to claim 1, wherein the pair of transistors are connected to each other. 11. The insulated gate field effect semiconductor device according to claim 1, wherein the channel region is embedded in the convex region with a predetermined length from the first side surface. 12. An insulating gate type field effect semiconductor device having a pair of insulating gate type field effect transistors and a pair of capacitors, wherein the pair of transistors is formed on a semiconductor substrate and a main surface of the semiconductor substrate. A convex region having a pair of first side faces and a pair of second side faces that are parallel to each other, and a pair of first impurity regions having a predetermined conductivity type that are provided on the semiconductor substrate. A second impurity region provided in the convex region and having the same conductivity type as that of the first impurity region; and a second impurity region provided on the second impurity region and having the same conductivity type as that of the second impurity region. A third impurity region having an impurity concentration higher than that of the second impurity region, and a pair of gate electrodes provided on each of the pair of first side faces of the convex region via a gate insulating film, The above A pair of channel regions provided between the second impurity region and the pair of third impurity regions, and the same conductivity type as the first impurity region, and the impurity concentration is the first impurity region. A higher impurity region, which is provided in the semiconductor substrate and has a pair of fourth impurity regions having an end face in contact with the first impurity region; and an end portion of the gate electrode, The end surface of the fourth impurity region and the end portion of the gate electrode are defined in a substantially self-aligned manner so as to be close to the semiconductor substrate at a portion substantially farthest from the film, and In order to prevent a leak current from flowing between the impurity region and the second impurity region, an impurity is added to each of the pair of second side surfaces of the convex region, and the pair of capacitors includes the pair of second capacitors. 4 impurity regions A pair of first electrode layers connected to each other, a pair of second electrode layers, and a pair of insulating layers provided between the first electrode layer and the second electrode layer, The insulated gate field effect semiconductor device, wherein the third impurity region is connected to a bit line and the gate electrode is connected to a word line. 13. The semiconductor substrate according to claim 12, wherein an impurity having a predetermined concentration is added to the semiconductor substrate, the impurity concentrations of the first impurity region and the second impurity region are substantially the same, and Unlike the impurity concentration,
The insulated gate field effect semiconductor device, wherein the impurity concentration of the pair of second side surfaces is a value between the impurity concentration of the semiconductor substrate and the impurity concentrations of the first and second impurity regions. . 14. The impurity concentration of the second side surface of the convex region according to claim 13, wherein the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ to 2 ×.
An insulated gate type field effect semiconductor device, characterized in that it is 10 ¹⁸ cm ^-3 . 15. A single crystal semiconductor substrate, which is provided upright on the surface of the semiconductor substrate, and which is substantially (1
00) A rectangular parallelepiped single crystal projection having a pair of first side surfaces parallel to each other and having a crystal plane, or a crystal surface equivalent to the crystal structure of the single crystal projection region, and a pair of second side surfaces parallel to each other. A region, a pair of gate electrodes respectively provided on the pair of first side faces via a gate insulating film, and provided in the semiconductor substrate, and laterally offset from the side faces of the convex region along the lateral direction. A pair of first impurity regions having a first conductivity type; a second impurity region having the same conductivity type as the first impurity region, the second impurity region being provided on an upper surface of the convex region; In a pair of insulating gate type field effect semiconductor devices having a pair of channel regions provided between an impurity region and the second impurity region, the semiconductor substrate is doped with an impurity of a predetermined concentration, The impurity region and The impurity concentration of the second impurity region is substantially the same, and different from the impurity concentration of the semiconductor substrate, the impurity concentration of the pair of second side surfaces in the convex region is the same as the impurity concentration of the semiconductor substrate. An insulated gate field effect semiconductor device having a value between the second impurity region and an impurity concentration. 16. A single crystal semiconductor substrate, a convex region provided upright on a surface of the semiconductor substrate, a gate electrode provided on a side surface of the convex region through a gate insulating film, and the inside of the semiconductor substrate. And a first impurity region having a predetermined conductivity type located outside the convex region along the lateral direction and having the same conductivity as the first impurity region provided on the upper surface of the convex region. An insulating gate type field effect semiconductor device comprising: a second impurity region having a mold; and a channel provided between the first impurity region and the second impurity region, wherein The edge of the impurity region is
An insulated gate field effect semiconductor device, which is formed inside a semiconductor substrate.