JPS60126859A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the areas of each diffusion region, to which the same potential must be applied, and to fine the device by making two regions having mutually reverse conduction types adjoin together in a surface section and directly coating adjacent section with a metallic film. CONSTITUTION:A p type well 2, an n type well 12, element isolation insulating films 3, gate oxide films 7, gate electrodes 8, gate protective insulating films 15 and phosphorus added Si oxide films 16 are formed on an Si substrate 1', and arsenic ions are implatned to the well 2 and boron ions to the well 12. An Si nitride film 17 and an Si thin-film 18 are deposited, and the surface is etched vertically. Phosphorus is implanted to the well 12 and boron to the well 2 to form a p type high-concentration diffusion region 4 and an n type high-concentration diffusion region 19. An Al film is evaporated on the whole surface, and the whole is processed up to desired constitution. Both the p type high-concentration region 4 and an n type source diffusion region 5 and both a p type source diffusion region 14 and the n type high-concentration region 19 are connected in the surface at that time.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and in particular to an ultra-fine complementary insulated gate electric field capable of forming a well ground electrode in a self-aligned manner in relation to a gate electrode of an in-well transistor. The present invention relates to effect transistors or ultrafine nonvolatile memory transistors using wells.

[Background of the invention]

One conventional complementary insulated gate field effect transistor (hereinafter referred to as CMQS) - transistor. ), a high concentration diffusion region of the same conductivity type as the well for taking out the well ground electrode, and a diffusion region of the opposite conductivity type to the well constituting the source/drain of the transistor in the well were independently formed. In other words, Figure 1 shows the conventional C OS
In the cross-sectional view showing the transistor part, ■ is an Nl silicon substrate, and 2 is a P-type well region. In the well 2, a p-type cavity dense impurity diffusion region 4 is formed using a thick filled oxide film 3 for element isolation as a mask. A source region 5 and a drain region 6 of the transistor are formed of n-type high impurity diffusion regions. Source diffusion region 5 and drain diffusion region 6 are formed by masking gate oxide film 7 and gate electrode 8.

9 is a surface stabilizing insulating film. The p-resistant high concentration impurity diffusion region 4 and the n-type source diffusion region 5 are connected by a metal electrode 10 and fixed to the ground potential. The drain diffusion region 6 is connected to the drain diffusion layer of a P-channel transistor constituting a CMOS transistor by a metal electrode 11.
The output terminal is the same as that of a CMOS transistor. In the side OS transistor of the conventional structure as shown in the partial cross-sectional view of FIG. 1, the diffusion region 4 providing the well potential was constructed completely independently of the source diffusion region 5. That is, P giving the well potential
The n-type source region 5 is used to form the mold cavity impurity concentration diffusion region 4.
The presence of the filled oxide film 3 region for isolation from the oxide film is essential, and this has been a drawback in terms of miniaturization. By reducing the number of high-concentration diffusion regions 4 that provide well potential (for example, replacing the high-concentration diffusion region 4 provided for each transistor in one well with one high-concentration diffusion region per well). ) The disadvantages of miniaturization are alleviated. However, in this case, since the distance from the p-type diffusion region 4 differs depending on the configuration position of the transistor in the well 2, a drawback arises in that the threshold voltage value of each transistor differs due to the influence of the well resistance.

Another drawback of the conventional structure is that although the same potential (ground, potential) is applied to the p-type diffusion region 4 and the n-type source diffusion region 5, holes are made separately in each diffusion region, and the wiring electrode Based on connecting with. Sunawafu desired location, 2
When each opening is provided, it is necessary to ensure a margin for positional deviation, which results in an increase in area. Furthermore, if the area of the opening is reduced to aim for a reduction in area, the number of holes required to process the hole increases, resulting in an increase in the probability of connection failure.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to dramatically reduce the area occupied by each diffusion region within a well that has different conductivity types and is to be given the same potential. It is in. Furthermore, the present invention reduces the number of electrode connection holes and the area occupied by the combined allowance.
The purpose of this invention is to provide an optimal structure for ultra-miniaturization of CMOS transistors and the like.

[Summary of the invention]

In order to achieve the above object, the present invention configures a diffusion region 4 of the same conductivity type as a well that provides a well potential in a self-aligned relationship with a source diffusion region 5 of a transistor in the well. That is, a conventionally known self-aligned gate transistor is one in which a source diffusion region 5 and a drain diffusion region 6 are configured in a self-aligned relationship with respect to an end of a gate electrode 8. However, in the present invention, a diffusion region 4 that provides a well potential is constructed. It is also constructed in a self-aligned relationship with the end of the gate electrode 8.

That is, the diffusion region 4 is formed apart from the gate electrode 8 by the thickness of the insulating film provided on the gate electrode 8. In order to realize the self-aligned structure described above, in the present invention, after forming the gate electrode and its sidewall insulating film, a diffusion blocking film such as a silicon nitride film is applied in a self-aligned manner to the sidewall insulating film. Leave it on selectively. The above-mentioned selective leaving of the diffusion blocking film is achieved by controlling the thickness of the thin film of silicon or the like deposited on the diffusion blocking film and by controlling the amount of anisotropic etching. What is necessary is to control the thickness of the thin film of silicon or the like. That is, by processing using the remaining silicon thin film as a mask, eight selective diffusion prevention films can be left in self-alignment with the gate electrode.

The gas that forms each of the diffusion regions 4 and 5 before and after selectively leaving the diffusion prevention film described above should give a well potential if each of the diffusion regions 4 and 5 is formed before and after removing the selectively left diffusion prevention film. Diffusion region 4 is also formed in self-alignment with gate electrode 8. the above.

After forming two diffusion regions having different conductivity types, metal wiring may be directly provided on the surface of each diffusion region, or the surface of each diffusion region may be silicided to electrically connect them.

In the structure of the present invention, two diffusion regions 4 and 5 having different conductivity types are in contact with each other, but CMOS
In the case of a semiconductor device, such as a transistor, in which an equal potential is applied to both sides, no trouble occurs. Furthermore, when forming diffusion layers having different conductivity types, the formation of one diffusion layer acts in the direction of compensating or eliminating the other diffusion layer formation region, but the diffusion coefficient of the impurity forming each diffusion layer difference,
No problem will arise if the impurity material selection and manufacturing conditions are set taking into consideration the implantation energy conditions for impurity ion implantation.

The present invention will be explained in more detail below using examples. For convenience of explanation, the explanation will be made using drawings, but please note that important parts are shown enlarged.

[Embodiments of the invention]

Embodiment 1 FIGS. 2 to 4 are diagrams showing an embodiment of a semiconductor device according to the present invention, in which a p-type well region 2, an n-type well region 2 and an n-type well Area 12
, and an element isolation insulating film 3 were formed. Element isolation insulating film 3
was formed by the buried insulating film method, but the conventional selective oxidation method (
It may be based on the LOCO5 method). After forming well regions 2, 12, etc., a gate oxide film 7 with a thickness of 15 nm, a gate electrode 8 made of tungsten (W), and a silicon oxide film doped with a slight amount of phosphorous are formed according to a known MOS transistor manufacturing method. Gate protection insulating film 1
5 was formed. The gate protection insulating film 15 was processed simultaneously with the etching of the gate electrode 8 using the same mask. After processing the gate electrode 8, a silicon oxide film 16 slightly doped with phosphorus was deposited on the entire surface to a thickness of 0.2 μm. Subsequently, reactive sputter etching is performed to advance the etching in a direction perpendicular to the surface of the silicon substrate to remove the silicon oxide deposited film deposited on the flat areas, leaving the silicon oxide deposited film 16 only on the side walls of the gate electrode 8. Ta. Next, the n-type well region 12 was covered with a photoresist film, and arsenic (Aa) was implanted only into the p-type well region 2 by ion implantation. Although the above-mentioned implantation was performed through the gate oxide film 7, the gate electrode 8 serves as a mask for ion implantation, and As ions are not implanted into the silicon substrate portion immediately below it. After the ion implantation, the photoresist film is removed and activation heat treatment is performed to form the n-type source diffusion layer region 5. And a drain diffusion layer region 6 was formed. A P-type source diffusion layer region 14 and a drain diffusion layer region 13 are formed in the n-type well region 12 by a similar manufacturing method using boron (B) ion implantation.
was formed. Thereafter, a 0.15 μm thick silicon nitride film (Si, N4) 17 and a 0.3 μm thick silicon thin film 18 were successively deposited over the entire surface (FIG. 2).

Next, by using the reactive sputter etching method again, etching is performed only in the direction perpendicular to the silicon substrate surface to remove the silicon thin film 18 deposited on the flat portion, and the side wall portion of the silicon oxide deposited film 16 on the side wall of the gate electrode 8 is etched. Only the silicon thin film 18 remained. In this state, the exposed silicon nitride film 17 was removed using hot phosphoric acid (HaPO4) using the remaining silicon thin film 18 as a mask (FIG. 3).

Subsequently, the remaining silicon thin film 18 was completely removed using a hydrazine ('N2 H2) solution.

In the above state, the silicon nitride film 17 remains in self-alignment with the silicon oxide film 16 and the gate electrode 17 with a width of about 0.3 μm from the end of the silicon oxide film 16 on the side wall of the gate electrode 8. Next, the p-type well region 2 is covered with a photoresist film, and phosphorus (P) ions are implanted only into the n-type well region 12. In the above ion implantation, the ions are not implanted into the silicon substrate under the remaining silicon nitride film 17, and the junction depth in the region of the silicon substrate where the silicon nitride film exists is already formed. P-type drain diffusion layer 14 of
Set the driving energy so that it is deeper than the bonding depth. After the ion implantation, the photoresist film was removed and the implanted ions were subjected to activation heat treatment to form a high concentration n-type diffusion layer 19.

B ion implantation was also carried out into the p-type well region 2 according to the above manufacturing process to form a high concentration P-type diffusion region 4. Thereafter, the gate oxide film 7 exposed on the surface of the silicon substrate 1 was removed, and an aluminum (AQ) film was deposited over the entire surface. The above AQ film was processed according to the desired circuit configuration.

Here, a ground electrode 10' is connected to connect the surfaces of the p-type cavity concentration diffusion region 4 and the n-type source diffusion region 5, and an output electrode is connected to the n-type drain diffusion region 6 and the p-type drain diffusion region 13. 11', a power supply electrode 20 was further configured to connect the p-type source diffusion region 14 and the n-type high concentration diffusion region 19. Thereafter, a surface stabilizing insulating film 9 is deposited and holes are formed at desired locations using known techniques.
AQ wirings 21, 22, and 23 were formed by vapor deposition of a second layer of AQ film and wiring processing according to a desired circuit configuration (FIG. 4).

A CMOS transistor with a gate length of 1.0 μm was manufactured using the above manufacturing process.
The dimension up to the end of the heavily doped diffusion region 19 has been reduced to about 1/3 of that of a conventional structure CMOS transistor with the same gate dimension. The above reduction in element size is based on the fact that the high concentration diffusion region 4 or 19 to which the well potential is applied and the source diffusion region 5 or 14 are formed in a self-aligned relationship with the gate electrode 8. In the above configuration, conventional C
Diffusion layers 4 and 5 or 1 in MOS transistor structure
There is no need for the filled oxide film 3 interposed between 4 and 19, contributing to size reduction. Furthermore, since the connection between the respective diffusion layers can be achieved through a common hole, the size required for the alignment margin of each hole in the conventional structure is also reduced. In the CMOS transistor based on this example, the number of openings was reduced by half as well as the element size, and the rate of poor contact between the diffusion layer and the electrode due to poor processing of the openings was also significantly reduced.

Although this embodiment has been described as an example of a two-layer wiring structure using AQ wiring, the effects of this embodiment will not be impaired in any way even if the structure is composed of one-layer wiring, or three or more layers of wiring.

Embodiment 2 FIGS. 5 to 8 are diagrams showing another embodiment of the present invention. In the first embodiment, the source diffusion layers 5 and 14
The ion implantation steps related to the formation of the drain diffusion layers 6 and 13 were omitted, and the deposition of the silicon nitride film 17 and the silicon thin film 18, the reactive sputter etching of the silicon thin film 18, and the remaining adjacent to the gate sidewalls were omitted. Each step of selective etching of the silicon nitride film 17 was carried out using the silicon thin film as a mask. Next, the p-type well region 2 and the region where the p-type drain diffusion layer is to be formed are covered with a photoresist film, and the n-type well region 12 is formed through the gate oxide film 7 exposed on the n-type well region 12. A high concentration of phosphorus was ion-implanted into the interior. In the above ion implantation,
Phosphorous ions are not implanted into the well region 12 under the region covered with the photoresist film, silicon nitride film 17, and gate protection insulating film. After the above ion implantation, the remaining photocondensing disuit film is removed. Thereafter, the implanted ions were subjected to activation heat treatment to form an n-type high concentration diffusion region 19. Next, the areas where the n-type well region 12 and the n-type drain diffusion layer are to be formed are again covered with a photoresist film 24, and boron ions are implanted (FIG. 5). Boron ion implantation was also performed through the exposed gate oxide film 7, but the silicon nitride film 17. Also, boron is not implanted into the p-type well region 2 under the photoresist film 24. After the boron ion implantation, the remaining photoresist film 24 was removed, and the implanted ions were subjected to activation heat treatment to form a P-type cavity concentration diffusion region 4 in the P-type well 2. After the above heat treatment, the silicon nitride film 17 remaining adjacent to the side walls of the gate electrode 8 is removed using a hot phosphoric acid solution, and then the exposed gate oxide film 7 is also removed to expose the silicon substrate surface. A silicon thin film with a thickness of 5 Qnm was selectively removed under the condition. , in the above, the remaining silicon thin film 25
, 26, and 27 are configured to completely cover at least the exposed silicon substrate surface. The silicone above is thin! 1g25.2B and 27 may be formed by a so-called selective deposition method, that is, a method of selectively depositing a silicon thin film only on the exposed silicon substrate surface.

After forming the silicon thin films 25, 26, and 27, the n-type well region 12 was covered with a photoresist film 28 (FIG. 6).

Using the photoresist film 28 as a mask, arsenic is implanted into some regions of the silicon thin films 25 and 26 by ion implantation, the photoresist film 28 is removed, and the n-type source diffusion region 5 and the n-type A drain diffusion region 6 was formed. In the above diffusion mounting formation, the junction depth of the source diffusion region 5 in the P-type well region is approximately 0.2μ.
m, but the junction depth formed by the n-type impurity in the p-type cavity concentration diffusion region 4 was 30 nm or less. After forming the n-type source 5 and drain diffusion regions 6, a photoresist film is selectively left on the p-type well region 2;
A p-type drain diffusion region 13 and a p-type source diffusion region 14 were formed by boron ion implantation in the n-type well region according to the above manufacturing method. After forming the P-type train 13 and the source diffusion region 14, a palladium (Pd) film is deposited on the entire surface,
After heat treatment at about 250°C, Pd and silicon thin film 25,
The reaction of 26.27 resulted in a 0.1 μm thick palladium silicide (P d 2 Si) layer 29, 30, and 31.
was formed. In forming the above Pd and Si layers, the base silicon thin films 25, 26, and 27 are completely consumed by the formation of the Pd25t layer, and the base silicon substrate is also approximately 50 nm from the surface.
About m was consumed. That is, the extremely shallow n-type layer region on the P-type cavity concentration diffusion region 4 and the extremely shallow p-type layer region on the n-type high concentration diffusion region 19 disappear due to the formation of the Pd and Si layers 29 and 31 described above. Ta. Note that Pd does not react with the silicon oxide film 15 and the Pd25t layers 29, 30.3
After forming 1, when the unreacted Pd film is removed with an aqueous solution of iodine (I2-) and ammonium iodide (NH,I), P is removed only in the regions where silicon thin films 25, 26 and 27 were present.
d, the St layer was selectively left (Fig. 7).

After forming the Pd, St layers 29, 30, and 31, the Pd, S
Heat treatment was performed at 500°C to lower the resistance of i. Thereafter, a surface stabilizing insulating film 9 was deposited and holes were formed at desired locations. Tungsten (W) was deposited with the photoresist film used for the openings remaining, and the W film on the photoresist film was removed at the same time as the photoresist was removed. As a result, the W film 32 was left only in the opening. Next, the AQ film is deposited and the wiring is processed according to the desired circuit configuration.
Wirings 20, 22, and 23 were formed (FIG. 8).

As with the first embodiment, the size of the side OS transistor manufactured through the above manufacturing process can be reduced to about 1/3 of that of the conventional structure CMOS transistor. Furthermore, in the CMOS transistor based on this embodiment, extremely shallow junctions (tunnel junctions) formed on the surfaces of the high concentration diffusion regions 4 and 19 of the same type as the wells 2 and 12 can also be easily controlled by forming the silicide layers 29 and 31. It can disappear. Therefore, it was possible to apply voltage to the wells 2 and 12 with better ohmic properties than in the CMOS transistor according to the 16th embodiment.

Based on this embodiment, the CMOS transistor, run, and star have all the features based on the first embodiment, but additional features include source diffusion layers 5 and 14 and drain diffusion layers 6 and 6. and 13 can be made shallower than those of the first embodiment. That is, based on this embodiment, the silicon residue consumed during silicide formation can be compensated for by depositing a silicon thin film of 25°26.27°.

Furthermore, unless a silicide layer is subjected to high-temperature heat treatment after formation, it has poorer reactivity with the substrate silicon than a metal film such as AQ. Therefore, it is more stable than the structure in which the surface of each diffusion layer is directly covered with a metal film as in the first embodiment, and the junction depth of each source/drain diffusion layer 5. In this embodiment, silicon thin films 26 and 27 were deposited to compensate for the silicon consumed during silicide formation, but the above deposition may be omitted if desired. You may. Furthermore, in this embodiment, the formation of the source/drain diffusion layers 5, 14 and 6, 13 is performed using the silicide layers 29, 3.
This was carried out before the formation of 0 and 31, but after the silicide layer was formed, ions were implanted into the silicide layer, and the source was
A drain diffusion layer may also be formed. In this case, the shallower 10
An extremely shallow junction on the order of nm can be obtained.

〔Effect of the invention〕

According to the present invention, the diffusion region to which a well potential is to be applied can be constructed in self-alignment with the gate electrode of the transistor in the well, so that the element dimensions can be significantly reduced compared to conventional structures. The above reduction degree is 1/3 or less of the conventional structure under the condition that the gate length is 1.0 μm.

Another feature of the present invention is that the diffusion region providing the well potential can be directly connected to the source diffusion layer, so the number of connection holes can be halved, which also has the effect of halving conduction failures caused by the hole-opening process.

Although the present invention is most suitable for ultra-miniaturization of CMOS transistors, its application is not limited to CMOS transistors. That is, the present invention can also be applied to a semiconductor device having a well structure, such as an electrically rewritable non-volatile semiconductor memory device. Furthermore, the present invention can be applied not only to semiconductor devices configured with two types of wells as described in the above embodiments, but also to semiconductor devices configured with one type of well.

In the embodiments of the present invention, the case where Pd2Si is used as the silicide layer is described, but other silicide layers, ie, T
i, Zr, Hf, Vt Nb.

The effects of the present invention do not change at all even if it is a silicide layer of a high melting point metal such as Ta, Cr', Mo, W, Go, Ni, and Pt, or a transition metal, or a film of these metals themselves. In this case, since the silicon film thickness consumed during the formation of each silicide differs depending on each metal, the film thickness of the compensating silicon thin film may be controlled as desired.

[Brief explanation of the drawing]

FIG. 1 is a partial cross-sectional view of a conventional CMOS transistor, FIGS. 2 to 4 are cross-sectional views showing the manufacturing process of the first embodiment of the present invention in order of process, and FIGS. 5 to 8 are cross-sectional views of a conventional CMOS transistor. FIG. 7 is a cross-sectional view illustrating the manufacturing process of another example in order of process. 1.1'...Substrate, 2,12...Well region, 3.
...Insulating film, 4...Impurity region of the same conductivity type, 5, 6.
... Impurity region, 7... Gate insulating film, 8... Gate electrode, 9... Insulating film, 10.11... Electrode, 13
．． 14... Impurity region, 15... Gate protection insulating film, 16... Insulating film, 17... Insulating film, 18... Silicon thin film, 19... Same conductivity type impurity region, 20...
... Electrode, 21, 22° 23... Wiring, 24... Photoresist, 25, 26° 27... Silicon thin film,
28...Photoresist, 29.30,31...Palladium silicide layer, depth 1 Figure bottom 2 Figure %3 Figure ¥15 figure height 6 Figure

Claims (1)

[Claims] 1. First conductivity type region inner number: In a semiconductor device having at least a second region formed and having a conductivity type opposite to the above region, the first and second regions are formed. are adjacent to each other at least in their surface portions, and the adjacent surfaces are directly covered with a metal film. 2. In the semiconductor device according to claim 1, the metal film is made of a high melting point metal or a transition metal, or
Or a semiconductor device comprising a silicon compound of the above-mentioned high melting point metal or transition metal.