JPH0568745B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention belongs to the field of image processing using various sensors, and mainly relates to television cameras (hereinafter referred to as television cameras). It is used for image measurement to automate the appearance inspection of products and save labor.

(Prior Art) Conventionally, there are two types of data transfer methods between an image memory and a microprocessor, one of which is processor-controlled memory access (hereinafter abbreviated as PCMA), which focuses on software processing. ), and the other is direct memory access (hereinafter abbreviated as DMA), which can be speeded up by hardware processing. the former
In the case of PCMA, as shown in Figure 2, the microprocessor 11 outputs the bus switching signal e according to the program procedure stored in the ROM in synchronization with the timing when the scanning signal of the television camera indicates that the vertical blanking period is in progress. After switching the multiplexer 9 to the B side, arbitrary data in the image memory 10 is transferred to the RAM 13 via the bus gate 21. In this case, since the amount of data required for image processing becomes enormous, the load factor of the microprocessor 11 increases, there are variations depending on the program processing procedure, and it takes a long time to transfer the data. In the case of the latter DMA, the microprocessor 11 initializes the DMA control unit 15 with an arbitrary starting address in the image memory and the number of words to be transferred, as shown in FIG. setting, and then send the DMA to the DMA control unit 15.
Start DMA transfer by outputting start signal l. That is, after starting DMA transfer, the DMA control unit 15
The HLD request signal j is output from the microprocessor 11 to the microprocessor 11, and after acquiring the bus control right, it outputs the bus switching signal e to the image memory 10, switches the multiplexer 9 to the B side, and specifies the data in the image memory 10. For the specified number of words from the first address,
The data is transferred to the RAM 13 via the DMA bus gate 23. Here, the DMA address bus m output from the DMA control unit 15 must be a continuous bus that changes sequentially in a counter manner starting from the designated start address. Therefore, compared to the conventional PCMA, it is effective for high-speed block transfer of data in a continuous address space, and the transfer time is significantly shortened. However, as shown in Fig. 4, the handling of image data required by image processing technology requires processing of a group of data existing within a necessary window 24 (window frame) among the image data constituting one screen. Almost. This means that, when viewed from the address space of the image memory, target image data is currently scattered in discontinuous address spaces. Therefore, it is impossible to transfer data existing in discontinuous address spaces all at once, and the DMA transfer is performed every time the address changes discontinuously.
It is necessary to initialize the start address and the number of words to be transferred in the control unit 15, which has the disadvantage that the software processing procedure becomes complicated and the transfer speed is significantly reduced.

(Problems to be Solved by the Invention) In order to solve the above-mentioned drawbacks of the prior art, the present invention performs high-speed block transfer of image data existing in discontinuous address spaces at once, and improves the load ratio of the microprocessor. The aim is to provide a random access data transfer method that significantly reduces the

(Means for Solving the Problems) The present invention provides a multiplexer that switches access from the microprocessor side and access from the DMA control unit during DMA transfer, and a microprocessor that arbitrarily sets addresses arranged in a random order. By providing a possible address buffer memory and a timing correction unit that performs synchronization and sequential control between the scanning signal of the television camera and the control signal of the DMA control unit, it is possible to transfer This address buffer memory is accessed and a generated random transfer address is sent to the image memory side, while discontinuously existing image data groups are collectively transferred at high speed.

(Function) According to the present invention, addressing of an image data group required for image processing can be arbitrarily set by a microprocessor. In addition, by simply initializing the start address and number of transfer words from the microprocessor to the DMA control unit once for a group of image data existing in a discontinuous address space, high-speed block transfer can be performed all at once to the hardware. Furthermore, the data set required for image processing can be controlled independently of the television camera scan.

(Example) To explain the present invention in detail using an example, the first
As shown in the figure, this embodiment includes an address buffer memory 18 that generates arbitrary discontinuous addresses in addition to data transfer using the prior art DMA, and an address buffer memory 18 that generates arbitrary discontinuous addresses from a microprocessor 11. Bus gate 21 for setting random addresses, during DMA transfer
It constitutes a multiplexer 17 that switches between counter-type access from the DMA control section 15 and access from the microprocessor 11, and a timing correction section 19 that performs synchronization and sequential control between the scanning signal of the television camera and the control signal of the DMA control section 15. It consists of

The read operation in the random access data transfer method will be explained in detail below. First, the multiplexer 17 is switched to the B side (microprocessor side bus), and the random address corresponding to the data group of the image memory 10 to be transferred is set to the number of words to be transferred. They are arranged in the number shown in the table and set in the address buffer memory 18 from the microprocessor 11 via the bus gate 21. Next, DMA control unit 1
5, initialize the start address and number of transferred words. Here, the storage location on the RAM 13 corresponding to the transfer destination is fixed. After that, the microprocessor 11
A DMA start signal l is output to the DMA control unit 15, and the DMA control unit 15 outputs an HLD request signal j to the microprocessor 11, and after receiving the bus permission signal k, switches the multiplexer 17 to the A side (DMA control unit side bus), and high-speed block transfer using DMA is started. To generate a random address, the address buffer memory 18 is accessed by a counter-type continuous address output from the DMA control unit 15, and in synchronization with this counter-type address, the previously set random transfer address is transferred via the buffer gate 22. The image is output to the image memory 10. At the same time, the image data accessed by the random transfer address on the image memory 10 is stored in the designated address space of the RAM 13 on the microprocessor side via the DMA bus gate 23. Also, at this time DMA
Various control signals output from the control section 15 are sent to the image memory 10 and the timing correction section 19 in synchronization with the vertical blanking period of the scanning signal of the television camera.
Output to RAM13.

As described above, high-speed DMA transfer is performed all at once for data groups existing in discontinuous address spaces on the image memory, and the microprocessor 1
1 is not subject to any special load for data transfer.

(Effects of the Invention) As described above, according to the present invention, data groups existing in discontinuous address spaces on the image memory can be transferred as a block by a single initial setting and transfer start, thereby reducing the load on the microprocessor. In addition, the software processing procedure of the microprocessor can be simplified, and the data transfer time can be significantly shortened.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of data transfer using the random access data transfer method according to the present invention, Fig. 2 is a circuit diagram of data transfer using conventional PCMA, and Fig. 3 is a circuit diagram of data transfer using the conventional PCMA method.
The figure is a circuit diagram of data transfer using conventional DMA, and FIG. 4 is a diagram showing the correspondence between a CRT screen and an image memory. In the figure, 1 is synchronization separation, 2 is video separation, and 3 is A/
D converter, 4 is a data register, 5 is a buffer gate, 6 is an address generation counter, 7 is a decoder, 8 is a multiplexer, 9 is a multiplexer,
10 is an image memory, 11 is a microprocessor,
12 is a ROM, 13 is a RAM, 14 is an I/O driver, 15 is a DMA control section, 16 is an address latch register, 17 is a multiplexer, 18 is an address buffer memory, 19 is a timing correction section,
20 is a decoder, 21 is a bus gate, 22 is a buffer gate, 23 is a DMA bus gate, and 24 is a window. a is a horizontal synchronization signal, b is a vertical synchronization signal, c is a basic clock, d is a sampling clock, e is a bus switching signal, f is a bus gate signal, g
is the MPU address, h is the MPU control bus,
i is MPU data bus, j is HLD request signal, k
is the bus permission signal, l is the DMA start signal, m is the bus permission signal, and m is the DMA start signal.
DMA address bus, n is random address & data bus, o is DMA bus gate signal, P, Q are the number of pixels.

Claims (1)

[Claims] 1 In a method of collectively transferring multiple pieces of arbitrary data between an image memory that stores image data from a television camera and a microprocessor that performs various image measurements based on that data, the microprocessor side A multiplexer that switches between access to the buffer memory and access from the DMA control unit to the buffer memory during DMA transfer, an address buffer memory that allows the microprocessor to arbitrarily set addresses arranged in random order, and a scanning signal for the television camera. By providing a timing correction unit that performs synchronization and sequential control between the control signals of the DMA control unit and the DMA control unit, this address buffer memory is accessed by counter-type continuous transfer addresses from the DMA control unit, and the generated A random access data transfer method in which a group of discontinuous image data is collectively transferred at high speed while sending a random transfer address to the image memory side.