JPH0713507A - Image processing device - Google Patents

Abstract

PURPOSE:To provide an image processing device capable of accessing DMAC, etc., during displaying of character images on a CRT. CONSTITUTION:This device is provided with the CRT 700 of a luster scanning system, a first memory 601 for a plurality of character image data, a second memory 601 for storing identification information for specifying character images and attribute data on how many times images are displayed continuously, a detecting means for scanning positions, a first signal generation means for reading the identification information and attribute data from the second memory 602 based on the scanning positions, a second signal generation means for reading the character image data corresponding to the read identification information, i.e., the data of a line corresponding to the scanning positions, from the first memory 601, a third memory for storing data from the first memory 601 and a control means 300 for repeatedly outputting data stored in the third memory to the CRT 700 by a number of times specified based on the attribute data and simultaneously accessing the first and second memories 601 and 602 to a data exchanging means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for displaying a predetermined character image on a display CRT adopting a raster scanning system.

[0002]

2. Description of the Related Art A raster scanning CRT is shown in FIG.
As shown in (a), the scanning beam sequentially scans from left to right starting from the pixel at the upper left corner of the screen, and then sequentially scans each pixel on the line one step below from left to right.
In this way, the scanning beam scans up to the pixels of the final line. After scanning the last pixel of the last line, the scanning beam retraces to the upper left corner of the display CRT. Subsequently, the scanning beam sequentially scans from the upper left corner to display the next screen. Here, as shown in FIG. 3B, a period during which the data from the first pixel to the last pixel of a certain line is output is called a line display period. Further, a period from the output of the data of the last pixel of a certain line to the output of the data of the first pixel of the next line is referred to as a horizontal blank period. The period required to output all the data for one screen is called the display period. Further, a period from the output of the data for one screen to the output of the data of the first pixel of the next screen is referred to as a vertical blank period.

As an image processing apparatus for displaying a character image composed of a predetermined pixel matrix on a display CRT of a raster scanning system, for example, Japanese Patent Laid-Open No. 59-11.
It is disclosed in Japanese Patent No. 8184. This image processing device includes a first memory for storing data of a character image composed of a predetermined pixel matrix, and a second memory for storing the name of the character image to be displayed at each position of the display CRT.

The image processing apparatus checks the currently scanned line of the scanning beam of the display CRT, and based on the position of the checked scanning line, the name of the character image to be displayed on the next line from the second memory. Read out. Then, the image data corresponding to the name of the character image read from the second memory is read from the first memory, and the read data is output to the display CRT.

[0005]

In the above image processing apparatus, as shown in FIG. 3A, the name and data of the character image displayed by the display CRT during the period in which a certain line is being displayed are described above. It is supposed to be read from the first and second memories. When the image displayed on the display CRT is a still image, the number of character images displayed in one line is the same as the number of character images read from the first memory. Therefore, the address bus and the data bus connected to the first and second memories read the name of the character image to be displayed from the second memory and display the data of the character image corresponding to the name during the line display period. It is completely occupied by the processing unit that executes reading from one memory. Therefore, the name and data of the character image stored in the first and second memories are stored in the external CPU or DM.
The timing for changing the setting by AC or the like was only during the vertical blank period. However, as the data amount of the character image increases, it becomes difficult to execute all the setting change processing within the vertical blank period.

Therefore, an object of the present invention is to provide an image processing apparatus capable of executing a setting change process of a character image even during a line display period.

[0007]

An image processing apparatus according to a first aspect of the present invention is a raster scanning type display CRT and M ×.
A first memory that stores image data of a plurality of character images composed of an N pixel matrix, identification information that identifies each character image that is stored in the first memory, and the number of times that character image is continuously displayed. A second memory that stores the attribute data about whether or not to be set as a set in the order of output to the display CRT, a detection unit that detects the position of the scanning beam of the display CRT, and a scanning position that is detected by the detection unit. Based on the first address generating means for generating the first address signal for reading out the identification information and the attribute data of the character image to be output from the second memory, based on the first address signal generated by the first address generating means. The identification information is read from the second memory, and is data of a character image corresponding to the read identification information,
Second address generating means for generating a second address signal for reading the data of the n-th line (where 1 ≦ n ≦ N) corresponding to the scanning position detected by the detecting means from the first memory; A third memory for reading the data of the character image of the nth line from the first memory by the second address signal generated by the address generating means and storing the read data, and the attribute data read from the second memory. The output means for repeatedly outputting the character image data stored in the third memory to the CRT, the data changing means for changing the data in the first and second memories, and the output means for the third time. The data of the first and second memories is changed while the character image data of the nth line stored in the memory is being output to the display CRT. An access control means enabling stage and accessible.

An image processing apparatus according to a second aspect of the present invention is the image processing apparatus according to the first aspect, wherein the third memory is a shift register capable of rotating operation and also functions as the output means. It is characterized by

An image processing apparatus according to a third aspect is the image processing apparatus according to the first or second aspect, and further includes the identification information and the attribute data read from the second memory. The first address generating means includes an adding means for calculating a total value of the attribute data, and the first address generating means generates a first address signal based on the total value of the attribute data calculated by the adding means and the detection result by the detecting means. Is characterized by.

[0010]

According to the image processing apparatus of the present invention, the identification information and the attribute data of the character image composed of the M × N pixel matrix are generated from the second memory by the first address signal generated by the first address generating means. read out. Also, the second address signal generated by the second address generation means causes the n-th (where 1 ≧ n ≧ N) corresponding to the identification information read from the first memory from the second memory.
The data of the character image of the line is read. The data of the character image of the n-th line read from the first memory is stored in the third memory. The output means outputs the character image data of the nth line stored in the third memory to the CRT the number of times determined based on the attribute data. The control means makes the first and second memories accessible to the data change means such as the DMAC while the output means outputs the character image data of the nth line stored in the third memory to the display CRT. To do. That is, the image processing apparatus according to claim 1 is a display CR.
When the data of the same character image on the same scanning line of T is continuously output a plurality of times, the value of the display count is stored in the second memory as the attribute data together with the character name. When the value of the attribute data attached to the character name read from the second memory is "1" or more,
After displaying the character image, the data of the same character image is not read again from the first memory, but the data of the read character image is temporarily stored in, for example, a shift register, and the number of times of the value of the attribute data is changed. Output only for minutes. As described above, the image processing apparatus of the present invention reduces the redundant reading process for the first memory, and releases the remaining time as the accessible time of the data conversion unit.

An image processing apparatus according to a second aspect of the present invention is the image processing apparatus according to the first aspect, in which the third memory is a rotatable shift register and also functions as an output means. The third memory rotates the character image data of a predetermined line stored in the shift register by the number of times determined based on the attribute data and outputs the data to the display CRT.

In the image processing apparatus according to the third aspect of the present invention, the sum of the values of the attribute data of the identification information and the attribute data read from the second memory is obtained by the adding means. The first address generating means generates a first address signal based on the total value of the attribute data obtained by the adding means and the detection result of the detecting means.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the image processing apparatus of the present invention, when the data of the same character image is continuously output a plurality of times on the same scanning line of the display CRT, the value of the number of times of display is used as the attribute data for the character name. It is also stored in the second memory. When the value of the attribute data attached to the character name read from the second memory is “1” or more, after displaying the character image, the data of the same character image is not read again from the first memory. Data of the read character image is stored in, for example, a shift register, and repeatedly output as many times as the value of the attribute data. As described above, the image processing apparatus of the present invention is characterized in that the redundant reading process for the first memory is reduced and the remaining time is released as the DMAC accessible time (see FIG. 8). ). In the embodiment of the present invention, one screen is made up of 256 × 224 pixels, and three character images made up of an 8 × 8 pixel matrix are displayed.
A total of 896 2 × 28 pieces are displayed on the display CRT.
Hereinafter, the image processing apparatus of the present invention will be described in the following order with reference to the accompanying drawings. (1) Description of configuration of image processing device <1-1> Outline description of each functional block <1-2> Operation description of still image data processing circuit <1-3> Operation description of still image address processing circuit (2) Character image display processing

(1) Description of Configuration of Image Processing Apparatus <1-1> Schematic Description of Each Functional Block FIG. 1 is a diagram showing each functional block constituting the image processing apparatus of the present invention. An address bus, a data bus, and a control bus are connected to each functional block. The CPU 300 executes control processing of the entire image processing apparatus. The RAM 100 is a writable memory used in the control processing executed by the CPU 100. R
The OM 200 stores processing programs and the like necessary for the operation of the image processing apparatus of the present invention. DMAC400 is
Data transfer from the RAM 100 and the ROM 200 to the image display device is controlled and executed. DMAC400 is CPU3
In response to the request of 00, the VRAM 600 is connected to the RAM 100 and the ROM 200, and the setting of the name and data of the character image stored in the VRAM 600 is changed. The image display device 500 is a device that executes display processing of a character image in the image processing device of the present invention.
As shown in FIG. 4, the VRAM 600 includes a first memory 60.
1 and a second memory 602. Image data of a character image is stored in the first memory. Further, as shown in FIG. 7, the second memory 602 has a display CRT.
The name of the character image displayed at a predetermined position of 700 and the attribute data indicating the number of times of displaying the same character image continuously on the same line (hereinafter,
Attribute data is called run length data. ) And are stored at predetermined addresses.

FIG. 2 is a diagram showing each functional block constituting the image display device 500. The image display device 500 includes a CPU interface 501 (hereinafter, the interface is referred to as I / F) connected to an address bus, a data bus, and a control bus, a still image address control circuit 502 described later, and a VRAM I / F5.
03, a still image data processing circuit 504, a color signal generation circuit 505, an NTSC encoder 506, an HV counter 507, and a timing generation circuit 508. Here, the CPU I / F 501 uses the data bus and the control bus to control the still image address control circuit 502, V
It is connected to the RAM I / F 503 and the color signal generation circuit 505. Further, the still image address control circuit 502 is connected to the VRAM 600 via an address bus and a data bus. The VRAM I / F 503 is connected to the VRAM 600 via an address bus and a data bus. The still image data processing circuit 504 receives VR via the data bus.
It is connected to AM600.

The still image data processing circuit 504 is provided with a shift register capable of rotating operation, and stores character image data input via the data bus. Here, when the value of the run length data similarly input via the data bus is "1" or more, the character image data stored in the shift register is continuously output to the display CRT 700 a plurality of times. In addition, the character image data held in the shift register is displayed on the display CRT.
During the period of 0 output, the VRAM 60 is added to the DMAC 400.
0 accessible signal (hereinafter referred to as NA signal)
Is output. The still image address control circuit 502 detects the scanning position of the scanning beam of the display CRT, and based on this, generates a screen address for reading out the name and run length data of the character image stored in the second memory. Is output to the address bus. Further, a character address for reading the image data corresponding to the name of the character image read from the second memory from the first memory is generated and output to the address bus.

Further, while the NA signal is being output from the still image data processing circuit 504, the still image address control circuit 50 is connected to the address bus connected to the VRAM 600.
2 is released and the CPU 300 and the DMAC 400 can access. The color signal generation circuit 505 includes a color table, adds palette data as color additional information to the data of the character image output from the shift register 26 of the still image data processing circuit 504, and uses the corresponding address as the address of the color table. And outputs the image data stored in the NTSC encoder 506. N
The TSC encoder 506 adds the horizontal and vertical synchronization signals given from the HV counter 507 to the image data output from the color signal generation circuit 505 to synthesize an NTSC color television signal and outputs it to the display CRT 700.

FIG. 5 is a more detailed structural circuit diagram of the still picture address control circuit 502, the still picture data processing circuit 504, the HV counter 507 and the timing generation circuit 508 shown in FIG. In the figure, a still image data processing circuit 50
4 is a run length register 14 to which run length data is input.
A down counter 15 for down-counting the value of the run length data, a NAND gate 16, a flip-flop 17, NOR gates 18, 19, 20 and an AND gate 21, and an addition for obtaining the sum of the values of each disturbance data. Bowl 22
, Total run length register 23, and inverter 24
A character data register 25 to which image data of a character is input, a shift register 26 that performs a rotation operation based on the value of run length data, AND gates 27 and 28, and a JK flip-flop 29. . The still image address control circuit 502 includes a name register 1, a character address register 2, a screen address register 3, an inverter 11, an adder 6, a corrected screen address register 7, and three state buffers 8, 9, 10. And 12 and a NAND gate 13. The HV counter circuit 507
It is composed of an H (horizontal) counter 4 and a V (vertical) counter 5. Further, FIG. 6 shows a still image data processing circuit 50.
4 is a timing chart showing a data waveform in each part of the No. 4 and still image address processing circuit 502.

<1-2> Description of Operation of Still Image Data Processing Circuit FIG. 5 shows the still image address control circuit 50 shown in FIG.
2. Still image data processing circuit 504, HV counter 507
9 is a more detailed configuration circuit diagram of a timing generation circuit 508. FIG. The operation of the still image data processing circuit 504 will be described below with reference to the configuration circuit diagram shown in FIG. 5 and the timing chart of FIG. The timing generation circuit 508
In response to the input of the DCK (dot clock) signal, the EN signal and the PrEN signal whose phase leads the EN signal by one cycle of the DCK signal are output. The EN signal and the PrEN signal correspond to the size of the character image (8 × 8
One positive pulse signal is generated every eight cycles of the DCK signal corresponding to each pixel. The EN and PrEN signals are used as control signals for down-counting the down counter 15 (described later).

The name, run length, and character data of the character image are loaded from the VRAM 600 into the name register 1, the run length register 14, and the character data register 25 at predetermined timings via the data bus. As will be understood with reference to the time chart of FIG. 6, a set of name, run length and character data is sent in units of 8 cycles of the DCK signal. To the down counter 15, the run length data from the run length register 14, the DCK signal and the EN signal, and the load signal described later are input. As shown in FIG. 6, the down counter 15 counts down the value of the input run length data in synchronization with the falling timing of the EN signal.
The down counter 15 outputs a carry signal of a high level from the output terminal C when the value of the run length data is "0", and outputs a carry signal of a low level when it is other than "0". The carry signal output from the output terminal C of the down counter 15 and the PrEN signal are input to the next NAND gate 16. The signal output from the NAND gate 16 is output at a timing proportional to the value of the run length data, as shown in FIG. NAN
The signal output from the D gate 16 is input to the next flip-flop 17 to be a load signal delayed by one cycle of the DCK signal. As shown in FIG. 5, the load signal is supplied to the down counter 15 and the shift register 26.
To the total run length register 23, and each serve as a trigger signal when reading the next data.

The shift register 26 stores character image data for 8 pixels. In addition to the load signal, the DCK signal and the character image data output from the serial output terminal SO are input to the serial input terminal SI of the shift register 26 by the rotate operation described later. With the input of load signal, shift register 2
Reference numeral 6 reads the character image data from the character data register 25 in synchronization with the DCK signal. The shift register 26 is provided with a serial input terminal SI and a serial output terminal SO, and is capable of rotating operation. After the load signal is output from the flip-flop 17 described above, the shift register 26 outputs bit serial data from the serial output terminal SO in synchronization with the DCK signal until the next load signal is output. The output is input to the serial input terminal SI to perform the rotate operation. The value "N" of the run length data provided with the name of a certain character image means that a total of N + 1 character images are continuously displayed N times after displaying the character image of the name. Therefore, when the value of the run length data is “1” or more, the shift register 26 synchronizes with the falling timing of the EN signal until the value of the down counter becomes “0” while synchronizing with the serial input terminal SI. The character image data input to is output again to the color signal generation circuit 505 from the serial output terminal SO. Here, down counter 15
If the value of the run length data read in is 0 from the beginning, or if the result of the down count is "0", the down counter 15 outputs a load signal. Along with this, the shift register 26 reads the data of the character image to be displayed next.

During the period when the value of run length data is "1" or more,
No load signal is output from the down counter 15, and the next character image is not read. When the NOR gate 18 detects that the value of the run length data is “1” or more, it sets the JK flip-flop 29,
An NA signal is output to notify the DMAC 400 that the RAM 100, the ROM 200, and the VRAM 600 can be accessed, and the still image address control unit 502.
Switch the 3-state buffer 12 in the VRAM 6
The 00 address bus is disconnected from the still image address control unit 502 to enable access to the VRAM 600 of the DMAC 400. When the down counter 15 counts down and its output becomes "1", the NOR gate 20 detects this (see FIG. 6). AND gate 21
Is the value of the input RvEN signal and the NOR gate 20
The value of the down counter 15 is "1" from the value of the output signal of
The timing of switching from "0" to "0" is detected. The JK flip-flop 29 cuts the output of the NA signal according to the value of the AND gate 21. Further, in order to output the address data of the character image to be read next, the 3-state buffer 12 is switched, and the still image address control unit 5
02, and access to character image data and name is restarted. The adder 22 and the total run length register 23 calculate the total of the values of the run length data in synchronization with the acquisition of the run length data of the down counter 15. The cumulative total of the run length data values held in the total run length register 23 is input to the still image address control circuit 502 for the screen address correction calculation described later.

<1-3> Description of Operation of Still Image Address Processing Circuit In the still image address processing circuit 502, the HV counter 50 is used.
A screen address for reading the name and run length data of a predetermined character image from the second memory included in the VRAM 600 is created based on the counter values of the H counter 4 and the V counter 5 included in 7 and is output to the address bus. , Corresponding 8 based on the name read from the second memory and the counter value of the V counter 5.
A character address for reading the data of the n-th line (where 1 ≦ n ≦ 8) of the character image composed of a × 8 pixel matrix is created and output to the address bus. Further, the still image address processing circuit 502 switches the 3-state buffer 12 in response to the NA signal output from the JK flip-flop 29 included in the still image data processing circuit 504 described above, and responds to the address from the DMAC 400 in response to the request. Release the bus to DMAC 400.

The operation of the still image address processing circuit 502 will be described in more detail below. HV counter 507
Counts up in synchronization with the movement of the scanning beam of the display CRT 700 and always confirms the position of the scanning beam. 32 × 2 on the display CRT screen as shown in FIG.
The name representing the array of 8 character images is VRAM
It is stored in the second memory 602 included in 600.
The names of the character images are stored in order of address from the left end to the right end and from the upper end to the lower end, with the upper left end of the screen of the display CRT 700 as a lower address. Therefore, the address (hereinafter referred to as a screen address) in the second memory in which the name of the character image displayed on the current scan line is stored is the H counter 4 and the V counter 5 provided in the HV counter circuit 507. Can be obtained based on the value of.

However, in the present invention, run length data is provided together with the name of the character image. Therefore, when the value of the run length data is "1" or more, the stored screen addresses are sequentially shifted by the value of the total run length data. Therefore, in order to obtain an accurate screen address, the value of the total run length data may be subtracted from the value of the screen address obtained in the adder 6. FIG. 7 shows the relationship between the conventional screen address and the corrected screen address used in the image processing apparatus of the present invention. As shown in the figure, in the conventional second memory, Name1, Name2, Name3, Name3, Name4, Na are associated with each address.
Each name was remembered as me4, Name4, Name5, .... The second memory 602 included in the image processing apparatus of the present invention includes run length data in addition to name data, but does not store name data in duplicate. Therefore, the capacity of the memory used as a result can be reduced.

After accessing the second memory 602, the still image address processing circuit 502 transfers the data of a predetermined line of the character image formed of the 8 × 8 pixel matrix corresponding to the name fetched in the name register 1 to the first memory. An address to be read from (hereinafter, this address is referred to as a character address) is generated. The data of the character address is the data composed of the 8 × 8 pixel matrix corresponding to the name of the character image in the upper bits.
Data of which address is stored in the first memory is provided, and data specifying which line of the character image to read is provided in the lower bit.
Specifically, as the character address data, the character image corresponding to the name stored in the name register 1 is changed to the address data stored in the first memory.
The lower 3 bits corresponding to the remainder of the current scanning position of the CRT 700 in the vertical direction (counter value of the V counter 5) divided by 8 are added. The screen address and the character address are transferred to V via the 3-state buffers 8 and 9.
It is alternately output to the address bus connected to the RAM 600.

(2) Character Image Display Processing Next, as shown in FIG. 7, the VR including the second memory in which the character name and run length data are stored.
Display processing of a character image in the image processing apparatus of the present invention will be described using AM600. First, the total run length register 23 is reset and initialized. Next, the counter values of the H counter 4 and the V counter 5 included in the HV counter 507 are combined in the screen address register 3 to generate a screen address. The generated screen address is input to the second memory 602 provided in the VRAM 600 via the address bus (see point a1 in FIG. 6). Upon receiving the screen address, the second memory 602 outputs the character name “Name1” stored in the corresponding address and the run length data “0” to the name register 1 and the run length register 14 via the data bus ( (See point a1 'in FIG. 6). After executing other processing (see point b1 in FIG. 6), the still image address processing circuit 502 adds V counter to the data of the address where the character image corresponding to the name “Name1” is stored in the character address register. A character address is generated by adding the lower 3 bits of the counter value of 5. The data of the generated character address is transferred to the VRAM 60 via the address bus.
It is input to the first memory 601 provided in 0 (see point c1 in FIG. 6). Upon receiving the character address, the first memory 601 stores the data of the predetermined line of the character image data “CHR1” consisting of the 8 × 8 pixel matrix corresponding to the character name “Name1” in the character data register 25 via the data bus. Output (Fig. 6
See point c1 '). As described above, the value of the run length data is the CRT 700 for displaying the corresponding character image.
It is attribute data indicating the number of times the same character image is continuously output after being output to. In the above case, since the value of the run length data is "0", the data of the predetermined line of the character image of "CHR1" is output only once on the screen.

Also in the case of the next character name "Name2", since the value of the run length data is "0", the data of the predetermined line of the character image "CHR2" is output to the display CRT 700 only once. However, in the case of the character name "Name3", the value of the run length data is "1". In this case, the data of the predetermined line of the character image “CHR3” is held in the shift register 26 and output to the display CRT 700 twice in succession as described above. Similarly, in case of character name "Name4",
Since the value of the run length data is “2”, the data of the predetermined line of the character image “CHR4” is the display CR.
It is continuously output to T700 three times.

As described above, the JK flip-flop 29 provided in the still image data processing circuit 504 outputs the output of the NOR gate 19 when the value of the run length data input via the data bus is "1" or more. Output of the NA signal in synchronization with the falling timing of the AND gate 2
The output of the NA signal is cut in synchronization with the fall timing of the output of 1. As shown in FIG. 6, the timing at which the data sent via the data bus is stored in the character data register 25 is delayed by eight cycles of the DCK signal. Character name above "Name
When the character image "CHR4" of 4 "is displayed, the value of the run length data is" 2 ".
CHR4 "is displayed once and then continuously displayed twice. At this time, the first and second character images" C "are displayed.
During the display period of "HR4", as described above, the DMAC40
The address bus is released to 0.

As described above, in the image processing apparatus of this embodiment, when data of a predetermined line of a character image consisting of an 8 × 8 pixel matrix is output to a raster scanning system display CRT, the same line is used. When the character images are continuously output, it is not necessary to read the character image data in duplicate. Therefore, the DMAC 400 can access the VRAM 600 even during the line display period (see FIG. 8). Also, VRA
Since the amount of character name information required by M600 is reduced, the memory capacity required for processing can be reduced.

[0031]

According to the image processing apparatus of the present invention, in the case of displaying a character image consisting of a predetermined pixel matrix in a raster scanning CRT, when the same character image is continuously displayed on the same line. The data of the character image that has been read once is held in the shift register, and this is repeatedly output, so there is no need to perform redundant processing such as reading the data of the same character image many times. Therefore, the control unit can make the first and second memories accessible to the DMAC 400 during the line display period. Further, since the second memory is provided with the attribute data, it is possible to reduce the memory usage amount as compared with the conventional method of storing all the identification information in the display order.

[Brief description of drawings]

FIG. 1 is each functional block constituting an image processing apparatus of the present invention.

FIG. 2 is a diagram showing each functional block constituting the image display device 500.

FIG. 3A shows a configuration of a raster scanning CRT, and FIG. 3B shows scanning timing.

FIG. 4 is a diagram showing a first memory 601 and a second memory 602 included in the VRAM 600.

5 is a diagram showing a configuration circuit of a still image address processing circuit 502 and a still image data processing circuit 504. FIG.

FIG. 6 is a timing chart showing a data waveform in each component of the still image address processing circuit 502 and the still image data processing circuit 504.

7 is a diagram showing a state of name and run length data stored in a second RAM provided in the VRAM 600. FIG.

FIG. 8: VR in the present invention and the conventional image processing apparatus
It is a figure which shows the accessible period of AM600 and DMAC400.

[Explanation of reference numerals] 100 ... RAM 200 ... ROM 300 ... CPU 400 ... DMAC 500 ... Image display device 501 ... CPU interface 502 ... Still image address processing circuit 503 ... VRAM interface 504 ... Still image data processing circuit 505 ... Color signal generation circuit 506 ... NTSC encoder 507 ... HV counter 508 ... Timing generation circuit 600 ... VRAM

Claims (3)

[Claims] 1. A raster scan type display CRT and M ×
A first memory that stores image data of a plurality of character images composed of an N-pixel matrix, identification information that identifies each character image stored in the first memory, and the number of times the character image is continuously displayed. A second memory that stores the attribute data about whether or not to be set in the order of output to the display CRT, a detection unit that detects the position of the scanning beam of the display CRT, and a scanning position that is detected by the detection unit. On the basis of the first address generating means for generating the first address signal for reading the identification information and the attribute data of the character image to be output from the second memory, and the first address signal generated by the first address generating means. The identification information is read from the second memory, and is data of a character image corresponding to the read identification information, which is detected by the detection means. Second address generating means for generating a second address signal for reading the data of the n-th line (where 1 ≦ n ≦ N) corresponding to the detected scanning position from the first memory, and the second address generating means. A third image data is read from the first memory by the second address signal generated by the second address signal, and the read data is stored.
A memory; output means for repeatedly outputting the character image data stored in the third memory to the CRT a number of times determined based on the attribute data read from the second memory; Data changing means for changing the data, and during the period in which the output means is outputting the data of the character image of the nth line stored in the third memory to the display CRT, the first and second memories are used as the data changing means. An image processing apparatus comprising an access control unit that enables access. 2. The image processing apparatus according to claim 1, wherein the third memory is a shift register capable of rotating operation, and also functions as the output means. 3. The image processing apparatus according to claim 1 or 2, further comprising: an addition unit that obtains a total value of attribute data among the identification information and the attribute data read from the second memory. An image processing apparatus comprising: a first address generating means, wherein the first address generating means generates a first address signal based on a total value of the attribute data obtained by the adding means and a detection result by the detecting means.