JP2565581B2 - CRT display circuit - Google Patents

Description

The present invention relates to a CRT display circuit for displaying characters such as numbers and letters provided by a microcomputer on a screen of a CRT display device over a plurality of lines. It is about.

[Conventional technology]

FIG. 3 shows a conventional example of a CRT display circuit for displaying a character on the screen of a CRT display device. In FIG. 3, a CRT display circuit 1 supplies a raster scanning signal to a CRT display device (not shown) in order to display a character on the screen. The control microcomputer 2 is provided to control various operations of the CRT display circuit 1, and specifies, for example, a character to be displayed on the screen, a horizontal and vertical display position of the character, and the like. .

In the CRT display circuit 1, the interface 3 matches the control microcomputer 2 with the internal circuit of the CRT display circuit 1. The timing generator 4 receives the dot clock 12, the horizontal synchronizing signal 13 and the vertical synchronizing signal 14 and generates various timing signals for screen display.
The horizontal display start position control circuit 5 controls the horizontal display start position of each character on each display line on the screen. The vertical display start position control circuit 6A controls the vertical display start position of the character on each display line on the screen.

The video RAM 7 stores the character to be displayed on the screen in association with the screen. The video RAM control circuit 8 is a video RAM
Controls writing and reading of 7. The character ROM 10 stores data indicating the shape of the character and is accessed by the read data of the video RAM 7. The shift register 11 sequentially transfers the output of the character ROM 10 serially to generate a time series signal. The CRT display output circuit 9 outputs a CRT display signal 25.

In the CRT display circuit 1 having the above-described configuration, various data for display control is supplied from the control microcomputer 2 through the interface 3 to the timing generator 4, the horizontal display start position control circuit 5, and the vertical display start position control. circuit
6A, video RAM 7 and output circuit 9 for CRT display.

Prior to displaying characters on the screen, the timing generator 4 is supplied with data such as the display size of characters from the control microcomputer 2 through the interface 3. Similarly, in the horizontal display start position control circuit 5,
Data indicating the horizontal display start position of each character is given. Further, the vertical display start position control circuit 6A is supplied with data indicating the vertical display start position of each character. Data indicating the type of character to be displayed on the screen is given to the video RAM 7 in one-to-one correspondence with the screen. The CRT display output circuit 9 is supplied with data such as the display color of the character.

When various kinds of data as described above are sent from the control microcomputer 2 to the CRT display circuit 1, various kinds of timing pulses required for the timing generator 4 to display on the screen (for example, horizontal dot clock, vertical dot clock). , Video RAM precharge, ROM precharge,
A data load signal from the video RAM to the shift register is generated and supplied to the horizontal display start position control circuit 5, the vertical display start position control circuit 6A, the video RAM control circuit 8 and the shift register 11.

The horizontal display start position control circuit 5 creates a signal indicating the horizontal display start position of each character to be displayed on the screen based on the timing pulse from the timing generator 4 and the horizontal synchronizing signal 13, and outputs the signal. It is sent to the CRT display output circuit 9. Further, the vertical display start position control circuit 6A is
Based on the timing pulse from the timing generator 4, the horizontal synchronizing signal 12 and the vertical synchronizing signal 14, a signal indicating the vertical display start position of the character of each display line to be displayed on the screen is created and displayed on the CRT. For output to the output circuit 9.

On the other hand, the video RAM control circuit 8 includes the timing generator 4
Video RA according to the timing pulse sent from
The display data stored in M7 is read out sequentially
Send to ROM10. The character ROM 10 performs a read operation by using the data sent from the video RAM 7 as an address, and sends the data to the shift register 11.

In the shift register 11, the output data of the character ROM 10 is displayed as time series data for CRT display based on the timing pulse of the timing generator 4 and the signal indicating the horizontal display start position of the character given from the horizontal display start position control circuit 5. It is sent to the output circuit 9.

As a result, in the CRT display output circuit 9, a signal corresponding to the raster scan on the screen is created and sent to the CRT display device (not shown), and the character stored in the video RAM 7 is horizontally displayed on the screen. It is displayed together with the background at the position defined by the start position control circuit 5 and the vertical display start position control circuit 6A.

FIG. 4 shows a specific structure of the vertical display start position control circuit 6A in the CRT display circuit shown in FIG. In FIG. 4, the counting circuit 15 clocks the horizontal synchronization signal 13 (CK).
The vertical sync signal 14 is used as the reset input, and the horizontal sync signal 13 is set with the trailing edge of the pulse of the vertical sync signal 14 as the starting point.
It has a function of counting the number of pulses of the horizontal scanning line and detecting the position of the horizontal scanning line currently being scanned on the screen.

The register 19 has N storage areas and stores vertical display start position data indicating the vertical display start position of each of the first to Nth display lines of the character to be displayed on the screen. The number of pulses of the horizontal synchronizing signal 13 generated from the trailing edge of the 14th pulse to the upper end of each of the first to Nth display rows is stored as the starting point. In particular,
As shown in FIG. 5, the register 19 displays the screen P when the screen P has the first to Nth display lines L _{1 to} L _N.
The number of horizontal scanning lines included between the upper end of the line (corresponding to the trailing edge of the pulse of the vertical synchronizing signal 14) and the upper edge of each display row L _{1 to} L _N , that is, the trailing edge of the pulse of the vertical synchronizing signal 14 vertical display start position corresponding to the number of pulses of the horizontal synchronizing signal 13 to the upper end of each display line L ₁ ~L _N as starting point data VP ₁ ~VP _N
Will be remembered respectively.

The multiplexer 18 stores the vertical display start position data of each of the _{first to Nth} display rows L _{1 to} L _N stored in the register 19.
VP ₁ ~VP any one of _N and selected according to the line number data 20 output. The data comparator 16 compares the output value of the counting circuit 15 with the output value of the multiplexer 18 and outputs a coincidence signal 24 when they coincide with each other. The vertical display start signal generating circuit 17 including a latch receives the coincidence signal 24 output from the data comparator 16 and starts outputting the vertical display start signal 24, and receives the row display completion signal 21 to display the vertical display. The output of the start signal 24 is stopped.

Next, the vertical display start position control operation of the vertical display start position control circuit 6A will be described. In this vertical display start position control circuit 6A, the counter circuit
After 15 is reset, the counting circuit 15 counts the pulses of the horizontal synchronizing signal 13 and sequentially increases the output value for each horizontal synchronizing signal 13. On the other hand, the multiplexer 18 determines the vertical display start position data VP _{1 of the} register 19 according to the line number data.
Select one of ～VP _N send to the data comparator 16.

Immediately after the trailing edge of the pulse of the vertical synchronization signal 14, the line number data 20 is the first row shows the display lines L ₁ of the (first line), the vertical display start position data VP ₁ display line L ₁ of the first row Is sent to the data comparator 16, a match signal 24 is generated when the output value of the counting circuit 15 matches the vertical display start position data VP ₁ .
The vertical display start signal generation circuit 17 starts outputting the vertical display start signal 22. Then, the vertical display start signal 22 is sent to the video RAM control circuit 8 and the CRT display output circuit 9 (see FIG. 3), and the display of the character in the display row L ₁ is started. After that, when the row display completion signal 21 given from the timing generator 4 (see FIG. 3) is input to the vertical display start signal generation circuit 17, the output of the vertical display start signal 22 is stopped and the display row L Complete the display of character ₁ .

Then, the line number data 20 is changed to the data indicating the display lines L ₂ of the second row, since the vertical display start position data VP ₁ display line L ₂ of the second row is sent to the data comparator 16, This time, the character on the display line L ₂ is displayed from the position corresponding to the vertical display start position data VP ₂ .

Thereafter, the line number data 20 are sequentially changed, is sequentially displayed from the third line to each display line L ₃ ~L _N characters sequentially vertical display start position data VP ₃ positions corresponding to the ～VP _N of the N-th row It

The above operation is repeated for each frame
Unless the contents of the RAM 7 are changed, the same character is displayed on the screen P over a plurality of frames.

[Problems to be Solved by the Invention]

However, according to such a configuration, as in the case of vertically scrolling on the screen P, all the display lines on the screen P are displayed.
When it is necessary to change the vertical display start position of L _{1 to} L _N , the control microcomputer 2 that controls the CRT display circuit 1 displays the vertical display start position data for all the display rows L _{1 to} L _N. without transferring the VP ₁ ~VP _N to CRT display circuit 1 not. In the case of the vertical scroll, this transfer is required once for each frame of the display screen, and there is a problem that the control microcomputer 2 has a heavy load.

Therefore, an object of the present invention is to control the vertical display start position data when rewriting the vertical display start position of all display lines on the screen evenly, for example, when performing vertical scrolling. It is an object of the present invention to provide a CRT display circuit that can reduce the load on a microcomputer.

[Means for solving the problem]

The CRT display circuit according to the present invention displays a character string composed of a plurality of characters, symbols and numerals on a CRT screen. The vertical display start position data of the first display line is converted into a vertical synchronization signal. Is stored as a value corresponding to the number of pulses of the horizontal synchronizing signal included in the vertical direction display start position, and the vertical direction display start position data of each display line after the second line is stored as the previous display line. Starting from a fixed position of, the register that stores the value corresponding to the number of pulses of the horizontal synchronization signal included in the vertical display start position of the display row, and the pulse of the horizontal synchronization signal that is reset at each starting point A counting circuit for counting the number, a data comparator for comparing the output value of the counting circuit with the vertical display start position data corresponding to the display row stored in the register, and in response to the generation of the coincidence signal of the data comparator. And a vertical display start position control circuit which is constituted by a vertical display start signal generation circuit for generating a vertical display start signal for the display line.

[Action]

According to the configuration of the present invention, when it is necessary to uniformly change the vertical position of all display lines, as in the case of performing vertical scrolling on the screen, the control It is not necessary to transfer the vertical display start position data for all the display lines from the microcomputer to the register that stores the vertical display start position data for each display line,
By only transferring the vertical display start position data of the first line, the vertical display positions of all the display lines can be changed evenly. For example, when the vertical scroll start position data is rewritten when vertical scrolling is performed on the screen. It is possible to remarkably reduce the load on the control microcomputer.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 and 3. This CRT display circuit uses the vertical display start position control circuit 6B shown in FIG. 1 in place of the vertical display start position control circuit 6A shown in FIG. It is similar to FIG.

In FIG. 1, the counting circuit 15 uses the horizontal synchronizing signal 13 as a clock (CK) input, and the vertical synchronizing signal 14 and the row display completion signal.
The OR signal from the OR circuit 23 of 21 is used as the reset input,
The trailing edge of the pulse of the vertical synchronizing signal 14 and the first to Nth rows
-Counting the number of horizontal synchronization signals 13 from the lower end of each of the display rows L _{1 to} L _N-1 of the 1st row to the upper end of each of the display rows L _{1 to} L _N of the _{1st to Nth} rows Then, it has a function of detecting the horizontal scanning line position (the position with respect to the trailing edge of the pulse of the vertical synchronizing signal 14 or the lower end of the preceding line as a reference) during the current scanning on the screen.

The register 19 has N storage areas, and each of the display lines L ₁ to N ₁ to N of the character to be displayed on the screen is displayed.
The vertical display start position data indicating the vertical display start position of L _N is displayed on the vertical synchronization signal 14 for the _first display line L _1.
The number of pulses of the horizontal synchronizing signal 13 up to the upper end of the display row L ₁ is stored starting from the trailing edge of the pulse of the above pulse, and each of the _{second to Nth} display rows L _{2 to} L _N is stored in the preceding row. The number of pulses of the horizontal synchronizing signal 13 in each of the display lines L _{2 to} L _N is stored as the starting point at the lower end of. Specifically, as shown in FIG. 2, the register 19 controls the upper end of the screen P (vertical sync signal when the screen P has display lines L _{1 to} L _{N of the first to Nth} characters). (Corresponding to the trailing edge of 14 pulses) from the trailing edge of the pulse of the vertical synchronizing signal 14, that is, the number of horizontal scanning lines included up to the upper end of the _first display line L ₁ The vertical display start position data VP ₁ corresponding to the number of pulses of the synchronization signal 13 is stored, and the second row is started from the lower end of the _{first to N−} 1th display rows L _{1 to} L _N-1. To the number of horizontal scanning lines included between the upper ends of the display rows L _{2 to} L _N of the Nth row, that is, the number of pulses of the horizontal synchronizing signal 13 calculated from the lower ends of the display rows L _{1 to} L _N-1. The corresponding vertical display start position data VQ _{2 to} VQ _N are stored respectively.

The multiplexer 18 stores the vertical display start position data of each of the _{first to Nth} display rows L _{1 to} L _N stored in the register 19.
Any one of VP ₁ and VQ _{2 to} VQ _N is selected and output according to the row number data 20. The data comparator 16 compares the output value of the counting circuit 15 with the output value of the multiplexer 18 and outputs a coincidence signal 24 when they coincide with each other. The vertical display start signal generating circuit 17 including a latch receives the coincidence signal 24 output from the data comparator 16 and starts outputting the vertical display start signal 24, and receives the row display completion signal 21 to display the vertical display. The output of the start signal 24 is stopped.

Next, the vertical display start position control operation of the vertical display start position control circuit 6B will be described. In this vertical display start position control circuit 6B, the counter circuit
After 15 is reset, the counting circuit 15 counts the pulses of the horizontal synchronizing signal 13 and sequentially increases the output value for each horizontal synchronizing signal 13, and the output value is also reset for each row display completion signal 21. . On the other hand, the multiplexer 18 determines the vertical display start position data VP ₁ ,
Any one of VQ _{2 to} VQ _N is selected and sent to the data comparator 16.

Immediately after the trailing edge of the pulse of the vertical synchronization signal 14, the line number data 20 indicates a display line L ₁ of the first row, since sending a vertical display start position data VP ₁ display line L ₁ to the data comparator 16 When the output value of the counting circuit 15 matches the vertical display start position data VP ₁ , a match signal 24 is generated, and the vertical display start signal generating circuit 17 starts outputting the vertical display start signal 22. The direction display start signal 22 is sent to the video RAM control circuit 8 and the CRT display output circuit 9 (see FIG. 3) to start displaying the character on the display row L ₁ . And
When the row display completion signal 21 given from the timing indicator 4 (see FIG. 3) is input to the vertical display start signal generating circuit 17, the output of the vertical display start signal 22 is stopped and the display row L ₁ Complete the display of the character.

Subsequently, the line number data 20 is changed to the data indicating the display lines L ₂ of the second row, since the vertical display start position data VQ ₂ display line L ₂ is sent to the data comparator 16, the counting circuit 15
When the output value of is coincident with the vertical display start position data VQ ₂ , the coincidence signal 24 is generated, the vertical display start signal generating circuit 17 starts outputting the vertical display start signal 22, and the vertical display start signal is generated. 22 is a video RAM control circuit 8 and C
It is sent to the output circuit 9 for RT display (see Fig. 3), and travels L ₂
The display of the character starts. Then, the row display completion signal 21 provided from the timing generator 4 (see FIG. 3)
Is input to the vertical display start signal generation circuit 17, the output of the vertical display start signal 22 is stopped, and the display of the character in the display row L ₁ is completed. After that, the line number data 20 is sequentially changed so that the characters of the _{third to Nth} display lines L _{3 to} L _N are sequentially displayed from the positions corresponding to the vertical display start position data VQ _{3 to} VQ _N. Be seen.

The above operation is repeated for each frame
Unless the contents of the RAM 7 are changed, the same character is displayed on the screen P over a plurality of frames.

Also, by changing the vertical display start position data VP ₁ of the first display line L ₁ of the register 19 for each frame, vertical scrolling of the character display on the screen is not performed and the line spacing is not changed. The characters in each line can be evenly moved in the vertical direction.

It is assumed that the data transfer from the control microcomputer 2 to the vertical display start position control circuit 6B is completed in advance through the interface 3.

As described above, when the vertical synchronizing signal 14 is input to the CRT display circuit 1 of FIG. 1, each of the first to Nth display rows is displayed.
A vertical display start signal 22 that permits display start is output for each of L _{1 to} L _N. The vertical display start signal 22 generated for each of the display rows L _{1 to} L _N starts the operation of the CRT display output circuit 9 and the VRAM control circuit 8 (see FIG. 3) as described above, and The display character code stored in the video RAM 7 accesses the character ROM 10 according to the timing signal generated by the timing generator 4 by the clock 12, the horizontal synchronizing signal 13 and the vertical synchronizing signal 14. The output of the character ROM 10 becomes time series data synchronized with the horizontal synchronizing signal 13 by the shift register 11 and is input to the CRT display output circuit 9. The CRT display output circuit 9 outputs a CRT display signal synchronized with the vertical synchronizing signal 14 and the horizontal synchronizing signal 13, and this is supplied to the CRT display device, so that the character is displayed on the screen.

In the above embodiment, the row display completion signal 21 is used to reset the counting circuit 15, so that the lower end of the previous display row is the starting point for determining the vertical display position of the display row. However, if the signal generated at a certain position of the previous display line, for example, the upper end is created and the counting circuit 15 is reset by this signal, the upper end of the previous display line is set as the starting point. be able to. That is, the starting point for determining the vertical display position of each display line may be a fixed position with respect to the immediately preceding display line.

〔The invention's effect〕

According to the CRT display circuit of the present invention, all display lines on the screen can be moved uniformly by only changing the vertical display start position data of the first display line on the screen.
It is possible to significantly reduce the large amount of data transfer that becomes a problem when it is necessary to uniformly change the vertical display start position of all display lines, such as when performing vertical scroll on the screen. To remarkably reduce the load on the control microcomputer when rewriting the vertical display start position data when the vertical display start position of all display lines is changed evenly, for example, when vertically scrolling on the screen. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a vertical direction display start position control circuit in a CRT display circuit according to an embodiment of the present invention, and FIG. 2 shows the concept of vertical direction display start position data in the configuration of FIG. The conceptual diagram shown on the screen and Fig. 3 are conventional CRTs.
FIG. 4 is a block diagram showing the configuration of the display circuit, and FIG.
FIG. 5 is a block diagram showing the configuration of the vertical display start position control circuit in the CRT display circuit. FIG. 5 is a conceptual diagram showing on the screen the concept of vertical display start position data of the conventional vertical display start position control circuit. Is. 1 ... CRT display circuit, 2 ... control microcomputer, 3 ... interface, 4 ... timing generator, 5 ... horizontal display start position control circuit, 6B ... vertical display start position control circuit, 7 ... Video RAM, 8 ...
Video RAM control circuit, 9 …… CRT display output circuit, 10 ……
Character ROM, 11 …… Shift register, 12 …… Dot clock, 13 …… Horizontal sync signal, 14 …… Vertical sync signal,
15 …… Counter circuit, 16 …… Data comparator, 17 …… Vertical display start signal generating circuit, 18 …… Multiplexer, 19 ……
Register, 20 ... Line number data, 21 ... Line display completion signal, 22 ... Vertical display start signal, 23 ... OR circuit, 24
…… Match signal, 25 …… CRT display signal

Claims (1)

(57) [Claims] 1. A CRT display circuit for displaying a character string consisting of a plurality of characters, symbols and numbers on a CRT screen, wherein vertical display start position data of a first display line is vertically synchronized. The signal is used as a starting point and is stored as a value corresponding to the number of pulses of the horizontal synchronizing signal included up to the vertical display start position, and the vertical display start position data of each display row from the second row onward is stored. A register that is stored with a value corresponding to the number of pulses of the horizontal synchronizing signal included in the display row at a certain position as a starting point and up to the vertical display start position of the display row, and is reset at each starting point to perform horizontal synchronization. A counting circuit for counting the number of signal pulses, a data comparator for comparing the output value of the counting circuit with vertical display start position data corresponding to the display row stored in the register, and the data comparator. CRT display circuit having a vertical display start position control circuit which is constituted by a vertical display start signal generation circuit for generating a vertical display start signal of the corresponding display line in response to the generation of the match signal.