JPS6228473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT (Cathode Ray Tube) display system, and is particularly directed to a raster scan type CRT display system.

For example, when displaying characters using a CRT, a raster scan type display device writes character information in ASCII code to a refresh memory configured with a shift register, and sequentially stores this content in synchronization with raster scanning. Read it and send it to the character generation circuit. This character generation circuit is a ROM
(Read Only Memory), and inputs the character information in 8-bit ASCII code read from the refresh memory and the timing signal of CRT screen scanning, and displays the information necessary for displaying an alphabet consisting of, for example, 5 x 7 dots. This is to form a pulse signal in the scanning order of the screen to make only the dots shine by brightness modulation.

In this CRT display device, in order to display different screens in an overlapping manner, two sets of refresh memory and character generation circuits are prepared and operated simultaneously, and a signal synthesis circuit is used to synthesize the character generation outputs of both. It is conceivable to obtain overlapping screens.

However, this method requires a plurality of refresh memory access circuits and character generation circuits, as well as a signal synthesis circuit, so that the system inevitably becomes larger and more complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CRT multiple display system that allows multiple display screens to be obtained using a system with a simple configuration.

Another object of the invention is to provide a new CRT display method.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a CRT display system showing one embodiment of the present invention.

The principle of CRT display system can be explained as follows. In order to display characters on a CRT screen, it is necessary to constantly scan the CRT screen and refresh the screen. For this reason, CRT display devices store the data to be displayed in memory, and this content also needs to be refreshed. A method is used in which the screen is refreshed. The refresh memory that stores this data is equipped with an MPU (Micro Processor).
Data is written from the processing system including the MPU, but since the data written by the MPU usually uses ASCII codes, etc., it cannot be displayed as characters on the screen as it is, so the character code is converted to a character pattern. A character generation circuit is used for this conversion.

A character generation circuit is a type of circuit that generates character patterns using character codes and scanning line numbers as addresses.
It is a ROM. Normally, the time required for one dot to form a character is as short as a few nanoseconds, so character patterns are generated by reading each row or column of character dots in parallel, converting this into a serial pulse train, and displaying it on a CRT.

In the figure, numeral 1 is a CRT display control circuit CRTC, which is composed of an LSI (large scale integrated circuit). The CRTC 1 is composed of an internal register group for storing the screen configuration, horizontal and vertical timing generation circuits, a linear address generation circuit, a cursor control circuit, and a light pen detection circuit. The horizontal and vertical timing generation circuits form RA, DISP, and SYNC signals, of which signal RA is a raster address signal and is used as one input signal of the character generation circuit 4. Further, the signals DISP and SYNC are used as video control signals.

The linear address generation circuit is connected to a refresh memory (3a or 3) used for refreshing the screen.
It forms the address signal MA of b), and this address signal MA causes the refresh memory (3
a or 3b) is accessed periodically to refresh the screen.

The light pen register stores the address generated by the linear address generation circuit upon receiving a light pen strobe signal in order to store where the light pen is located on the screen. The cursor control circuit controls the position of the cursor on the screen, the shape of the cursor, and the blinking of the cursor.

Such an operation is performed by the dot timing logic 1 which receives the oscillation output formed by the oscillation circuit 11.
The character clock signal CLK formed in step 2 is used as a reference clock.

The internal registers include a horizontal total character count register that programs the number of characters per scanning line including the horizontal retrace period, a horizontal display character count register that programs the number of display characters per line, and a horizontal display optimum position on the CRT screen. In addition to the horizontal synchronization position register for syncing, and the same various registers for the vertical direction, it also includes a start address register for programming the read start address of the refresh memory, and an address register for specifying these various addresses. be.

The CRT 1 has a program for forming a screen written therein by a processing device such as the MPU 10, for example. This program is written through address bus A and data bus D.

2 is a refresh address selector AS, which selects the input side and the output side of address information. The input side selection is as above.
The address from CRTC1 or MPU10 is selected. That is, the address from the CRT 11 is used to read character codes for display, and the address from the MPU 10 is selected. That is, the address from the CRT 11 is used to read character codes for display, and the address from the MPU 10 is used to write character codes into the refresh memory (3a or 3b). This write information is input from the data bus D through the bus driver 9.

The selection of the output side is to send the address information as described above to either the refresh memory (3a or 3b).

3a and 3b are refresh memories, respectively.
RM, which stores the character code to be displayed.

Reading of the refresh memories 3a and 3b for display is performed in synchronization with scanning from the CRTC 1 to the CRT.

Reference numeral 4 denotes a pattern generation circuit PG, which is composed of a ROM having the above-mentioned refresh memory output and raster address signal RA as address inputs.

Reference numeral 5 denotes a conversion circuit that converts the ROM output read out in parallel into serial data, and is used to form a pulse train signal for bright spot modulation.

A video control circuit VC 6 adds a synchronizing signal SYNC from the CRTC 1 to the luminance modulation signal to form a video signal necessary for the CRT display device 7.

In this embodiment, a switching circuit 8 for controlling a refresh address selector is provided in order to display the contents of the refresh memories 3a and 3b for each display in an overlapping manner.

When there is an overlap display command OV, this switching circuit 8 receives a synchronizing signal as shown in FIG.
Each time the vertical synchronization signal USYNC of SYNC arrives
Refresh memory address MA from CRTC1
is input alternately from refresh memory 3a to 3b or from refresh memory 3b to refresh memory 3a during the vertical retrace period.

Therefore, the contents displayed on the CRT 7 are displayed by overlapping the contents of the refresh memories 3a and 3b. In other words, in a CRT display system that performs refresh 60 times per second, even-numbered refreshes display the contents of the refresh memory 3a, and odd-numbered refreshes display the contents of the refresh memory 3b, allowing for overlapping display. .

In this case, the number of refreshes performed by each refresh memory 3a, 3b is halved, and the brightness of the display screen is reduced.
You can do it automatically with OV. (not shown).

Note that when selectively displaying the contents of the refresh memory (3a or 3b), the switching circuit 8
At the same time as stopping CRTC1 or MPU10
etc. to control the refresh address selector and select a specific refresh memory.

According to this embodiment described above, the addition of a switching circuit makes it possible to display an overlap display, and it is possible to achieve an overlap display using a simple system.

Note that the contents of the refresh memory may be displayed alternately within the horizontal blanking period. That is, it can be realized by switching not every frame as described above but every raster. In this case, for example, if the odd numbered rasters are used as the refresh memory 3a and the even numbered rasters are used as the refresh memory 3b for odd frames, then
For even-numbered frames, even-numbered rasters are used as the refresh memory 3a, and odd-numbered rasters are used as the refresh memory 3a.
It is necessary to make an assignment such as b, which makes the control method somewhat complicated.

Furthermore, even when displaying the contents of the refresh memory alternately during the vertical blanking period, the display may be switched every two frames. In this case, it is necessary when using an interlace scanning type CRT. This is because one image is obtained in two frames.

Also, the switching circuit Su is not particularly necessary and CRTC
1, if there is a function to switch the memory to be refreshed, the above vertical pulse is used to interrupt the MPU 10 and the CRTC 1 is controlled within the above period to alternately read the refresh memory for each frame. can be done.

Note that three or more refresh memories 3 may be accessed in sequence, but this increases screen flickering, so it is possible to have three or more refresh memories 3 at most.
In other words, the limit would be triple display (in the case of 60 frames/second).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating the operation of the main parts thereof. 1... CRT display control circuit, 2... Refresh address selector, 3a, 3b... Refresh memory, 4... Pattern generation circuit, 5
...Conversion circuit, 6...Video control circuit, 7...
CRT, 8...Switching circuit, 9...Bus driver, 10...MPU, 11...Oscillation circuit, 12...
...dot counter.

Claims (1)

[Claims] 1. In a CRT display system in which contents are sequentially retrieved from a storage area in which information to be displayed is stored in synchronization with the raster scanning of the CRT, and a display corresponding to the retrieved contents is performed on the CRT screen. a display state in which a first display corresponding to content retrieved from a first storage area and a second display corresponding to content retrieved from a second storage area are alternately performed in mutually different display frames; The CRT screen has at least a display corresponding to the content retrieved from the storage area and a display state to be performed in each display frame, and the brightness of the CRT screen is adjusted in accordance with changes in the display state. was characterized by
CRT display method.