JPS61165788A - Crt display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT (Cathode Ray Tube).
e: "Cathode ray tube) display system, particularly the raster scan CRT display system.

For example, when displaying characters using a CRT, a raster scan type display device writes character information based on ASCII codes into a refresh memory made up of registers, and stores this content in synchronization with raster scanning. Read the first character and send it to the character generation circuit. This character generation circuit is a ROM (Read Only Memory).
y), character information and CR in 8-bit ASCII code read from refresh memory.
For example, if the T screen scanning timing signal is input,
The alphabet display button consisting of 7 dots forms a pulse signal for scanning the screen to illuminate only the necessary points by brightness modulation.

In this CRT display device, refresh memory,
It is conceivable to prepare two sets of character generation circuits and operate them simultaneously, and to synthesize the outputs of both characters using a signal synthesis circuit to obtain an overlapping screen.

However, this method requires a plurality of refresh memory access circuits and character generation circuits, as well as a signal synthesis circuit, so the system inevitably becomes larger and more complex.

Regarding display devices, for example, Japanese Patent Laid-Open No. 52
-147026.

An object of the present invention is to provide a CRT multiple display system that allows multiple display screens to be obtained using a system with a simple configuration.

Another object of the present invention is to provide a new CRT display method.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a CR7 display system showing one embodiment of the present invention.

The principle of the CR7 display system can be explained as follows.

In order to display characters on a CRT screen, it is necessary to constantly scan the CRT screen and refresh the screen. For this reason, CRT display devices store the data to be displayed in memory, and then display the data based on this content. A method is used in which the screen is reflected. The refresh memory 17 that stores this data contains MPU (Micro
Data is written from the processing system including Process+5sorUnit), but the data written by the MPU usually uses ASCII codes, etc., so it cannot be displayed as characters on both sides as it is, so the character code is converted to a character pattern. There is a need,
A character generation circuit is used for this conversion.

The character generation circuit is a type of ROM that generates character patterns using character codes and scanning line numbers as addresses.

Since the time required for one dot of normal characters is as short as several nanoseconds, character patterns are generated by reading character dots in parallel rows or columns, converting them into a serial pulse train, and displaying it on a CRT.

In the figure, 1 is a CRT display control circuit (CR
TC) and is composed of LSI (large scale integrated circuit). This CRTCI has a group of internal registers that stores the configuration of one screen, and timing generation circuits for horizontal and vertical squares.
It consists of a linear address generation circuit, a cursor control circuit, and a light pen detection circuit. The horizontal and vertical timing generation circuits form signals RA, DISP, and 5YNC, among which the signal (RA) is a raster address signal and is used as one input signal of the character generation circuit 4. In addition, the signal (DISP.

5YNC) is used as a video control signal.

The linear address generation circuit forms an address signal (MA) for the refresh memory (3a or 3b) used for refreshing both sides, and this address signal (
MA ) depending on 7 retouch memo'l (3a or 3b
) is accessed periodically to make a double-sided Il7 retrieval.

The light pen register determines how far on the screen the light pen [K
When a write bend strobe signal is received and received to store whether the address exists, the address generated by the linear address generation circuit is stored. The cursor control circuit controls the position of the cursor on the screen, the shape of the cursor, and the blinking of the cursor.

Such an operation is performed using a character clock signal (CLK) generated by the dot timing logic 12 which receives the oscillation output generated by the generation circuit 11 as a reference clock.

The internal registers include a horizontal total number of characters register that programs the number of characters per scanning line including the horizontal retrace period, a horizontal display character number register that programs the number of characters displayed per line, and a register that programs the optimal horizontal position on the CRT screen. In addition to the horizontal synchronization position register to perform vertical synchronization, and various similar registers for vertical processing, a start address register to program the read start address of the refresh memory, and an address register to specify these various addresses. It is.

A program forming a screen is written into this CRTI by a processing device such as, for example, MPU10. This program is written through address bus A and data bus D.

Reference numeral 2 denotes a fresh address selector (AS) which selects the forward side and output side of address information. The choice on the long side is the above CRTCI or GtM
This is to select an address from the PU 10. That is, the address from CRT11 is used for reading character codes for display, and the address from MPU10 is selected. That is, the address from CRTII is used to read the character code for display, and the address from MPU10 is used to write the character code to the refresh memory (3a or 3b). This write information is input through the data bus D or the path driver 9.

The selection on the output side is to send the address information as described above to either the refresh memory (3a or 3b).

(3a, 3b) are Refreshier Memo 1 (RM), respectively.
) and stores the character code to be displayed.

Reading of the refresh memories (3a, 3b) for display is performed in synchronization with the scanning of the CRT from the CRTCI.

Reference numeral 4 denotes a pattern generation circuit (PG), which is constituted by a ROM whose address inputs are the refresh memory output and the last 4 address signal (RA).

Reference numeral 5 denotes a conversion circuit for serially converting the ROM output read out in parallel, and is used to perform brightness modulation and form a pulse train signal.

A video control circuit (VC) 6 adds a synchronization signal (SYNC) from the CRTCI to the luminance modulation signal to form a video signal necessary for the CRT display device 7.

In this embodiment, a switching circuit 8 for controlling the refresh address selector is provided in order to display the contents of the refresh memo II (3a, 3b) for each display in an overlapping manner.

This switching circuit 8 uses an overlamp display command (OV
), the synchronization signal (SYNC
), each time a vertical synchronization signal (USYNC) arrives
The refresh memory address (MA) from the TCI is transferred from the refresh memory (3a) to (3b) within the vertical retrace period.
), or from the 7 Lexie memory (3b) to (3a) and input alternately.

Therefore, the contents displayed on the CRT 7 are displayed by overlapping the contents of the seven renocie memories (3a, 3b). In other words, in a CRT display system that refreshes 60 times per second, even-numbered refreshes store the contents of the refresh memory (3a), and odd-numbered refreshes store the contents of the refresh memory (3b).
), allowing for overlapping display.

In this case, the number of refreshes by each refresh memory (3a, 3b) is halved and the brightness of the display screen is reduced, so the brightness adjustment of the CRT display device 7 is
It may be set to 5 so that it is automatically performed using the overlap signal (Ov) from the CI.

(not shown).

In addition, when selectively displaying the contents of the refresh memory (3a or 3b), the switching circuit 8 is stopped and the refresh address selector is controlled by the CRTCI or MPU10, etc. to select a specific refresh memory.

According to this embodiment described above, the addition of a switching circuit makes it possible to display an overlap display, and it is possible to achieve an overlap display using a simple system.

Note that the contents of the refresh memory may be displayed alternately within the horizontal blanking period. That is, it can also be realized by switching not every frame as described above but every raster. In this case, for example,
For odd frames, refresh memory (3
a), and when even-numbered lamps are used as refresh memory (3b), it is necessary to make allocations such that when even-numbered frames are busy, even-numbered lamps are used as refresh memory (3a), and odd-numbered lamps are used as refresh memory (3b). , the control method becomes somewhat complicated.

Furthermore, even when displaying the contents of the refresh memory alternately during the vertical blanking period, the display may be switched every two frames. In this case, it is necessary when using an interlaced scanning type CRT. This is because one image is obtained in two frames.

Also, there is no need for a switching circuit (Su), and CRTCI
If there is a function to switch the memory to be refreshed, the above vertical pulse is used to refresh the MPU.
By interrupting l0 and controlling CRTCI within the above period, it is possible to alternately read the refresh memory frame by frame.

Note that three or more refresh memories 3 may be accessed in sequence, but this will increase screen flickering, so the limit is three or more, that is, triple display (at 60 frames/second). ).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation of the main part. 1...CRT display control circuit, 2...Refresh address selector, (3a + 3b)...
・Refresh memory, 4... Pattern generation circuit, 5
...Conversion circuit, 6...Video control circuit, 7...C
RT, 8... switching circuit, 9... bus driver,
1o...MPU. 1st Figure 1σ 2nd Figure 3YMC Mi...7'b

Claims (1)

[Claims] In synchronization with the raster scanning of the CRT, contents are sequentially retrieved from a storage area in which information to be displayed is stored, and
In a CRT display system in which a display corresponding to the content retrieved from the first storage area is displayed on the screen of the T, at least between multiple frames, a display corresponding to the content retrieved from the first storage area and a display corresponding to the content retrieved from the first storage area are displayed on the screen of the CRT. A CRT display system characterized in that a display corresponding to content retrieved from a second storage area different from the first storage area is performed.