JPS60208794A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] <Technical description of the invention> What is this invention? For example, this paper relates to a display device used in a woodcutter's open side device or control side 1/stem, etc., and in particular relates to an improvement of the display device so as to display multiple pieces of image information in an overlapping manner (★).

<Technical Background of the Invention> For example, in a measuring instrument equipped with a display device such as a spectrum analyzer, the measurement results are converted into AD and converted into ADff because the measurement results are easy to store and the processing of each signal is easy. Digital signals are loaded into a memory, the information loaded into the memory is read out, and a frequency spectrum, such as a frequency spectrum, is displayed on a display screen.

For example, in such a device, it would be convenient if the previous measurement result and the next measurement result could be superimposed on one screen and displayed as a lower one, making it easier to compare.

<Prior Art> Projecting a plurality of pieces of image information on one screen using a fingernail has been practiced for a long time. The method is to write multiple 1ifii (. This is the way to get it out.

When this method is used, the following disadvantages arise.

Since multiple pieces of image information are written to one reflex memory, the image information once written to the reflex memory may be erased individually or partially. The disadvantage is that it is not possible to perform operations such as changing the

Also, especially - RI'Tu with image 1 tip-off at the swearing-in ceremony.
In the printing method, multiple images 1'i'i
There is an inconvenience that it is not possible to display information over and over again.
Purpose of the Invention> The present invention provides a display device that displays a plurality of picture information in a single direction, in which it is easy to erase each piece of picture information individually or change a part of it. The purpose of this project is to provide a display gi# that can be performed.

<Structure of the Invention> The display device according to the present invention comprises: A. Abdominal glue fresnon memory, each of which stores one screen worth of memory, and B. Any number of refresh memories among the plurality of refresh memories. A memory specifying means to be specified, and C6 time-sharing of this specified refresh memory.
D. A video signal converter that converts the image information read from each refresh memory into a video signal; E. A ωG output means for outputting ωG from the specified arbitrary number of refresh memories output from the video signal converter. and a display that displays the read image information in an overlapping manner.

By providing a plurality of refresh memories in this way, the image information V stored in the valley refresh memory can be easily erased individually or partially changed. Furthermore, even if there is a refresh memory of the one-write type, it is possible to display multiple pieces of image information in a superimposed manner.

<Embodiments of the Invention> A display device according to the present invention will be described in detail below along with Examples.

FIG. 1 shows the overall configuration of a display device according to the present invention.

Block 104B, 1 surrounded by a dotted line in FIG.
04C, 104D and 108 show the configurations added in this invention.

First, the configuration and operation VC of a normal display device will be explained in advance.

In a normal display device, there is only one fresh memory 104A.
The readout output is given to a video signal converter 109 formed by a 4'M parallel-to-serial converter, and the converted output is sent to the display 10.
7 and displays the image (i♂1 construction).

Reading from refresh memory 104A is performed by a read address signal generated by read means 106. That is, the reading means 106 receives the clock pulse generated by the display control 11 path 105 and generates an exit address signal for the refresh memory 104A. This read address signal is applied to multiplexer 102.

? In addition to the read address signal, the multiplexer 102 receives a nested address signal from the microcomputer 101. In other words, the microcomputer is normally written one by one in read mode, but when writing is required, the microcomputer 1
For example, an interrupt is generated at 01 to enter the write mode. In the write mode, writing is performed in refresh memory 104A according to the write address output from microcomputer 101. Multiplexer 102 operates to switch the address signal applied to refresh memory 104A according to read mode and write mode. This switching operation is performed by the transparent selection signal SEL given from the microcomputer 101.
It is carried out by

Further, the image information to be input into the refresh memory 104A[tkF is applied to the refresh memory 104AVc via the data bus 111 and the buffer 103, and writing is performed.

<Description of Main Parts of the Invention> In this invention, a reflex memory +Xe is provided in such a display device, and the memory specifying means 10
8. Reference numerals 104B and 104 in the figure
3. These refresh memories 140A, 140B, 14.1) C, 14
Each address terminal of 0D is connected to an address bus ill' (and accessed by an &out address signal or write address signal selected by multiplexer 102).

The memory specifying means 108 selects these multiple memory memories 104A, 104B, 104C9104,1.
) in the list to use.
Then, specifying it and sequentially reading out the FRESSON memory in a time-division manner Nf41 is performed. Refresh memory" o4
Switching between A, 104B, 104C, and 104D is performed by synchronizing the vertical synchronizing signal V output from the display device 111 and 11'4105.

A specific embodiment of the memory specifying means 108 is shown in FIG. The example in Figure A2 shows a structure in which up to four flexible memories can be selectively specified.

In FIG. 2, 201 indicates a latch circuit. Numerical data of the desired refresh memory is given from the input terminal D+ of this latch circuit 201 and the D21C microcomputer 101. LS indicates a latte command signal.

The latch output of the launch circuit 201 is applied to lower bit input terminals A and H of a 4-bit presettable down counter 202, for example. Top 2 input terminals C, DK
In this example 1, gives L logic. down counter 2
The vertical synchronizing signal V is given to the clock input y#a child CK of 02, and the count is down counted every time the vertical synchronizing signal V is given. Counting output terminals Q+ and Q of the down counter 202
2 is the output terminal of the lower 2 bits, and this output terminal Q+
, Q2 are connected to multiplexer 1102K and sent to address bus 112 as signals of the upper two bits of the read address. The outputs of the output terminals Q1 and Q2 are also given to the Nant gate 203, and the output of the Nant gate 203 is supplied to the load terminal LOAD K of the down counter 202.

Reflex memories 104A, 104B, 104
C.

104D is 'hj of the upper 2 bits of address bus 112.
The Mi output operation is selected by @. That is, when the upper two bits of the signal are ro, OJ, the first refresh memory 104A is selected, and when the signals of the upper two bits are ro, OJ, the second refresh memory 104B is selected, and ro, 1''.
When , the third refresh memory 104C is selected and rl
, 1'', the fourth refresh memory 104D is selected.

The interior of each refresh memory 104A-104D is escaped by an address signal output from escape means 106.

<Operation of the invention> In the circuit shown in FIG. 2, the human power terminal D+ of the latch circuit 201
, D2 is given, for example, "o, o", the down counter 202 is preset to "ro, o".

Therefore, the output terminals Q1 and Q of this down counter 202
tJt Normal K r Output O, OJ and address bus 11
2) Hold the 1st 2 bits at ro, o. Therefore, in this state, only the first refresh memory 17104A is selected and read operation is performed, and the first refresh memory IJ
Only the image information stored in 104A and 4' is displayed on the display 107.
will be displayed on the screen.

The input terminal D r + D 2 K of the latch circuit 201, for example "].

0”, the down counter 202 is set to “1°0”.
” is preset. This A fruit and vegetable down counter 20
The states of the output terminals Q1 and Q2 of 2 repeat the states rl, OJ, ro, and OJ every time one vertical synchronizing signal (2) is input. When the second reflex memory 104B is removed and the image information stored in the second reflex memory 104B is read out for one screen, a vertical synchronizing signal V is output, and this vertical synchronizing signal (■) causes the down counter 202 to be output. The output state becomes ``ro, 0'', the first refresh memory 104A is selected, and the first refresh memory 1θ4A executes the read operation.

Therefore, after the screen escaped from the second refresh memory 104A and displayed, the first refresh/you memo 1J10 is displayed.
The image information read from 4A is displayed, and the switching is done at the synchronous frequency Jυ], so it is as if the two screens are superimposed and %,? Looks like it's being served.

When the output state of the down counter 202 becomes rO, OJ, the Nant gate 203 detects this and provides a load command signal to the load terminal LOAD K of the down counter 202. When the vertical synchronizing signal V is applied to the clock input terminal CK while this load command signal is being applied, the contents of the launch circuit 201 are preset. Therefore, the counter 202 outputs the signals II and OJ given from the IIJ and latch circuit 201, thereby selecting the second refresh memory 104B. In this way, the first reflex memory 104A and the second reflex memory 10/IB are alternately ejected, and the two pieces of image information are displayed superimposed.

Next [Input terminal D+ of latch circuit 201, 02VCI
-0.

1” is given, the 1st. 2nd, 81'! 3 reflex memory memories 104A, 104B, and 104C are specified, and these three reflex memory memories 104A.

104B, 104. The image information stored in C is No1 [
The result is displayed on the display 107K.

Moreover, when the latch circuits 201 K r 1 and I J are latched, the first. Second. Third. Fourth reflex memory 104A, 104B, 104C, 104
D has been designated, and the four pieces of image information are combined and displayed on the display 107.

<Effects of the Invention> As described above, according to the present invention, an arbitrary number of multiple 1 non-reso/yu memories can be selected, and the contents can be summarized in Table 7Je gi10.
7K can be displayed in an overlapping manner. Therefore, it is convenient to be able to freely change or delete the contents of each of the 104A to 104D memories on the mi screen. The effect is particularly great when using a flexible memory that stores and reads data in a memory format.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the overall structure of the present invention, and FIG. 2 is a block diagram for explaining the layout of the mounting section of the present invention. 101: Microcomputer, 102: Multi-7 lexer, 103: Buffer, 104A to 104D: Fresh memory, 105: Display ηilf 4 circuit, 1
06: Reading means, 107: Display device, 108: Memo 1 designation means, 109. :Video signal converter, 111: Data bus, 112: Address nox.

Claims (1)

[Claims] (1) A: a plurality of glue fresh memories each having a storage capacity for one screen; B: memory designation means for specifying any one page of glue fresh memories among the plurality of glue fresh memories; and C0: this designation. D. Reading means for reading out the valley refresh memory in a time-division manner;
``A blowout signal converter that converts the J report into a video signal; A display device consisting of a display device that projects images and ν.