JPS5939053B2 - Storage element specification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for selecting a memory element that is an element or circuit having a memory function such as an arbitrary flip-flop in a logic circuit of a board such as an LSL printed board that has a limited number of external terminals. The present invention relates to a storage element designation method that allows test data to be directly written and read from the outside.

As logic circuits become more complex and the degree of integration of LSIs increases, circuit configurations that can freely read and write memory elements such as flipflops within logic circuits are becoming an important feature in testing logic circuits. be.

In other words, you can write data to a flip-flop in a logic circuit, then read it to check whether the data has been written correctly, or write an initial value to each flip-flop in a logic circuit to check the logic. The operation of a relatively small portion of a logic circuit can be investigated by, for example, examining the change in state of each flip-flop by applying a clock pulse to the circuit and operating the logic circuit. This makes it much easier to check whether a complex logic circuit operates normally than when testing the entire logic circuit as one black box.
However, in the conventional method, a large number of control signal terminals are required for inputting address information that specifies the storage element under test included in the logic circuit under test on the board from outside the board. Particularly in LSIs, the lack of terminals (pins) is a major problem that hinders high-density packaging, but it is not desirable to provide a large number of pins that are only used during testing.
That is, in LSIs and the like, there is a limit to the number of pins, and if a large number of pins are used for testing, the number of pins that can be used for normal operation decreases, making it impossible to achieve high density, which is a major problem.
The aim of the invention is to obviate the above-mentioned drawbacks. In other words, in the present invention, a logic function test does not involve a huge number of repeated calculations as in normal operation, and therefore high operating speed is not required. Therefore, the control signal for the test is input as a series of control pulses. , which reduces the number of control signal terminals. Therefore, the feature of the present invention is that by the control pulse applied via the input terminal,
In a storage element designation method that designates an arbitrary storage element in a logic circuit on a board, one input terminal sequentially inputs control pulses onto the board, and the control pulses input through the input terminal, A state circuit whose state changes is provided, and address information for selecting an arbitrary storage element and data input to or output from the arbitrary storage element are controlled by control pulses successively inputted from an input terminal. The purpose is to set specified information in the state circuit, specify the arbitrary storage element, and input data to the specified arbitrary storage element or output data from the specified arbitrary storage element.

Further, the state circuit may be a counter that adds up the number of control pulses input from the input terminal, or a shift register that stores a pattern of a control pulse train input from the input terminal. Hereinafter, the present invention will be explained in detail with reference to the drawings.

The figure shows one embodiment of the invention.

In the figure, CL is a clock terminal that inputs clock pulses that drive the logic circuit, CT is an input terminal, and DG is 1101 in the normal mode that allows the logic circuit to operate as intended.
1. In test mode, a terminal for switching between these two modes by applying a level of 521F';
C is a binary counter that totals the number of control pulses input from the input terminal CT, and the lowest pit is not used to specify the storage element under test, but is used as a switching digit to switch between writing and reading test data. do. DF is a differentiation circuit that differentiates the level of terminal DG and resets counter C using the differential pulse, and DC is a differentiation circuit that differentiates the level of terminal DG. 10! On when W
All output terminals representing 1 become 1, and terminal DG becomes 111
When it is 8, the decoder decodes the number represented by the contents of the digits other than the switching digits of the counter/C, and sets only the output terminal corresponding to that number to 7V1 and the others to WlO8. FO-Fn is a flip-flop, and TO-Tn is a decoder. An AND circuit, DO-Dn, whose one input is connected to the output terminal representing the decoder DGf)on, the other input to the clock terminal CL, and the output side connected to the clock input portion of the flip-flops FO to Fn, respectively. are data input terminals to flip-flop FO-Fn in normal mode, GO~
The output sides of the momme are connected to the input sides of the flip-flops FO to Fn, respectively, and when the terminal DG is 111゛, the input from the terminals DO-Dn is connected, and the terminal DG is 111゛.
When T is a selector that selects and outputs the input from the input/output terminal SC, the output side is connected to the input/output terminal SC,
Is the switching digit of counter C 110? ' When the level on the input side is cut off and does not appear on the output side, the impedance seen from the output side becomes high, and when the switching digit is 1111, the level on the input side is output directly to the output side, SO- One input of Sn is the decoder DC (
1) An AND circuit in which the output terminals representing o-n, the other inputs are connected to the output sides of the flip-flops FO-Fn, and the output side is connected to the input side of the gate T, B is the above circuit, etc. This is a board that accommodates. The terminals used for the test here are a clock terminal CL, a terminal DG for mode switching, and an input terminal C for inputting address information, etc.
T, and an input/output terminal SC for test data. However, since the clock terminal CL originally used in the normal mode is used for testing, there are three test-only terminals provided on the board B. The operation of the circuit shown in the figure will be explained below.

In the normal mode, the terminal DG is set to 1101. Therefore, each selector GO-monme is the terminal DO~
Select input from Dn and flip-flop FO~Fn
Since the total output of the decoder DC is 1111, the clock pulse is supplied to all the flip-flops through the AND circuit TO-Tn. Therefore, in the normal mode, by applying a clock pulse to the clock terminal CL, the flip-flops FO-Fn receive data input from the terminals DO-Dn, respectively. Terminal D
By changing the level of G to 11"1, the circuit shown in the figure enters the test mode. At this time, the counter C is reset by the differential pulse generated by the differential circuit DF due to the level variation of the terminal DG. Here, When 2m control pulses are manually applied from the input terminal, the output terminal of the decoder DC is 11F1 for the terminal representing m, and all other terminals are 710?1.In addition, the selectors GO to Momme select the input/output terminal SC side. Furthermore, since the switching digit is 110V1, the input/output terminal S
The input from C is applied as is to each flip-flop. However, since the clock pulse applied to the clock terminal CL is supplied only to the flip-flop Fm by the output of the decoder and the AND circuit TO-Tn, data is applied from the input/output terminal SC and one clock pulse is applied to the clock terminal CL. By giving the input/output terminal S
The data given from C is sent only to flip-flop Fm. Here, when one control pulse is input from the input terminal CT, the output of the decoder DC does not change, but the switching digit of the counter C changes to 11F1. One input of each AND circuit SO-Sn is connected to the output terminal representing 0 to n of the decoder DC, so the output side of the AND circuit SO-Sn, that is, the input side of the gate T, is connected to the flip-flop Fm. The corresponding value will appear. Since the switching digit is 7vrv, the value on the input side of gate T appears at the input/output terminal SC connected to its output side. Therefore, the value stored in flip-flop Fm can be read from input/output terminal SC. As described above, input terminal C
The number of control pulses input from T specifies the flip-flop to which test data is written or read.

By using the storage element specification method as described above,
There is one input terminal for inputting the address information of the storage element.
Therefore, the number of test terminals provided on the board can be reduced.

In the above embodiment, a counter is used as the state circuit, but a shift register may be provided instead, and the pit pattern may be input to this shift register from the input terminal CT. In addition to the flip-flop, the storage element may be a magnetic core, an IC memory, or the like.

[Brief explanation of the drawing]

The figure is a circuit diagram of a logic circuit according to an embodiment of the present invention. CT...Input terminal, C...Counter,
FO~Fn...Flip-flop, DC...
...Decoder, TOゝTn and SO~Sn゜゜゜゜゜゜゜AND circuit, Momme ~ Momme゜゜゜゜...Selector, T...
...Gate, CL...Clock terminal, DG...
...Terminal for switching between normal mode and test mode, SC...Test data input/output terminal, B...
····substrate.

Claims (1)

[Scope of Claims] 1. In a storage element designation method in which an arbitrary storage element in a logic circuit on a board is designated by a control pulse applied via an input terminal, one element that sequentially inputs control pulses onto the board and a state circuit whose state changes according to the control pulses inputted through the input terminal, and the address information for selecting an arbitrary storage element and the control pulses successively inputted from the input terminal. The state circuit is configured to set information specifying data input to or data output from the arbitrary storage element, and specifies the arbitrary storage element and data input to or output from the specified arbitrary storage element. A storage element designation method characterized in that data is output from the designated arbitrary storage element. 2. The storage element designation method according to claim 1, wherein a counter is provided as the state circuit to add up the number of control pulses input from the input terminal. 3. The storage element designation system according to claim 1, wherein a shift register is provided as the state circuit to store a pattern of a control pulse train input from the input terminal.