JPS5947394B2 - Variable length two-dimensional register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital shift register, particularly a variable length two-dimensional shift register.

Conventionally, in order to configure a shift register that can specify an arbitrary shift amount, that is, a variable length shift register, it has been constructed by combining several types of shift registers with different shift amounts. For example, specify the shift amount in binary numbers from 0 to 10.
In order to configure a variable length shift register that can be specified arbitrarily within the range of 23, 512, 256, 128, 64, 3
2, 16, 8, 4, 2, 10 bit shift registers
A minimum of several shift registers and a 10-circuit multiplexer are required. Further, a two-dimensional shift register used in a pre-processing circuit for image processing etc. is configured with these variable length shift registers, for example, when the input data signal is 8 bits.
, and is a two-dimensional shift register consisting of four lines. According to simple calculations, 8 sets of variable length shift registers are required for 4 lines, and in terms of the number of ICs, as mentioned above, each set is made up of approximately 20 ICs, so 20 sets x 8 sets. ×
4 lines ■ 640 pieces, like this 64...times or more I
Not only does this require a large amount of shift registers of various types with different shift amounts, but also requires a large amount of assembly and wiring work, resulting in a large economic loss.

An object of the present invention is to provide a variable length two-dimensional shift register with a simple circuit configuration without using several types of shift registers with different shift amounts.

According to the present invention, there is provided a ring counter that periodically generates a ring address signal having M values according to a specified shift amount M, a block counter that generates a block address signal, and the ring address signal and the block address. a memory for writing the output of the multiplexer described later into an address specified by the signal; a plurality of registers for latching the read signal of the memory; a multiplexer for selectively outputting the output of the register according to the block address signal; A variable length shift register is obtained that includes a decoder and gate circuit that outputs a latch signal to the plurality of registers in response to an address signal, and a timing generator that generates a timing signal.

The variable length two-dimensional shift register of this invention is suitable for use with recent ICs.
Rapid advances in RAM have made it possible to use large-capacity, high-speed, low-cost, and highly reliable memory, and the simple circuit configuration has made it possible to use I
Not only can the number of Cs be reduced, but also high speed and high reliability can be obtained.

If the same variable-length two-dimensional shift register as the circuit shown in FIG. 2 is constructed according to the present invention, at most 22 ICs are required, which is less than 1/15 of the conventional method, and as the two-dimensional size increases, The effects of the present invention can be exhibited. Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit example of a 10-bit variable-length shift register in which the input data 1-bit shift amount is specified from O to 1023 using a conventional method. Shift clock signal 204 is input to each shift register 20-29. A multiplexer (hereinafter referred to as MUX) 19 selects an input data signal of 100 or 512 bits from the input data signal 100 or 512-bit shift register 2 according to the 10th bit M9 signal 309 of the specified shift amount M signal 105.
MUXl8 selects and outputs the output of MUXl9 by the M8 signal 308 of the 9th bit of the shift amount M signal 105.
Select the output of the 256-bit shift register 28 or the output of the 256-bit shift register 28. do. Similarly, MUXl7, l6..., 11
, 10 are 8, 7, ..., 2 of the shift amount M signal 105
, 1st Bit M7, M6,..., Ml, MO signal 3
MUXl by 07,306,...,301,300
8, l7, . . . , 12, 11 output or 128 Bit shift register 27, 64 Bit shift register 26, .
..., selects and outputs the outputs of the 2-Bit shift register 21 and the 1-Bit shift register 20. Thus MUXl
An output data signal 101 is obtained by shifting the input data signal 100 from O by the shift amount specified by the shift amount M signal 105. FIG. 2 shows an example in which a four-row variable length two-dimensional shift register is constructed by using a variable length shift register as a two-dimensional shift register that is often used in pre-processing circuits such as image processing.

The shift amount M signal 105 and the shift clock signal 204 are input to each variable length shift register 30, 31, 32, 33. The input data signal 100 is input to the variable length shift register 30.
Enter. The output of the variable length shift register 30 is input to the variable length shift register 31 and outputs an output data A signal 101 to an external device (not shown). Similarly, the outputs of the variable length shift registers 31 and 32 are input to the variable length shift registers 32 and 33, and output data B signal 102 and output data C signal 103 to an external device. The variable length shift register 33 outputs the output data D signal 104 to an external device. Variable length shift register 3
0, 31, 32, and 33 are configured with the circuit shown in FIG.
In the case of each variable length shift register 30, 31, 32, 3
3 is composed of 8 sets of the circuit shown in FIG. 1, and a total of 8 sets x 4 rows = 32 sets are required. The number of ICs required for the circuit configuration in Figure 1 is 21 or more by simple calculation, and the number of ICs required for the circuit configuration in Figure 2 is 204 ICs x 8 sets x 4 lines =
More than 640 pieces are required.

It requires too many ICs compared to the function of simply shifting input data. The main drawback of requiring such a large number of ICs is that several types of shift registers with different shift amounts are used. FIG. 3 shows an embodiment of the present invention, and a case will be described in which the maximum size of the variable length two-dimensional shift register is 1024W0rd×4 rows and 4KW0rd is used as the memory.

A thin line indicates one signal line, a thick line indicates multiple signal lines, and the shift amount M signal 105 and ring address signal 1
06 is 10Bit 1 block address signal 107 is 2B
It is made up of IT. The block counter 43 is operated by the clock signal 200 from the timing generator 40 which generates various signals in response to the input start request signal 400, outputs the block address signal 107, and generates a ring clock signal with a period four times that of the clock signal 200. 204 is output. Ring counter 42, external device (not shown)
0, 1, 2, . . . , (M-
2), (M-1), 0, 1, 2... and O ~ (M-1)
This is a so-called ring counter which is well known as a digital circuit technology and outputs a ring address signal 106 having M values of . The memory 41 receives the block address signal 107 and the ring address signal 10 in response to a timing signal (hereinafter referred to as CE signal - chip enable signal) 202 that enables reading and writing to the memory 41 from the timing generator 40.
6 outputs the contents of the address specified in step 6 as a read signal 109, and uses a CE signal 202 from a timing generator 40 and a timing signal (hereinafter referred to as WE signal - write enable signal) 203 that specifies writing. The block address signal 107 and the ring address signal 106
The write signal 108 from the multiplexer 45 (described later) is written to the address specified in . The decoder 44 inputs the block address signal 107 and outputs the block 0 signal 20.
5. It outputs a block 1 signal 206, a block 2 signal 207, and a block 3 signal 208, and is the same as a normal decoder. The gate circuit 50 is connected to the timing generator 4
The data latch signal 201 from 0 is outputted to the gate by the block 0 signal 205 as a latch 0 signal 209.
Similarly, the gate circuits 51, 52, 53 connect the data latch signal 201 to the block 1, 2, 3 signals 206, 2.
Gate by 07,208 to latch 1, 2, 3 signal 2
Outputs 10, 211, 212. The register 46 converts the read signal 109 of the memory 41 into the latch 0 signal 20.
9 and outputs the output data A signal 101 to an external device. Similarly, the registers 47, 48, 49 transmit the read signal 109 to the latch l, 2, 3 signals 210, 211.
, 212, output data B, C, D signals 1
02, 103, and 104 are output to the external device. The multiplexer 45 receives an input data signal 100 from an external device,
The output data A, B, C signals 101, 102, 103
is selectively outputted by the block address signal 107 and outputted to the memory 41 as a write signal 108. That is, the multiplexer 45 is a multiplexer that selectively outputs one set of data from four sets of data in response to the block address signal 107. The timing signals associated with memory 41, CE signal 202, WE signal 203, and latch 0, 1, 2, 3 signals 209, 210, 211, 212, are well known in digital circuit technology using memory. Similarly, the timing generator 40 will not be described in detail since it can be easily realized using digital circuit technology. FIG. 4 is a time chart showing the main operations of the embodiment shown in FIG.

The block address signal 107 is generated by the clock signal 200.
The contents of 0, 1, 2, 3, 0, 1, etc. are cycled every 4 clocks, and the contents of the block address signal 107 are
A ring clock signal 204 is generated at the clock time of ''. That is, the ring clock signal 204 is the same as the clock signal 20.
Since the period is four times 0, the contents of the ring address signal 106 are the same during four ticks of the clock signal 200.
The block 0 signal 205 is the block address signal 107.
This occurs when the content of is “0”. Similarly, the block 1, 2, 3 signals 206, 207, 208 have the contents of the block address signal 107 "1,,,"2,,,"3,"
, occurs at the time of . Since the latch 0 signal 209 is the AND of the data latch signal 201 and the proc 0 signal 205, when the contents of the proc address signal 107 are generated at a timing of "0", the latch 1, 2, 3 signals 210,
211 and 212 are generated when the contents of the block address signal 107 are "1", "2-"3".
Now, the address for the memory 41 is generated by the block address 107 and the ring address signal 106, but in the case of this embodiment, the block address signal 107 is 2 bits, and the ring address signal 106 is 1 bit.
With a 0-bit configuration, the address has a total of 12 bits, and the block address signal 107 is assigned to the upper 2 bits, and the ring address signal 106 is assigned to the lower 10 bits. At the time when the ring address signal 106 is "i" and the block address signal 107 is "0", the address for the memory becomes address i+0, and the contents of the memory 41 are changed by the CE signal 202 indicated by the R mark. The output data A signal 101 is output as the read signal 109 and is latched in the register 46 by the latch 0 signal 209. After that, the write signal 108 (which is selectively outputted from the multiplexer 45 by the CE signal 202 and WE signal 203 indicated by the W mark) In this case, the input data signal 100) is written to address i+0. When the block address signal 107 clocks "1", the address for the memory is i+102.
4, the contents of the memory 41 are outputted as a read signal 109 by the CE signal 202 indicated by the R symbol, and latched in the register 47 by the latch l signal 210, resulting in output data B.
The signal 102 is output, and then the CE signal 20, indicated by the W symbol, is output.
The write signal 108 (in this case, the output data A signal 101 latched in the register 46' at the previous clock time) selectively outputted from the multiplexer 45 by the write signal 2 and the WE signal 203 is written to address i+1024. When the block address signal 107 clocks in at ``2'', the address for the memory becomes address i+2048, and the contents of the memory 41 are changed to the read signal 10 by the CE signal 202 indicated by the R symbol.
9, is latched in the register 48 by the latch 2 signal 211, and the output data C signal 103 is output.
After that, CE signal 202 and WE signal 203 indicated by W mark
The write signal 108 selectively output from the multiplexer 45 (in this case, the output data B signal 102 latched in the register 47 at the previous clock time) is written to address i+2048. When the block address signal 107 clocks "3", the address for the memory is i+3072.
address, and the CE signal 202 indicated by the R mark causes the memory 4 to
The contents of 1 are output as the read signal 109, and are latched in the register 49 by the latch 3 signal 212 and output data D.
The signal 104 is output, and then the CE signal 20, indicated by the W symbol, is output.
2 and the write signal 108 selectively outputted from the multiplexer 45 by the WE signal 203 (which is the output data C signal 102 latched in the register 48 at the previous clock time) is written to address i+3072. The write signal 108 at the time when the ring address signal 106 is “゛゜i” is:
When the clock address signal 107 is ゜"O", the input data signal 100 is selected, so the output data signal 101 is selected at the next clock time. In this case, the output data B signal 102 is selected.
At the first-next clock, the output data C signal 103 is selected and becomes "0". Also, the output data, A, B, C, D signals 101, 102 at the time when the ring address signal 106 is "i" and the clock address signal 107 is "3".
, 103, 104 are each ゜゛1゜'', 660-4≦1-
6609 la is obtained. FIG. 5 schematically shows the functions of FIGS. 3 and 4 with a focus on memory.

At the time when the ring address signal 106 is "i", the contents of the address i+0 of the memory 41 shown by the bold line are latched in the register 46 when the block address signal 107 is "0", and then the input data signal 100 is latched to the address i+0. When the block address signal 107 reaches "1", the contents of the address i+1024 indicated by the bold line are latched in the register 47, and then the output data A signal 101 latched in the register 46 is written to the address i+1024. written. When the block address signal 107 reaches "2", the contents of the address i+2048 indicated by the thick line are latched into the register 48, and then the output data B signal 102 latched in the register 47 is written to the address i+2048. When the address signal 107 reaches ゜“3゛, the contents of address i+3072 indicated by the bold line are in register 4.
After that, the output data C signal 103 latched in the register 48 is written to address i+3072. When the shift amount M is specified, when the block address signal 107 is clocked at ゜゜0゛, it becomes O~(M-1
) address is addressed and the block address signal 107 is 1024 to (M-1)+ indicated by diagonal lines.
Address 1024 is addressed and block address signal 1
When 07 is ゜゜2゛, 2048 ~ (M-
1) When address +2048 is addressed and the block address signal 107 is clocked at "3", addresses 3072 to (
Address M-1)+3072 is addressed. i.e. 4
The memory 41 of KW0rd receives the block address signal 10.
7, the block is divided into 4 blocks of 1KW0rd each, and each block is divided into 4 blocks of 1KW0rd each, and each block is divided into M blocks at positions O to (M-1) within the block.
Addresses are periodically addressed by the ring address signal 106, and data is read and written in a time-division manner. Hereinafter, the area of the memory 41 that is addressed when the block address signal 107 is "0°" will be referred to as block O.
At the same time, the areas of the memory 41 that are addressed when the block address signal 107 is "1-.degree.2-.3" are called blocks 1, 2, and 3, respectively. Now ring address signal 10
Assume that "0-"1-"O-"1" is written in the "0" position of bookmarks 011, 2, and 3 when 6 is "0".

At the time point after one cycle of the ring address signal 106, each block is addressed to the "0" position and is first read and then written, so the output data A, B, C, D signals 101, 102, 103, 104 are are respectively "0-"'1-
"0-"1", and the next input data signal 1 (1), for example "1", is written to block O, and blocks 1 and 2
, 3 contain the contents written in blocks O, 1, and 2, that is, output data A, B, C signals 101, 102, 10.
3, so "0-"l-゜"0- is written. After the next cycle, the output data A, B, C, D signal 10
1, 102, 103, 104 are each "1-゛O-"1-
“O” is obtained. Similarly, when the ring address signal 106 is at "i", the same operation is performed at the "i" position of each block. This is the same function as the general variable length two-dimensional shift register shown in FIG. , each block corresponds to a variable length shift register.Proc 0 corresponds to variable length shift register 30, and blocks 1, 2, and 3 correspond to variable length shift registers 31, 32, and 33. The ring clock signal 204 shown in FIG. 3 corresponds to the shift clock signal 204. In this embodiment, the block address signal 107 is assigned to the upper 2 bits and the ring address signal 106 is assigned to the lower 10 bits as an address for the memory 41. However, since there is only one address in the memory 41 specified by the address, it is clear that any allocation method may be used.

It is also easy to divide into arbitrary blocks.

In recent years, ICRAM has achieved great results, especially in terms of large capacity and high speed. Dividing large capacity memory has great cost advantages by saving the number of ICs, and also allows for time sharing due to its high speed. There is no major disadvantage in using it.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional generally used variable length one-dimensional shift register, Fig. 2 is a block diagram of a general four-row variable length two-dimensional shift register, and Fig. 3 is a block diagram of a variable length two-dimensional shift register of the present invention. FIG. 4 is a diagram showing a time chart of the main parts of the configuration diagram of FIG. 3, and FIG. 5 is a schematic diagram of the operational functions of FIG. 3.

Claims (1)

[Claims] 1 In a digital variable length shift register, the first
a block counter that generates a first address signal and a second clock signal using a clock signal; and a block counter that periodically generates a second address signal having M values using a specified shift amount M and the second clock signal. a ring counter which is generated in the block counter; a decoder connected to the block counter and decoding the first address signal; and a decoder connected to the decoder and gated with a first timing signal inputted by the output of the decoder, and a plurality of latches. a plurality of gate circuits that generate signals, and a second timing when the contents of an address specified by the first address signal and the second address signal are input, the gate circuit being connected to the block counter and the ring counter; A memory for outputting a read signal according to a signal and then writing a postscript write signal from a postscript multiplexer to the same address according to the second timing signal and a third timing signal inputted, and connected to the memory and the gate circuit. a plurality of registers that latch the read signal output from the memory with the latch signal to obtain an output data signal; the block counter; A variable length two-dimensional shift register including a multiplexer selected by the first address signal and outputted as a write signal to the memory.