JP2751382B2 - Shift path control system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a shift path control system used for testing or initial setting of an LSI.
In particular, the present invention relates to a shift path control system that performs shift path control with a small number of control signals.

2. Description of the Related Art Conventionally, as a test method or an initial setting method of an information processing apparatus and an LSI including a sequential circuit and a combinational circuit, there is a scan method described below.

In the scan method, a shift register called a shift path is formed by connecting flip-flops in the information processing device (hereinafter referred to as device) in addition to a circuit for normal operation in series, and arbitrary data is stored in the shift path. And reads the data.

FIG. 3 is a block diagram showing a configuration of a device in a conventional shift path control system.

Reference numeral 1 denotes an apparatus for performing inspection and initialization.
D1 is a data input terminal, D2 is a data output terminal, A1 is an address input terminal, A2 is an address output terminal, CK1 is a data shift lock signal input terminal, and CK2 is an address shift clock signal input terminal.

The clock switching circuit 2 switches the data shift clock signal c1 input via the data shift clock signal input terminal CK1 in accordance with the address signal a2 to shift the shift path S1.
~ SN.

The shift output selection circuit 3 switches the data signals output from each of the shift paths S1 to SN in accordance with the address signal a2 and outputs the output data signal d2 via the data output terminal D2.

The address register 4 inputs an input address signal a1 through an address input terminal A1 according to an address shift clock signal c2 input through an address shift clock signal input terminal CK2, and outputs the input address signal
a1 is sent as an address signal a2 to the clock switching circuit 2 and the shift output selection circuit 3, and an output address signal a3 is output via an address output terminal A2.

The input data signal d1, the output data signal d2, the input address signal a1, and the output address signal a3 are serial signals, and the address signal a2 is a parallel signal.

 Next, the operation will be described.

First, address information for selecting a shift path for writing data is supplied to the address register 4. In other words, the input address signal a1 is supplied to the address register 4, and the same number of shift clocks as the number of bits of the address register 4 are supplied to the address register 4 by the address shift clock signal c2 to perform the shift operation, whereby the address of the input address signal a1 The information is set in the address register 4.

The address information set in the address register 4 is supplied to the clock switching circuit 2 and the shift output selection circuit 3 by the address signal a2.

The clock switching circuit 2 selects one shift path based on the address information supplied from the address register 4, and supplies the data shift clock signal c1 only to the selected shift path. This data shift clock signal
By the c1, the data of the input data signal d1 is written to the shift path, and the data is output from the shift path. When writing and reading data to and from all the bits forming the shift path, it is necessary to supply the same number of shift clocks to all the bits forming the shift path to the shift path.

On the other hand, the shift output selection circuit 3 selects the shift path based on the same address information supplied to the clock switching circuit 2, and outputs data output from the shift path as an output data signal d2.

By the way, when the device 1 as shown in FIG. 3 is configured as an LSI, by connecting the input / output terminals of a plurality of LSIs to each other to form one shift path, the same operation as in the case described above is performed. Can be performed. This will be described with reference to FIG.

In FIG. 4, L _{1 to} L _K are K LSIs. In LSIL _K of LSIL ₁ ~ last stage of the first stage, the sign of the input and output terminals are common and the third FIG. The data input terminal D1 is
An output data signal d2 is input from the data output terminal D2 of I. The address input terminal A1 receives the output data signal a3 from the address output terminal A2 of the preceding LSI. Data shift clock signal input terminal CK1 and the address shift clock signal input terminal CK2 is being respectively connected commonly, each LSIL ₁ ~L _K common data shift clock signal c to
1 and an address shift clock signal c2 are supplied, respectively.

 Next, the operation will be described.

First, address information for selecting a shift path is
LSIL ₁ supplies the address register 4 of ~L _K. Supplies to input address information input address signal a1 from the address input terminals A1, by entering the address shift clock signal c2 from the address shift clock signal input terminal CK2, selects the shift path of the LSIL ₁ ~L _K . Here, since the address register 4 of the LSI are connected in series, all LSIL ₁ to set the address information in the address register 4 of ~L _K are bits of all LSIL ₁ ~L _K of the address register 4 It is necessary to supply the same number of shift clocks as the sum of the numbers to the address shift clock signal input terminal CK2.

Next, the writing and reading operations of the data and supplies the data shift clock signal c1 to the shift path of the LSIL ₁ ~L _K thus selected, the data input terminal D1
Input data signal d1 to supply input data information, and a data shift clock signal input terminal CK1.
Input the data shift clock signal c1. As a result, the input data information is written to the selected shift path, and output data information is output from the selected shift path. At this time, each of LSIL _{1 to} L _K
Are connected in series, so all LSIL _{1 to} L
During writing and reading data to all the bits of the shift path of the _K, the total LSIL ₁ ~L _K data shift the sum of the same number of the shift clock of the number of bits of the flip-flops constituting the shift path of the clock signal input terminal CK
Need to supply 1

In the case of FIG. 3 and FIG. 4 described above, one shift path is selected from a plurality of shift paths to write and read data. Therefore, a signal input / output to / from the device is an input data signal d1 as a data control signal. , A data shift clock signal c1 and an output data signal d2.
Input address signal a1, address shift clock signal c2,
And an output address signal a3. That is, a total of six signal lines are required.

[Problems to be Solved by the Invention] As described above, in the conventional shift path control system,
Two signals, a data control signal for inputting / outputting data and an address control signal for selecting one shift path from a plurality of shift paths, are required.

Therefore, when a device having a plurality of shift paths is configured as an LSI as described above, it is necessary to provide a large number of input / output pins for a large number of signal lines, resulting in an increase in manufacturing cost. Was.

[Means for Solving the Problems] The shift path control system of the present invention has the following units.

a) an address register that inputs and holds address information by an address shift clock signal; b) selects a shift path based on the address information held by the address register, and supplies a data shift clock signal to the selected shift path. First clock switching means; c) first shift selection means for selecting and outputting data output from the shift path selected by the first clock switching means based on the address information; d) mode signal mode E) a second shift output selecting means that operates according to the mode of the mode signal.

[Operation] When the mode signal indicates the mode for selecting the shift path, the address shift clock signal is supplied to the address register via the second clock switching means, and the output signal of the address register is supplied to the second shift output selection means. Select and output. As a result, predetermined address information is held in the address register, and this address information is sent to the first clock switching means and the first shift output selecting means.

On the other hand, when the mode signal indicates a mode for causing the shift path to perform a shift operation, the data shift clock signal is supplied to the first clock switching means via the second clock switching means, and the second shift output selecting means is supplied with the data shift clock signal. The output signal of the first shift output selecting means is selected and output. As a result, data is output from the selected shift path.

Embodiment Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an apparatus in a shift path control system according to an embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same or corresponding parts, and a description thereof will be omitted.

D ₁ is a data input terminal for inputting data, CK is a clock signal input terminal for inputting a clock signal, M
Is a mode input terminal for inputting a mode signal m described later, and _DO is a data output terminal for outputting data. Data to the input terminal D _1, shift path S1~SN to supply the input data information data signals d1 and address signals a1 provides input address information in the address register 4 is input. The shift path S1 is connected to the clock signal input terminal CK.
SNSN and a data shift clock signal c2 for shifting the address register 4 are input. From the data output terminal D _O, shift path S1~SN the output data signal
d2 and the output address signal a3 of the address register 4 are output.

That is, the data input terminal D ₁ and the clock signal input terminal
CK, and a signal to be input to the data output terminal D _O is duplicated, the signal types that these input and output is definite according to the mode of the mode signal m. The mode of the mode signal m includes the following two types depending on whether the address register 4 performs the shift operation or the selected shift path performs the shift operation.

A shift path selection mode in which the address register 4 performs a shift operation and sets address information in the address register 4 to select a shift path. A shift in which the selected shift path performs a shift operation to write and read data to and from this shift path. Pass shift mode.

1A is a device, 2A is a first clock switching circuit, 3A is a first clock switching circuit.
This is a shift output selection circuit. First clock switching circuit
2A and the first shift output selection circuit 3A correspond to the clock switching circuit 2 and the shift output selection circuit 3 shown in FIG.
This is for selecting a shift path in accordance with the address information a2 from the address register 4 to input / output data.

Reference numeral 2B denotes a second clock switching circuit, which switches the data shift clock signal c1 and the address shift clock signal c2 input from the clock signal input terminal CK to the first clock switching circuit 2A and the address register 4 according to the mode of the mode signal m. Output.
Reference numeral 3B denotes a second shift output selection circuit which selects and outputs an output data signal d2 input from the first shift output selection circuit 3A and an output address signal a3 input from the address register 4 according to the mode of the mode signal m. The data is output as a data signal d4.

 Next, the operation will be described.

First, address information for selecting a shift path is supplied to the first clock circuit 2A. That is, the providing and receiving an input address signal a1 to the data input terminal D ₁ of the address information in the address register 4, the mode input terminal M
, The second clock switching circuit 2B is switched to the address register 4 side, and the address shift clock signal c2 is supplied to the clock signal input terminal CK. As a result, the address shift clock signal c2 is supplied to the address register 4 via the second clock switching circuit 2B, and the same number of shift clocks as the number of bits of the address register 4 are supplied to the address register 4. As a result, address information is set in the address register 4. The address register 4 supplies this address information to the first clock switching circuit 2A. Thus, the first clock switching circuit 2A selects one shift path.

Next, the data shift clock signal c1 is supplied to the selected shift path to perform data write and read operations. That is, the input data signal to the data input terminal D ₁ d1
To input the input data information to the shift path and set the mode signal m to the mode input terminal M to the shift path shift mode, thereby switching the second clock switching circuit 2B to the first clock switching circuit 2A side, The data shift clock signal c1 is applied to the input terminal CK. As a result, the data shift clock signal c1 is supplied to the selected shift path via the second clock switching circuit 2B. As a result, the input data information is written to the selected shift path, and output data information is output from the selected shift path. Meanwhile, the first
The shift output selection circuit 3A includes a first clock switching circuit 2A
The shift path is selected on the basis of the same address information as the address information supplied to the second path, and the output data information output from this shift path is used as the output data signal d2 as the second data signal.
Output to shift output selection circuit 3B. This output data signal
d2 is output to the data output terminal D _O through the second shift output selection circuit 3B which selects the first shift output selection circuit 3A side by a mode signal m.

When the device 1A as shown in FIG. 1 is configured as an LSI, one shift path is configured by connecting input / output terminals of a plurality of LSIs to each other, and the same operation as in the above-described case is performed. It becomes possible. This will be described with reference to FIG.

In FIG. 2, M _{1 to} M _K are K LSIs. In LSIM _K of LSIM ₁ ~ last stage of the first stage, the sign of the input and output terminals are common and first FIG. Data input terminal D ₁ is the previous stage of the LSI
It is connected to the data output terminal D _O, the clock signal input terminal
CK and the mode input terminal M are commonly connected. Thus, a common clock signal and the mode signal are supplied to each LSIM ₁ ~M _K.

 Next, the operation will be described.

First, address information for selecting a shift path is
LSIM ₁ supplies the address register 4 ~M _K. That is, given a mode signal shift path selection mode to the mode input terminal M to select the mode of each LSIM ₁ ~M _K. The selection supplies enter the address information input address signal a1 from the data input terminal D _1, by entering the address shift clock signal c2 from the clock signal input terminal CK, the shift path of the LSIM ₁ ~M _K I do.

Next, the writing and reading operations of the data and supplies the data shift clock signal c1 to the shift path of the LSIM ₁ ~M _K selected in this manner. That is, given a mode signal of the shift paths shift mode to the mode input terminal M to the respective LSIM ₁ ~M _K to the data input mode. Then, supplies input data information by inputting the input data signal d1 from the data input terminal D _1, and inputs the data shift clock signal c1 from the clock signal input terminal CK. As a result, the input data information is written to the selected shift path, and output data information is output from the selected shift path.

[Effect of the Invention] As described above, the shift control system of the present invention shares signal lines used for input / output of a data signal and an address signal in two signals of a data control signal and an address control signal. In addition, by sharing a signal line used for inputting the data shift clock signal and the address shift clock signal, the number of input / output terminals required for shift path control can be reduced as compared with the related art. Therefore, when a device having a plurality of shift paths is configured as an LSI, the number of input / output pins can be reduced as compared with the related art, so that the manufacturing cost of the LSI can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration when a plurality of devices are interconnected in the embodiment, and FIG. FIG. 4 is a block diagram showing a configuration of a device in the system, and FIG. 4 is a block diagram showing a configuration when a plurality of devices are interconnected in a conventional shift path control system. 1A device, 2A first clock switching circuit (first clock switching means), 2B second clock switching circuit (second clock switching means), 3A first shift output selection circuit (second 1 shift output selection means), 3B ...
Second shift output selection circuit (second shift output selection means), 4... Address register, S1 to SN.

Claims (1)

(57) [Claims] 1. A shift path control system for selecting one shift path from a plurality of shift paths, writing data to the shift path, and reading data from the shift path, wherein the address register inputs and holds address information by an address shift clock signal. First clock switching means for selecting a shift path based on address information held by the address register and supplying a data shift clock signal to the selected shift path;
First shift selecting means for selecting and outputting data output from the shift path selected by the first clock switching means based on the address information, and second clock switching means for performing an operation according to a mode of a mode signal And a second shift output selecting means, wherein when the mode signal indicates a mode for selecting a shift path,
An address shift clock signal is supplied to the address register via the second clock switching means, and an output signal of the address register is selected and output from the second shift output selection means, and the mode signal causes the shift path to perform a shift operation. When the mode is indicated, the data shift clock signal is supplied to the first clock switching means via the second clock switching means, and the output signal of the first shift output selection means is selected from the second shift output selection means. A shift path control system characterized in that a shift path is output.