JPH04232700A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the evaluating time of a semiconductor storage device. CONSTITUTION:A checker pattern write circuit 27 which disconnects semiconductor storage elements l-16 from the address lines 17-20 of an X-address decoder 25 and address lines 21-24 of a Y-address decoder 26 and, at the same time, connects checker pattern writing signal lines 30 for writing data (checker pattern) having a grid-like pattern for evaluating semiconductor storage elements to the elements 1-16 are added between the decoders 25 and 26 and the elements 1-16. Therefore, the data having the grid-like pattern for evaluation can be written in the semiconductor storage elements 1-16 in a short time as compared with the conventional example which makes the writing one bit by one bit and the evaluating time of this semiconductor device can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a write circuit for data for evaluating semiconductor memory elements thereof.

0002

2. Description of the Related Art A conventional semiconductor memory device and its evaluation method will be explained using a 16-bit semiconductor memory device shown in FIG. 2 as an example.

As shown in FIG. 2, semiconductor memory elements 1 to 1
6 are connected to the X address data lines 17 to 20 of the X address decoder 25 and the Y address data lines 21 to 24 of the Y address decoder 26, respectively.

The operation of the semiconductor memory device configured as described above will be explained below. First, an addressing signal is sent to the X address data line 17 by the X address decoder 25, an addressing signal is sent to the Y address data line 21 by the Y address decoder 26, and the X address data line 17 and the Y address data line 21 intersect. Semiconductor storage element 1 is addressed. At the same time as addressing, certain information is read or written to the semiconductor memory element 1. Next, the semiconductor memory element 2 is addressed in the same manner as described above, and at the same time as being addressed, certain information is read and written to the semiconductor memory element 2, and in this way, the semiconductor memory elements 1 to 16 are Reading and writing are performed.

[0005] Also, a method for evaluating a semiconductor memory device operating as described above will be explained. When evaluating a semiconductor memory device, for example, semiconductor memory elements 1, 3, 6, 8
, 9, 11, 14, and 16 to form grid pattern data (hereinafter referred to as checker pattern). With this checker pattern, it is possible to check whether erroneous writing or erroneous reading occurs between adjacent semiconductor memory elements.

[0006]

However, in the conventional semiconductor memory device described above, when evaluating semiconductor memory elements 1 to 16, it is necessary to write one bit at a time and read out one bit at a time. There was a problem that the evaluation took a long time.

[0007] The present invention solves the above problems, and
It is an object of the present invention to provide a semiconductor memory device that can shorten evaluation time by adding a circuit that can write a checker pattern for evaluation in a short time to a semiconductor memory element.

[0008]

Means for Solving the Problems In order to solve the above problems, the semiconductor memory device of the present invention has a structure in which the address line of the address decoder and the semiconductor memory element are separated from each other between the address decoder and the semiconductor memory element. The present invention is characterized in that a write circuit is provided that connects a write signal line for writing semiconductor memory element evaluation data to the memory element.

[0009]

[Operation] With the above configuration, evaluation data is written to the semiconductor memory element using a signal output from the circuit that writes semiconductor memory element evaluation data, so compared to when writing was performed one bit at a time in the past, the writing speed is much faster. Saves time and reduces evaluation time.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Note that the same components as those in the conventional example shown in FIG.

The semiconductor memory device of the present invention newly includes address lines 17 to 20 of the X address decoder 25 and the Y address decoder 2 between the X address decoder 25 and the Y address decoder 26 and the semiconductor memory elements 1 to 16.
6 address lines 21 to 24 and semiconductor memory elements 1 to 1
At the same time, a checker pattern writing circuit 27 is added which connects a checker pattern writing signal line 30 for writing a checker pattern, which is semiconductor storage element evaluation data, to the semiconductor storage elements 1 to 16. This checker pattern writing circuit 27 includes an address data line switching signal input terminal 28 that inputs a signal for switching between the address lines 17 to 24 and a checker pattern writing signal line 30, and a checker pattern writing signal input terminal 28 for inputting a signal for switching between the address lines 17 to 24 and a checker pattern writing signal line 30. A checker pattern write signal input terminal 29 is provided to input the checker pattern write signal.

A method for evaluating the semiconductor memory device of this embodiment configured as described above will be explained below. First, a switching signal inputted from the address data line switching signal input terminal 28 drives, for example, a switching element (not shown) to control the address lines 17 to 20 of the X address decoder 25 and the Y address decoder 26.
address lines 21 to 24 and semiconductor memory elements 1 to 16
At the same time, the checker pattern writing signal line 30 is connected to the semiconductor memory elements 1 to 16. next,
Writing is performed in the semiconductor memory elements 1, 3, 6, 8, 9, 11, 14, and 16 by a checker pattern write signal inputted from the checker pattern write signal input terminal 29. The data of the formed lattice pattern, that is, the checker pattern, allows the adjacent semiconductor memory elements 1
It is possible to check whether erroneous writing or erroneous reading occurs between .

As described above, according to this embodiment, by providing the checker pattern writing circuit 27, it is possible to
It is possible to write grid pattern data for evaluation into the semiconductor memory elements 1 to 16 in a shorter time than when writing bit by bit, and it is possible to evaluate the semiconductor memory device in a short time. can.

Note that in this embodiment, the number of semiconductor memory elements is one
Although a 6-bit semiconductor memory device is used, semiconductor memory devices with semiconductor memory elements having other bit numbers may also be used.

[0015]

As described above, according to the present invention, by providing the evaluation data writing circuit, it is possible to write evaluation data to a semiconductor memory element in a shorter time than in the past. A semiconductor memory device can be evaluated in a short time.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1-16 Semiconductor storage elements 17-20 X address data lines 21-24
Y address data line 25 X address decoder 26 Y address decoder

Claims (1)

[Claims] 1. A write signal line for writing semiconductor memory element evaluation data into the semiconductor memory element is connected between an address decoder and a semiconductor memory element at the same time as the address line of the address decoder and the semiconductor memory element are separated. A semiconductor memory device equipped with a write circuit.