JPH05334900A - Test circuit for programmable read only memory - Google Patents

Abstract

PURPOSE:To shorten a test time by writing the data inverted to each other at one time on the adjacent memory cells at the time of testing a E2PROM. CONSTITUTION:This circuit consists of an X address decoder 1 selecting thirty two kinds of word lines X0-X31 out of the least significant bit A0 and five bits A4-A7 and a Y address decoder 2 selecting eight kinds of data lines Y0-Y7 from three bits of the addresses A1-A3. As to writing in a plaid pattern, when the side A is selected first, then the side B is selected second as inversion of A. Consequently, since writing by every one address is used conventionally, it takes a time of 5msec. multiplied by all addresses. In this method, writing twice, A side and B side, is enough, the test time is shortened by 1/128 with 256 words and by 1/1024 with 2048 words.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a programmable reader.
A test circuit for a read-only memory (hereinafter referred to as "E ² PROM"), especially an E ² PROM for reducing the time for writing data to a checkerboard for a data loss test between memory cells Test circuit.

[0002]

^2. Description of the Related Art As test items for a memory cell of a conventional E ² PROM, all bits L (chip erase), all bits H (chip write), random data, Ichimatsu (adjacent to the layout) (H and L are written alternately in the matching memory cells). Since the E ² PROM requires about 5 msec for writing per word, the ratio of the writing time to the test time is very large. Therefore, the writing of random data for shortening the test time is simplified by reducing the number of words, but the writing of checkered pattern is indispensable for checking the bit interference.

In order to write in a checkered pattern, all bits L (erase) must be set, and then H must be written in half of all bits (words), but the address is specified for each word. Was there. Further, for the write check of the inverted data, the same write must be performed on the remaining addresses. Therefore, the time required for writing is 5 msec × word number.

A circuit example of a conventional E ² PROM will be described with reference to FIG. 5. The drain of a normal N-type MOS transistor N ₁₁ is a data selection line Y ₁ , and the gate is an address selection line X ₁ . , The source is connected to the drain of the floating gate transistor (memory transistor) N ₂₁ , the gate is connected to the signal C _G , and the source is connected to the signal C _L. Similarly, N ₁₂
Is connected to Y ₂ and X ₁ , N ₁₃ is connected to Y ₁ and X ₂ , and N ₁₄ is connected to Y ₂ and X ₂ , respectively.
The drains of ₂₂ , N ₂₃ and N ₂₄ are connected. The gates and sources of N _{22 to} N ₂₄ are short-circuited with the gates and sources of N ₂₁ .

In the conventional E ² PROM circuit shown in FIG. 5, a high voltage is applied to C _G and a ground voltage is applied to C _L , and X is applied.
When a positive voltage is applied to _1, Y _1, N ₁₁ conducts and provides a write voltage to N _21, the floating gate of the N ₂₁ - electrons are accumulated in the bets.
This state is defined as "logic level H". On the other hand, signal C
_When a read voltage is applied to _G , N ₂₁ does not conduct. Thus, in normal writing, only 1-bit memory cells are selected.

[0006]

[Problems to be Solved by the Invention] The above-mentioned conventional E ² PRO
In M, usually only one address can be written at a time, so there is a problem in that it takes 5 msec × the number of words to write in the checkered pattern.

Therefore, an object of the present invention is to provide an E ² PROM test circuit that solves the above problems.
In particular, it is an object of the present invention to provide an E ² PROM test circuit capable of reducing the writing time in the test time.

[0008]

The E ² P of the present invention
The ROM test circuit includes an address decoder that selects all memory cells having the same least significant bit of address input and a memory cell block in which memory cells having the same least significant bit of address input are laid out in a checkered pattern. It is characterized in that the mutually inverted data are written at a time to the memory cells adjacent to each other in terms of layout, thereby achieving the above object.

That is, the present invention provides: "An address decoder for converting an n-bit address input to select a desired memory cell, a memory cell for 2 ⁿ words, and a writing for one word. In an electrically erasable E ² PROM with a built-in circuit,
A test circuit for an E ² PROM, which is characterized in that mutually inverted data are written into adjacent memory cells in a layout at a time. Is the gist.

[0010]

EXAMPLES The present invention will be described in more detail with reference to Examples of the present invention. FIG. 1 shows an embodiment of E ^{2 according} to the present invention.
It is a block diagram of a test circuit of a PROM, and for simplification, it shows one bit of an E ² PROM of 2 ⁸ = 256 words.

The address decoder for selecting a desired memory cell is, as shown in FIG. 1, 32 least significant address bits A ₀ and 5 bits from A _{4 to} A ₇ to X _{0 to} X ₃₁ . An X address decoder 1 for selecting a word line and a Y address decoder 2 for selecting eight data lines of Y ₀ to Y ₇ from 3 bits of addresses A _{1 to} A ₃ Composed.
In addition, the TEST1 signal that selects all memory cells and A
_The TEST2 signal, which selects all memory cells equal to _0, is input to the X and Y address decoders 1 and 2.

A write / read circuit 3 is connected to the data line selected by the Y address decoder 2. X address
Decoders X _{0 to} X ₃₁ and Y address decoders Y _{0 to} Y
₇ is normally only 1 output H due to the code of A _{0 to} A _7.
Is output.

Now, when all of A _{0 to} A ₇ are L, X ₀ and Y ₀ output H, and X _{1 to} X ₃₁ and Y ₁ to Y ₇ output L. As a result, the upper left memory cell is selected. The output X ₀ of the X address decoder 1 is connected to the gate of the control transistor N ₁₁ of the memory cell, and the output Y ₀ of the Y address decoder 2 is also connected to the drain of N ₁₁ . Connected.
The source of N ₁₁ is connected to the drain of floating gate transistor N ₂₁ . The gates of the floating gate transistors of all memory cells are connected to signal C _G and the source is connected to signal C _L.

When a high voltage is applied to signal C _G , a ground potential is applied to C _L , and H is applied to X ₀ and Y ₀ , electrons are accumulated in the floating gate of N ₂₁ . This state is defined as "logic level H" and H is written. On the other hand, when a read voltage is applied to C _G , N ₂₁ does not conduct. To delete, TEST
The I signal is set to H, all the memory cells are selected, and a high voltage is applied to C _L to remove the electrons accumulated in the floating gate. This state is defined as "logical level L".

Here, X and Y address decoders 1, 2
The TEST2 terminal is added to. X address decoder 1
When the signal TEST2 is H and A ₀ is L, X ₀ , X ₂ , ...
Outputs H to X ₃₀ , and when TEST2 and A ₀ are H, X ₁ and X
₃ …… Outputs H to X ₃₁ . Y address decoder 2
Outputs H to Y _{0 to} Y ₇ when TEST2 is H.

The top row of memory cells is X from the left in FIG.
₀ , X ₁ , X ₀ , X ₁ , X ₀ , X ₁ , X ₀ , X ₁ connected to 2
Steps from the left are X ₁ , X ₀ , X ₁ , X ₀ , X ₁ , X ₀ , X ₁ , X
₀ , and the third stage is X ₂ , X ₃ , X ₂ , X ₃ , X ₂ ,
Connected to X ₃ , X ₂ , X ₃ , and so on, and the bottom row is from the left, X ₃₁ , X ₃₀ , X ₃₁ , X ₃₀ , X ₃₁ , X ₃₀ , X ₃₁ , X ₃₁ ,
It is connected to the X _{3 0.} Further, the memory cells in the vertical direction are connected to the same data line, and in the case of the leftmost memory cell, Y ₀
Connected to.

Thus, the adjacent memory cells are connected to the output of the address decoder which is inverted with respect to LSBA ₀ of the address signal when the TEST2 signal is H. Therefore, since the address decoder that selects all the memory cells whose LSB of the address input is L and the memory cells whose LSB of the address input is the same are laid out in a checkered state, the decoders which are mutually inverted to the adjacent memory cells are arranged. -Data can be written at once.

(Specific Example of Address Decoder) An example of the above address decoder will be described with reference to FIG. Figure 2
FIG. 3 is a diagram showing a concrete circuit example of an address decoder section. The X address decoder 1 includes 32 5NAND circuits for decoding A ₀ and A _{4 to} A ₇ , and TEST1 + (TEST2
Two AND / NORs of A ₀ ) and TEST1 + (TEST2 ・ A ₀ bar)
Circuit, 5NAND circuit and AND-NOR circuit output is input 3
It consists of two 2NAND circuits. In addition, TEST1 + (TEST
_{2 · A 0), TEST1 +} (TEST2 · A 0 bar - each of the) bar - described omitted (hereinafter the same).

X ₀ , X _2, ... X ₃₀ are TEST1 + (TEST2.
Input A ₀ bar), X ₁ , X ₃ ... X ₃₁ is TEST1 + (T
Enter EST2 · A ₀ ). On the other hand, the Y address decoder 2 includes eight 3NAND circuits for decoding A _{1 to} A ₃ and a TEST.
It is composed of a NOR circuit of 1 + TEST2, 8 NAND circuits which inputs the outputs of 3NAND and 2NOR.

When TEST1 is H, two ANs of X decoder
NOR of D-NOR and Y decoder becomes L, and X _{0 to} X ₃₁ and Y ₀ to
All Y ₇ outputs H, and all memory cells are selected. When TEST2 is H, X address Deco - since one of the two the AND-NOR da 1 outputs an H, an inner an even or odd Deco X ₀ to X ₃₁ - de output 16 to the H output To be done. Since the NOR output of the Y decoder becomes L, all of Y _{0 to} Y ₇ output H. As a result, half of the memory cells (here, 128 addresses out of 256 addresses) can be selected and written simultaneously.

The mask layout pattern for realizing the memory cell shown in FIG. 1 has an address selection line A whose address input LSB is L and an address selection line whose address input LSB is H in one memory cell. There are two of B. This is a pair of X ₀ and X ₁ , X ₂ and X ₃ , and so on X ₃₀ and X ₃₁ . This X address decoder 1, Y address decoder 2 and memory cells A, B make TEST2 H, A
_{When O} is L, the memory cell with the symbol A is selected and T
When EST2 and A _O are H, the memory cell with the symbol B is selected (see FIG. 1). A memory map according to this example is shown in FIG.

By arranging the two address selection lines A and B in the layout pattern, the memory cells can be easily arranged. The gate of an ordinary transistor (N _{11 in} the memory cell at the upper left end) for selecting a memory transistor having a floating gate on the first address selection line A input to the coordinates (X ₁ , Y ₁ ) on the left side is set. Connect and coordinate on the right side (X ₂ ,
Output to Y ₂ ).

Further, the second address selection line B is input from the coordinate (X ₁ , Y ₂ ) on the left side, and from the coordinate (X ₂ , Y ₁ ) on the right side without connecting to the transistor in the cell. Output. By arranging these layout cells in the horizontal direction, the effective address selection lines are in the order of A, B, A, B ....

When the first stage and the second stage are arranged in a mirror-reversed manner in the vertical direction, A is input on the upper side and B is input on the lower side. When arranged in the same direction, if the first stage is A on the upper side and B is on the lower side, B is input on the upper side and A is input on the lower side in the second stage.

(Circuit Example Considering Memory Cell Layout) FIG. 4 is a diagram showing an embodiment of the memory cells arranged in a checkerboard of the E ² PROM of the present invention, which is a circuit considering the memory cell layout. It is a figure which shows an example. Two address selection lines X ₀ and X ₁ and two data selection lines Y ₀ and Y ₁ are input with a 4-bit memory cell as one unit. Further, signals common to all memory cells and C _G and C _L are input.

X ₀ is input to the selection transistors N ₁₁ and N ₁₄ of the upper left and lower right memory cells, and X ₁ is input to the selection transistors N ₁₃ and N ₁₂ of the lower left and upper right memory cells. In this example, two address selection lines are shared by the memory cells of 4 bits, which has the effect of reducing the layout cell size.

[0027]

INDUSTRIAL APPLICABILITY The present invention, as described above in detail, has a characteristic of E ² P
Providing a test circuit for writing mutually inverted data to adjacent memory cells in the ROM layout at one time has the effect of reducing the write time in the test time. In the present invention, in the checkered writing, when the A side is selected at the first time, the B side is selected as the inversion at the second time. Therefore, in the prior art, since one address was written at a time, it took a time of all addresses x 5 msec, but in the present invention, it is only required to be performed twice for the A side and the B side.
It can be shortened to 1/128 in the case of 2048 words and 1/1024 in the case of 2048 words.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit example of an address decoder unit.

FIG. 3 is a diagram showing a memory map.

FIG. 4 is a diagram showing an example of a circuit in consideration of a layout of memory cells.

FIG. 5 is a diagram showing a circuit example of a conventional E ² PROM.

[Explanation of symbols]

1 X Address Decoder 2 Y Address Decoder 3 Write / Read Circuit N _{11 to} N ₁₄ N-type MOS Transistor N _{21 to} N ₂₄ Floating Gate Transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 27/10 491 8728-4M

Claims (6)

[Claims] 1. An electric circuit having an address decoder for converting an n-bit address input to select a desired memory cell, a memory cell of 2 ⁿ words and a writing circuit for 1 word. Erasable programmable read-only memory, in which mutually inverted data are written at once to adjacent memory cells in layout, the programmable read-only memory Test circuit. 2. The address decoder has a function of selecting all memory cells whose LSB of address input is L and a function of selecting all memory cells whose LSB of address input is H. 2. The memory cells having the same LSB are laid out in a checkered pattern.
A programmable read only memory test circuit as described. 3. The memory cell includes, in a layout block, an address selection line A having an LSB of L for address input and an address selection line B having an LSB of H for address input. A programmable read only memory test circuit as described. 4. A gate of a transistor for selecting a memory transistor having a floating gate on a first address selection line input to the coordinates (X ₁ , Y ₁ ) on the left side of a layout block. , And coordinate on the right side (X ₂ ,
Y ₂ ), and the second address selection line is input from the left side coordinates (X ₁ , Y ₂ ), and the right side coordinates (X ₂ , Y ₁ ) without connecting to the transistor in the cell. 4. The test circuit for the programmable read-only memory according to claim 3, wherein 5. In a layout block in which the memory cells are copied vertically and horizontally, the same two address selection lines are input to the first and second stages, and the memory cells at the left end of the first stage are 4. A test circuit for a programmable read-only memory according to claim 3, wherein, when connected to the address select line A, the memory cell at the left end of the second stage is connected to the address select line B. .. 6. The memory cell is composed of 4 bits each consisting of 2 bits vertically and horizontally, and an address selection line A is connected to the upper left and lower right memory cells, and an address selection line B is connected to the lower left and upper right. The programmable device according to claim 3.
Read-only memory test circuit.