JP3130598B2 - PROM writing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PORM write circuit, and more particularly to a PROM write circuit capable of writing a checkerboard pattern having a different logic of [0, 1] into adjacent PROM cells during a test.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional PROM writing circuit connects a single digit line 7 to all PROM cells 6 adjacent in the digit direction by the number of word lines 5 to form a PROM cell array. Is configured.

The word line 5 is connected to the X decoder 2,
The selector 4 is connected to the Y decoder 1 and the write circuit 3,
PR where digit line 7 and word line 5 cross
The OM cell 6 is arranged. Here, only some word lines and digit lines are shown.

The operation of FIG. 2 will be described.

Signals Y1 to Yn (n is the number of selectors) address-decoded by Y decoder 1 and X decoder 2
Can be written to an arbitrary PROM cell 6 by changing the address according to the signals X1 to Xm (m is the number of word lines) decoded by the address in the above manner. The PROM cell 6 is selected and written so as to have a checkered pattern or an inverted checkered pattern.

[0006]

SUMMARY OF THE INVENTION Such a conventional PR
The OM write circuit uses a P
Due to the increase in the capacity of the digit line 7 in the PROM space,
This has the effect of lowering the M writing characteristics. In the PROM writing test by the LSI tester, the PROM is written in a checkered pattern or an inverted checkered pattern.
Since it is necessary to set an address for selecting the cell 7, there is a problem that it is not easy to create a test program and the test time is long.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a PROM writing circuit that can easily create a test program without lowering ROM writing characteristics.

[0008]

The structure of a PROM writing circuit according to the present invention has two digit lines for PROM cells arranged in the same column, and the adjacent PROM cells have the two digit lines. In a PROM writing circuit having a PROM cell array configured to be connected alternately with a line, a means for switching between the two digit lines is provided by a write test signal input from the outside during a PROM write test, and the write cells are checked. It is characterized in that a pattern or an inverted checkered pattern can be selected.

[0009]

FIG. 1 is a circuit diagram showing a PROM writing circuit according to one embodiment of the present invention. In FIG. 1, two digit lines 7 are prepared according to the present invention. That is, there is a digit line 7 for each PROM cell 6. Between the Y decoder 1 and the Y selector 4, NAND gates 15 to 18 and inverters 19 to 22 are interposed. Further, the MLTWR signal, CH
The ECK signal is input to the inverter 10 and the NAND gates 15 to 18 which receive the ECK signal. The rest is almost the same as FIG.

In this embodiment, PROMs arranged in the same column are used.
The cell 6 has two digit lines 7 each, and the adjacent PROM cells 6 constitute a PROM cell array so as to be alternately connected to the two digit lines.
A signal whose address has been decoded by the X decoder 2 is input to the gate of the M cell 6, and the gates of the control transistors A and B in the Y selector 4 for switching the two digit lines 7 are externally input. The write test signal and the signal whose address has been decoded by the Y decoder 1 are decoded and input.

Next, the operation of this embodiment will be described.

When a write test signal (hereinafter simply referred to as a test signal) MLTWR signal inputted from the outside is at "L" level, the state of a checkerboard write signal (hereinafter referred to as a checker write signal) CHECK signal is maintained. Not
Signals X1 to Xm (m is the number of word lines) whose addresses are decoded by the X decoder 2 (hereinafter, simply referred to as X decoder signals), and signals decoded by the Y decoder 1 (hereinafter, simply referred to as Y decoders) According to Y1 to Yn (n is the number of selectors), a control transistor for switching two digit lines (hereinafter simply referred to as a control transistor)
Since both A and B are ON, writing to any PROM cell 6 is possible by changing the address.

On the other hand, when the test signal (MLTWR signal) is at "H" level, first, the checker write signal (CH
When the ECK signal is at “H” level, the Y decoder signal Y
1 to Yn, only the transistor A among the control transistors A and B is turned on, and the X decoder signals X1 to X
The PROM cell 6 is selected by m, and a checkerboard pattern can be written by changing the address.

The checker write signal (CHECK)
Signal) is at "L" level, the Y decoder signals Y1 to Y
By n, only the transistor B of the control transistors A and B is turned on, the PROM cell 6 is selected by the X decoder signals X1 to Xm, and the inverted checkerboard pattern can be written by changing the address.

[0015]

As described above, the present invention has two digit lines for PROM cells arranged in the same column, and adjacent PROM cells alternate with the two digit lines. By providing a PROM cell array configured to be connected, the capacitance of the digit line is divided into two, so that the PROM writing characteristics can be improved, and
Since the PROM cell selected at the time of the ROM write test is a PROM cell having a checkerboard pattern or an inverted checkerboard pattern, it is particularly easy to create a test program in a PROM write test using an LSI tester, thereby shortening the test time. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a PROM writing circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional PROM writing circuit.

[Explanation of symbols]

MLTWR PROM write test signal CHECK Checkered pattern write signal Y1 to Yn Signal decoded at address by Y decoder X1 to Xm Signal decoded attress by X decoder A, B Control transistor for switching two digit lines VPP PROM write potential Reference Signs List 1 Y decoder 2 X decoder 3 Write circuit 4 Y selector 5 Word line 6 PROM cell 7 Digit line 10, 19 to 22 Inverter 11 to 14, 15 to 18 NAND gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 29/00

Claims (2)

(57) [Claims] 1. A PROM cell array comprising two digit lines for PROM cells arranged in the same column, and adjacent PROM cells being connected alternately to the two digit lines. Means for switching between the two digit lines by a write test signal input from the outside during a PROM write test, so that a write cell can be selected between a checkered pattern and an inverted checkered pattern. Characteristic PROM
Write circuit. 2. The P switch according to claim 1, wherein said switching means comprises a combination of a plurality of inverters and a plurality of NAND gates.
ROM writing circuit.