JPS59113600A - Highly reliable storage circuit device - Google Patents

Abstract

PURPOSE:To reduce bit defect to attain a highly reliable integrated circuit device by allowing plural storage cells to correspond to one address and providing a majority circuit. CONSTITUTION:A stored data is determined by an intersection selected by decoder line 5 and selector line 8. Only one of decoder lines 5 and only one of selector lines 8 are always selected. In Fig., three storage cells are always selected. In case of the read, three storage cells are compared with one another by decoder line 5, selector line 8 and the majority circuit 10 selected by selector lines 8 to determine always a majority data. In case of the write, the same data is written on the three storage cells coincidently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly reliable memory circuit device, and particularly to a data writing,
The present invention relates to an integrated circuit device that aims to reduce read errors and eliminate 1-bit defects to improve yield.

Conventional integrated circuit devices including this type of memory device include random access memory, programmable read-only memory, and the like. What these all have in common is that, as shown in Figure 1, one memory element 2 or one memory circuit corresponds to one address selected by the decoder 2-in-1 and selector line 3. When something exists, it has no place as a storage device. In addition, bit failures occur even in the case of accidental accidents such as radiation, although improvements are being made. In this way, a device in which one memory element or one memory circuit corresponds to one address has a weak reliability.

The present invention eliminates the above drawbacks by associating a plurality of memory elements or memory circuits with one address and passing a plurality of results for one address through a majority decision circuit, and provides an integrated system suitable for improving reliability. The purpose is to provide circuits.

According to the present invention, an integrated circuit device is obtained in which a plurality of memory cells are associated with one address and the output thereof is passed through a majority circuit.

Next, embodiments of the present invention will be described using the drawings. FIG. 2 shows one embodiment. The stored data is determined from the intersection selected by the decoder line 5 and the selector line 8. Here, one decoder line and one selector line are always selected. According to FIG. 2, three memory cells are always used. In the case of reading, the decoder line 15, the selector line 8, and the majority circuit 10 selected by the selector line 8 compare the three memory cells and always determine a large number of data. In the case of writing, the same thing is written to three memory cells at the same time, as described above.

According to the present invention, as described above, by associating a plurality of memory cells with one address and providing a majority circuit, defects in bits, bits, and defects can be reduced, and a highly reliable integrated circuit device can be obtained. The explanation above has been made assuming that the base number for majority voting is 3.

[Brief explanation of drawings]

FIG. 1 is a partial physical diagram of a conventional storage device, and FIG. 2 is a circuit diagram showing a partial block diagram of an embodiment of the present invention. In the figure, 1, 5...decoder line, 2.6...memory cell, 3, 8...selector line, 4.11...input/output Karain,
7...Bit 1.9...Input/output control signal, 10...Majority circuit, 12...Majority circuit selection signal, 13.14... ...Switch 1
5.16...Sense amplifier. h l Figure name 2 Figure

Claims (1)

[Claims] 1. A highly reliable integrated circuit device including memory cells, having a plurality of memory cells at one address, and comprising a majority circuit in a reading circuit for the tC+ cells.