JPS6233625B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device that multiplexes memory cell arrays and compensates for errors occurring in the memory cell arrays.

[Prior art]

In the field of semiconductor integrated circuits, there has been remarkable progress in increasing the degree of integration through miniaturization. As semiconductor memory devices become smaller, the probability of occurrence of minute defects that cause erroneous bits increases, and problems such as a decrease in device manufacturing yield and a decrease in device reliability become significant.

Conventionally, various methods have been known to compensate for error bits by multiplexing memory elements or memory cell arrays containing such defects (error bits).

(1) Effective use of defective elements is achieved by collecting multiple memory elements with different error bit addresses, writing the same information to each memory element, and extracting and outputting the correct data from the read data. Method.

(2) A method of increasing the reliability of storage devices by storing the same information in multiple memory elements that operate normally, and taking advantage of the low probability that the information stored at the same address in each memory element will be an error bit at the same time. .

(3) One memory element has multiple memory cell arrays that store the same information and a logic circuit that receives the output of each memory cell array as input and extracts only the correct information. A method of improving the yield of memory elements by taking advantage of the low probability that information stored at the same address in a memory cell array will become error bits at the same time.

FIG. 1 shows a storage device that uses conventional multiplexing to compensate for erroneous bits. The storage device in Figure 1 is
Duplicated N×M bit memory cell array 1,
2, N-bit row decoder circuits (including word drivers) 3 and 4 and M-bit column decoder circuits (including sense up) 5 and 6, which select memory cells in each memory cell array, and memory cell arrays 1 and 2. It consists of a logic circuit 7 which receives the output of , and outputs only correct information. The address from the outside is given to the address input terminal 8, and the address is given to the output terminal 9.
The storage device output is output from. Here, the order of the row addresses added to the row decoder circuits 3 and 4 and the order of the column addresses added to the column decoder circuits 5 and 6 are the same between the duplicated memory cell arrays. Address input terminal 8
When an address is given to 2, row decoder circuits 3 and 4 and column decoder circuits 5 and 6
Memory cells at the same position on two memory cell arrays 1 and 2 are selected, and column decoder circuits 5 and 2 are selected, respectively.
The data is read out to the logic circuit 7 via 66. The logic circuit 7 outputs correct information from the information read from the two memory cell arrays. There are various methods for outputting correct information. For example, if a defective memory cell is known in advance, the address of the memory cell is registered in an associative memory or the like, thereby selecting and outputting the output from the memory cell array of non-defective memory cells. In addition, if the memory cell array has characteristics such that defects are fixed at “0”, 2
By simply ORing the outputs of the two memory cell arrays and outputting the result, correct information can be output.

On the other hand, when looking at the defects that occur on the memory cell array, most of the defects are local defects such as short circuits and disconnections in word lines and bit lines. These defects cause bits along the word lines and bit lines to become errors, but the probability of an error bit occurring is different between a portion near the decoder circuit (near end) and a portion far away (far end). For example, in the case of a disconnection, the bits at the far end of the disconnection point will have an error, but the bits at the near end will operate normally. Even if the disconnection points exist randomly over the entire array, the bits at the ends farther from the disconnection points will be in error, so the probability of an error bit increasing at the farther end. Furthermore, even in the case of a short circuit, if the wiring resistance is large, the near end often operates normally. Furthermore, even if there is no disconnection or short circuit, the signal waveform at the far end tends to become dull due to the influence of the wiring time constant, and even slight noise or timing deviation can cause errors. As described above, depending on the connection positional relationship between the decoder circuit and the memory cell array, memory cells where error bits are likely to occur tend to be unevenly distributed at the far end.

Shaded areas 10 and 11 in FIG. 1 are simulated areas of memory cells where error bits are likely to occur along bit lines and word lines, respectively, and 12 is an equivalent memory cell array obtained as the output of the memory device. be. As is clear from the figure, when the memory cell array and decoder circuit of the same configuration are used for duplication, the areas where error bits are unevenly distributed overlap, increasing the probability of an error in information stored at a specific address. Therefore, there is a problem in that the effects of increasing yield and reliability resulting from duplication of the memory cell array are not fully exhibited.

[Purpose of the invention]

An object of the present invention is to further reduce the error probability in a memory device that compensates for error bits by multiplexing memory cell arrays.

[Summary of the invention]

The present invention prevents areas where error bits are unevenly distributed from overlapping by making the selected storage cell positions on each storage cell array different for addresses given from the outside.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the invention. The storage device shown in FIG. 2 is a storage device with a duplicated storage cell array, and includes two N×M-bit storage cell arrays 21 and 22, and an N-bit row for selecting a storage cell in each storage cell array. Decoder circuits (including word drivers) 23, 24 and M-bit column decoder circuits (including sense amplifiers) 25,
26, and a logic circuit 27 which receives the outputs of the memory cell arrays 21 and 22 and outputs only correct information. An address from the outside is applied to an address input terminal 28, and a storage device output is outputted from an output terminal 29. Shaded areas 30 and 31 are simulated areas where error bits are likely to occur along bit lines and word lines, respectively, and 32 is an equivalent memory cell array obtained as the output of the memory device. Further, the numbers in the row decoder circuit and column decoder circuit are a row address and column address, respectively, and the matrix elements in the memory cell array represent the address of each memory cell.

The feature of this embodiment is that the row decoder circuits 23, 2
The address ordering of the word lines, which are the outputs of the column decoder circuits 25 and 26, and the address ordering of the bit lines, which are the inputs of the column decoder circuits 25 and 26, are configured to be reversed between the duplicated memory cell arrays 21 and 22. It is that you are. As a result, the positions of memory cells with the same address in memory cell arrays 21 and 22 with respect to the decoder differ between each memory cell array.

As mentioned above, error bits along the bit line and word line are located at the far ends 30 and 31 when viewed from the decoder circuit.
However, the memory cells in the unevenly distributed areas have generally different addresses between the duplicated memory cell arrays. That is, an address located in an area where errors are likely to occur in one memory cell array exists in an area where errors are unlikely to occur in the other memory cell array. For example, if "1M" is given as the address, in the conventional example shown in Figure 1, the address "1M"
The storage cells in both arrays 10 and 11 are located in the same area in the upper right corner of the figure with a high error probability, whereas according to the embodiment of the present invention shown in FIG. The cell position is in the upper right corner of the drawing, in an area with high error probability.
In the memory cell array 22, the memory cell with the address "1M" is located in the lower left area of the drawing with a low error probability. By changing the address order between the two sets of decoders in this way, the area where error bits are likely to occur on the equivalent memory cell array 32 after duplication can be made much smaller than in the past.

Furthermore, by tripling the memory cell array, it is possible to completely eliminate duplication of unevenly distributed error bits. FIG. 3 shows an embodiment of a triplexed memory cell array, in which a third memory cell array 33, a row decoder circuit 34, and a column decoder circuit 35 are added to the embodiment of FIG. The address ordering of the row decoder circuit 34 and column decoder circuit 35 is different from that of other row decoder circuits 23,
24 and other column decoder circuits 25 and 26. Therefore, the addresses of memory cells in areas where error bits are unevenly distributed are generally different between memory cell arrays, and the equivalent memory cell array 3 after triplexing is
6, it is possible to prevent areas where error bits are likely to occur from overlapping.

The above is a case where the locations of memory cells having the same address and storing the same information are changed for each memory cell array by changing the row decoder circuit and column decoder circuit.

FIG. 4 explains how the same information can be stored in memory cells with different addresses. 41 and 42 are N×M
Bit duplex storage cell array, 43,4
4 is the same N-bit row decoder circuit, 45,
46 is the same M-bit column decoder circuit;
7 is a logic circuit which receives the outputs of the memory cell arrays 41 and 42 and outputs only correct information; 48 is an address input terminal; and 49 is an output terminal of the memory device. In this embodiment, each decoder circuit and the connection relationship between the memory cell array and the decoder circuit are exactly the same in both memory cell arrays. Therefore, the relative positions of the memory cells having the same address and the decoder circuits are also the same in both memory cell arrays, as in the conventional example shown in FIG. The feature of this embodiment is that the input address signal of one of the decoder circuits is changed using a conversion circuit 50. When an inversion circuit is used as a conversion circuit as shown in FIG.
Information stored at one address (X, Y) will be stored at (,) in the memory cell array 42. Since the writing cell at address (X, Y) and the storage cell at address (,) are located far from and close to the decoder circuit, respectively, the probability that both storage cells are simultaneously in the area where error bits are unevenly distributed is extremely small. Reference numeral 51 designates an equivalent memory cell array after duplication, and as in the embodiment shown in FIG. 2, the overlap of error bit maldistribution regions can be made much smaller than in the prior art. Note that this configuration can be easily extended to triplex as described above.

In the above description, the address order within the memory cell array was continuous. On the other hand, the present invention works more effectively on a memory cell array in which a memory cell array is divided into a plurality of sub-memory cell arrays and each sub-memory cell array is arbitrarily arranged. FIG. 5 shows an embodiment in which the memory cell array is divided into 16 sub-memory cell arrays. By changing the arrangement of the sub-memory cell arrays of the memory cell arrays 60 and 61 as shown in the figure, the error maldistribution area shown in the shaded area can be reduced to 2.
It is possible to prevent duplication on the equivalent memory cell array 62 after duplication.

According to these embodiments, it is possible to significantly reduce the probability that the same information stored in each memory cell array will result in an error, and furthermore, the following effects can be obtained.

(1) A method that has memory cell arrays multiplexed on the same semiconductor chip and ensures manufacturing yield by compensating for error bits caused by minute defects.
Further improvement in yield can be achieved.

(2) In the case where a number of defective memory elements are used and the good parts of the memory cell array are combined to have the function of one memory element and the defective elements are to be used effectively, the present invention is particularly shown in FIG. This method allows for even more effective utilization.

(3) In a method of compensating for errors by multiplexing memory elements or memory cell arrays in order to increase the reliability of a storage device, the present invention reduces the rate of errors in the same information at the same time, further increasing reliability. can be achieved.

In the above description, it has been assumed that errors are unevenly distributed at the far end, but the present invention is not limited thereto, and it is clear that a multiplexed storage device to which the present invention is applied can be constructed even if the error unevenly distributed region is located anywhere. Further, if a plurality of memory cell arrays are provided, the effects of the present invention are the same whether they are on the same semiconductor chip or separated into individual memory elements.

〔Effect of the invention〕

According to the present invention, it is possible to prevent the same information from being stored in areas where error bits are likely to occur in response to maldistributed error bits that frequently occur in each memory cell array. The probability that the same stored information will result in an error can be greatly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIGS. 2 to 5 are block diagrams showing an embodiment of the present invention. 21, 22, 33, 41, 42, 60, 61...
...Storage cell array, 23, 24, 34, 43, 4
4...Row decoder circuit, 25, 26, 35, 4
5, 46... Column decoder circuit, 27, 47...
...Logic circuit.

Claims (1)

[Claims] 1. A plurality of memory cell arrays that store the same information, and a plurality of decoder circuits that are provided corresponding to each of the plurality of memory cell arrays and select a memory cell in each memory cell array according to an address given from the outside. In a memory device comprising a logic circuit that outputs correct information from among the information read from the plurality of memory cell arrays, the memory cell arrays selected by each of the decoder circuits in response to the same address given from the outside. A memory device characterized in that the upper memory cell positions are different between each memory cell array.