JPH05128895A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the test of the defective rate and the hold characteristic of a memory cell by providing a gate switching the selective mode and the non-selective mode of an error correction circuit and an error correction circuit selecting signal. CONSTITUTION:Input data D0-D3 are written in an information bit cell array 3 and the error correction codes C0-C3 of an error correction code generating circuit 1 are written in an inspection bit cell array 4 in accordance with respective addresses specified by an address decoder 5. When the data is read, the data of the array 3 and the data of the array 4 specified by the decoder 5 are read and inputted to the error correction circuit 6. At this time, when the error correction circuit selecting signal 8 is an ''H-level, the circuit 6 becomes a selective condition and error corrected data D00-D03' are outputted. When the signal 8 is an 'L' level, the circuit 6 becomes a non-selective condition and the data of the array 3 is outputted as it is by syndrome decode gates 9-12. Thus, the defective rate and the hold characteristic of the memory cell are tested easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device incorporating an error correction circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional semiconductor device having an error correction circuit and a PROM (Programmable Read Only Memory) as a storage device.

In FIG. 2, the input data D0 to D3 are
The data input to the error correction code generation circuit 1 as it is, the data as it is, is stored in the information bit cell array 3 in the PROM circuit 2, and the generated error correction code is stored in the check bit cell array 4 at the address designated by the address decoder 5. Written in.

When reading the written data,
The data of the information bit cell array 3 designated by the address decoder 5 and the error correction code data of the check bit cell array 4 are input to the error correction circuit 6, and error-corrected data D0 'to D3' are output.

[0005]

In the PROM circuit 2 having such an error correction circuit 6, the PROM memory is affected by the error correction circuit 6 when testing the failure rate of the PROM memory cell or the data retention characteristic. There is a problem that the characteristic evaluation of the cell alone cannot be performed correctly.

The object of the present invention is to solve the above problems and to
It is an object of the present invention to provide a semiconductor device capable of accurately evaluating the characteristics of a ROM memory cell alone.

[0007]

According to the present invention, a memory device and an error correction circuit having an address decoder for selecting a desired memory cell from a plurality of memory cells arranged in a matrix based on an external address signal. And a circuit for obtaining a switching signal when the switching is performed, and a gate for switching the output of the storage device and the output of the error correction circuit.

[0008]

1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, this embodiment has an error correction code generation circuit 1, a PROM circuit 2, and an address decoder 5.
And an error correction circuit 6.

Here, the error correction code generation circuit 1 has four OR gates 30 which receive three input data of the input data D0 to D3 and output the error correction codes C0 to C3.

The error correction circuit 6 outputs the output data DO0-D.
Out of O3, four OR gates 40 each having three output data as inputs and the output of the check bit cell array 4 as well, four OR gates 50 outputting error-corrected data DO0 'to DO3', and a syndrome Decode gate 9-
12, a NAND gate 60, a NOR gate 61,
AND gate 62.

In FIG. 1, the error correction circuit 6 of the present embodiment.
Input data D0 to D3 are input to the error correction code generation circuit 1 in the PROM circuit 2 having a built-in.

The input data D0 to D3 as they are are stored in the information bit cell array 3 in the PROM circuit 2 and the error correction code C generated in the error correction code generation circuit 1.
0 to C3 are written in the addresses designated by the address decoder 5 with respect to the check bit cell array 4.

Next, when reading the written data, the data of the information bit cell array 3 and the error correction code data of the check bit cell array 4 designated by the address decoder 5 are read and input to the error correction circuit 6. .

Here, the error correction circuit selection signal 8 is "H".
If it is a level, the error correction circuit 6 is in a selected state, and the error-corrected circuit 6 outputs data DO0'-D in which an error is corrected.
O3 'is output.

Next, the error correction circuit selection signal 8 is "L".
If it is at the level, the error correction circuit 6 is in a non-selected state, the outputs of the syndrome decode gates 9 to 12 are "L" level outputs, and the information bit cell array output data DO0 to DO0.
DO3 is output as it is as DO0 'to DO3'.

The error detection signal 7 is output if any bit has an error regardless of whether the error correction circuit 6 is selected or not.

As described above, the semiconductor device of this embodiment has the gates 9 to 12 and the switching signal 8 for switching the selection mode and the non-selection mode of the error correction circuit 6.

[0019]

As described above, since the present invention has the switching gate for selecting and non-selecting the error correction circuit,
Raw output data DO0 to DO3 of the information bit cell array
It becomes possible to read out, and even when testing the bit failure rate of memory cells and data retention characteristics, it is possible to evaluate without being affected by the error correction circuit, and when the error correction code generation circuit is external If the user does not request a high level guarantee for data soft errors, etc.
If data is written only to the information bit cell array with an M writer or the like and the error correction circuit is not selected, there is also an effect that the time and effort for writing to the check bit cell array can be saved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor device of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

 D0 to D3 Input data DO0 to DO3 Information bit cell array output data DO0 'to DO3' Error correction circuit output data C0 to C3 Error correction code 1 Error correction code generation circuit 2 PROM circuit 3 Information bit cell array 4 Check bit cell array 5 Address decoder 6 Error correction circuit 7 Error detector signal 8 Error correction circuit selection signal 9-12 Syndrome decode gate A0-An Address input 30, 40, 50 OR gate 60 NAND gate 61 NOR gate 62 AND gate

Claims (1)

[Claims] 1. A semiconductor device including a memory device having an address decoder for selecting a desired memory cell from a plurality of memory cells arranged in a matrix based on an external address signal, and an error correction circuit. A semiconductor device comprising: a gate that switches between an output of the device and an output of the error correction circuit; and a circuit that obtains a switching signal when the switching is performed.