JPS6243407Y2 - - Google Patents

Description

[Detailed Description of the Invention] <<Field of the Invention>> This invention relates to an input device that serves as an interface between a central processing unit of a programmable controller and an external input signal source.

<<Background of the invention>> Conventional input devices for programmable controllers have a configuration in which one external input signal source (limit switch, photoelectric switch, etc.) is connected between each input terminal and a common terminal. Input circuits that binarize input signals and serve as buffers for subsequent circuits are built in, one for each input terminal. Therefore, for example 64
An input device to which 2 input signal sources can be connected has 64 input terminals and usually 8 common terminals, for a total of 72 terminals, and is also internally equipped with 64 input circuits.

In such conventional devices, the terminal board is large and occupies a large area due to the large number of terminals, making it difficult to downsize the device housing. In other words, for devices with a large number of connectable input signal sources, the dimensions of the device housing are determined not by the size of the internal circuitry but by the size of the terminal board, resulting in a very large device. do not have. Furthermore, the number of terminal boards and the number of input circuits greatly affect the device cost, and these have been a major obstacle to cost reduction.

<<Purpose of the invention>> This invention was devised in view of the conventional problems mentioned above.The purpose of this invention is to be able to connect far more input signal sources than the number of terminals, and to reduce the number of terminals compared to the number of connectable points. number and input circuits are small.
An object of the present invention is to provide an input device for a programmable controller that can easily be made smaller and lower in cost.

《Structure and effects of the invention》 In order to achieve the above purpose, this invention
N input terminals and M scanning terminals that are externally connected so that ×M input signal sources constitute a matrix circuit of N rows × M columns, and inputs from the above N × M input signal sources. A memory of 1 word and N bits for storing signals, an address generation circuit that sequentially and cyclically generates an address signal to be applied to this memory, and an address signal that sequentially and cyclically generates an address signal to the M scanning terminals in synchronization with the address generation circuit. a scanning circuit that selectively applies a scanning signal; and a scanning circuit that receives an input signal that is applied to the N input terminals in response to the scanning signal, and receives the input signal as specified by the address generation circuit of the memory. receives a select signal supplied from an input circuit for writing to an address in the programmable controller and a central processing unit side of the programmable controller, and inhibits the address generation circuit, scanning circuit, and input circuit from writing input signals to the memory; At the same time, the present invention is characterized by comprising a write/read switching circuit that reads data from the memory using an address signal supplied from the central processing unit and supplies the read data to the central processing unit.

According to this configuration, a much larger number of N×M external input signal sources can be connected to the N+M terminals. Therefore, compared to conventional devices having the same number of connectable input signal sources, the device of this invention has a much smaller terminal board, and therefore the device housing can be made much smaller. Furthermore, since the number of terminals and input circuits are significantly reduced compared to the conventional method, it is also advantageous in terms of cost.

<<Explanation of the embodiment>> The embodiment shown in the figure has 8+8=16 terminals,
This is an input device to which 8+8=64 input signal sources can be connected. In other words, this input device has eight input terminals IN1 to IN8 and eight scanning terminals T1 to
64 at each intersection of an 8 row x 8 column matrix circuit consisting of 8 input lines connected to input terminals IN1 to IN8 and 8 scanning lines connected to scanning terminals T1 to T8. input signal sources S1 to S64
is connected externally.

In addition, this device has the above 64 input signal sources S1 to
It has a memory 1 of 8 bits per word for temporarily storing the input signal from the S64, and the input signal is transmitted to the data bus DB of the central processing unit (hereinafter referred to as CPU) of the programmable controller via this memory 1. It will be done. As will be described later, when the CPU reads an input signal, the address signal supplied from the address bus AB is input to the memory 1 via the address switching circuit 5, and during other periods,
An address signal generated from the counter 4 is input to the memory 1 via the address switching circuit 5.

The counter 4 sequentially and cyclically generates address signals for scanning the memory 1 by counting clock signals of a predetermined period inputted from the clock generating circuit 2 via the gate circuit 3. The address signal output from counter 4 is sent to decoder 6
is also entered. This decoder 6 is a scanning circuit that scans the externally connected matrix circuit, and by decoding the address signal that changes sequentially and cyclically, it scans the eight scanning terminals T1 to T1.
Scanning signals are sequentially and selectively applied to T8.

When a scanning signal is applied to a certain scanning line, input signals corresponding to the on/off states of the eight input signal sources connected to that scanning line are applied to the input terminals IN1 to IN8. These input signals are waveform-shaped, binarized, and level-converted by an input circuit 7 including circuits for eight points, and are applied to the data input terminal of the memory 1 via a gate circuit 8. This input signal is written to the address specified by the output of the counter 4 in the memory 1.

While the channel selector signal CS from the CPU is not supplied, the gate circuit 3 and gate circuit 8 described above are open, and the address switching circuit 5 is selected to the counter 4 side, so that the The input signal write operation is repeated. In other words, 64 input signal sources S1 to S
64 are repeatedly scanned one by one in sequence, and their input signals are stored in the memory 1 while being repeatedly updated. With this, the latest input signal is always stored in the memory 1.

When the channel select signal CS is supplied from the CPU, the gate circuits 3 and 8 are inhibited, the address switching circuit 5 is selected to the address bus AB side, and the above-mentioned writing operation of the input signal to the memory 1 is stopped. . At the same time, an address signal is sent from the CPU to the address bus B, the advice signal is input to the memory 1 via the switching circuit 5, and the stored data at that address is read from the memory 1 and sent to the data bus DB. In this way, the CPU receives each input signal source S from the input device.
Take in the input signals of 1 to S64.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of an input device for a programmable controller according to this invention. 1...Memory, 4...Counter (main part of address generation circuit), 5...Address switching circuit, 6...
Decoder (scanning circuit), 7...Input circuit, IN1~
IN8...Input terminal, T1-T8...Scanning terminal,
S1 to S64...Input signal source, DB...Data bus, AB...Address bus, CS...Channel select signal.

Claims (1)

[Scope of utility model registration request] N input terminals and M scanning terminals are externally connected so that the N x M input signal sources constitute a matrix circuit of N rows x M columns, and A memory of 1 word and N bits for storing an input signal, an address generation circuit that sequentially and cyclically generates an address signal to be applied to this memory, and a memory that sequentially and cyclically generates an address signal to be applied to the M scanning terminals in synchronization with this address generation circuit. and a scanning circuit that selectively applies a scanning signal; and a scanning circuit that receives an input signal that is applied to the N input terminals in response to the scanning signal, and that input signal is designated by the address generation circuit of the memory. In response to the select signal supplied from the input circuit for writing to the address in the programmable controller and the central processing unit side of the programmable controller, the input signal writing operation to the memory by the address generation circuit, scanning circuit, and input circuit is prohibited. An input device for a programmable controller, comprising: a write/read switching circuit that simultaneously reads data from the memory using an address signal supplied from the central processing unit and supplies the read/write switching circuit to the central processing unit.