JPH0294094A - Data memory - Google Patents

Abstract

PURPOSE:To successively and directly transfer data to an immediately adjacent memory by providing a signal transmission control circuit between memories in longitudinal and lateral directions, and directly transmitting the memory data between the mutual memories. CONSTITUTION:Signal transmission control circuits 16a and 16b are provided in the lateral or longitudinal directions of a memory 11. First, when a clock signal line 18a is controlled to a 'low' condition, the data in the memory 11 on the front stage of a control circuit 16a are transmitted through a memory signal line 17a to a control circuit 16a. Further, the control circuit 16a holds memory contents. Next, when the signal line 18a is controlled to a 'high' condition, the data held by the control circuit 16a are transmitted through the signal line 17a to the memory 11 on the rear stage. In addition, when a clock signal line 17b is controlled, the contents of the memory 11 on an upper side are transmitted through the signal transmission control circuit 16b to the memory 11 on the lower side. By controlling the signal lines 17a and 17b, the data can be directly transferred to the adjacent memory 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The invention relates to a data storage device, and particularly to a two-terminal storage device that can read and write data stored in a memory independently from two terminals of the memory. It is related to.

[Conventional technology]

FIG. 4 shows a data storage device having a conventional two-terminal storage device, in which 11 is a memory having two data input/output terminals and stores data, and 12a is a memory
12b is a memory control circuit for the other terminal, and 13a and 13b are memory control circuits for the memory control circuits 12a and 12b, respectively. access signal lines 14a, 14b for transmitting access control instructions;
are read/write signal lines that transmit read or write instructions to the memory control circuits 12a and 12b, respectively;
15a and 15b are memory control circuits 12a and 12, respectively.
This is a data signal line that transmits data to be written to the memory 11 or data read from the memory 11 via the line B. Note that FIG. 4 shows a data storage device having a total of four two-terminal storage devices, two columns each in the vertical and horizontal directions.

Next, the operation will be explained.

In FIG. 4, the memory control circuit 12a connected to one terminal of the two terminals connected to the memory 11 will be described. The operation of the memory control circuit 12b on the other terminal side is completely similar.

First, the operation of reading data stored in the memory 11 will be described.

Access signal line 13a connected to memory control circuit 12a
In this example, the read/write signal line 14a is controlled as shown in the following table.

Therefore, when reading data stored in the memory 11, control signals are input to the two-terminal storage device so that the access signal line 13a=1 and the read/write signal line 14a=0. It is an object of the present invention to provide a data storage device that can sequentially transfer stored data in the memory of a two-terminal storage device to the memory of a directly adjacent two-terminal storage device in accordance with a control signal from the outside.

[Means to solve the problem]

The data storage device according to the present invention provides a signal transmission control circuit between the memories in the vertical direction and between the memories in the horizontal direction of the two-terminal storage device, and connects the memories and the signal transmission control circuit with a memory signal line, Data stored in the memories is transmitted between the memories based on clock signals and the like.

[Effect]

In this invention, a signal transmission control circuit is provided between the memories in the vertical direction and between the memories in the horizontal direction of the two-terminal storage device, and the memories and the signal transmission control circuit are connected by a memory signal line,
Since the data stored in the memories is transmitted between the memories based on a clock signal or the like, the data is transmitted in synchronization with the clock signal inputted from outside the two-terminal storage device via the clock signal line. The memory control circuit 12a reads data in the memory 11 and outputs it to the data signal line 15a.

Next, the operation of storing data on the data signal line 15a in the memory 11 will be explained.

According to the previous table, control signals are input to the two-terminal storage device as follows.

Access signal line 13a=1 Read/write signal line 14a=1 The memory control circuit 12a writes the data transmitted from the data signal line 15a into the memory 11.

[Problem that the invention attempts to solve]

Conventional data storage devices are configured as described above, so when moving stored data sequentially to an adjacent memory, the stored data must be read from the memory of the two-terminal storage device to the data signal line by read access. After that, the memory of the adjacent two-terminal storage device must be written again by write access, which poses problems such as a long processing time.

In order to solve the above-mentioned problems, the present invention can directly transmit data in a memory to an adjacent memory in sequence.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a data storage device having a two-terminal storage device according to an embodiment of the present invention.
12a is a memory control circuit that controls reading and writing of data in the memory 11 from one terminal of the memory 11;
b is a memory control circuit for another terminal, 13a
, 13b are access signal lines 14 for transmitting access control instructions to the memory control circuits 12a and 12b, respectively.
a and 14b are read/write signal lines for transmitting read or write instructions to the memory control circuit 12a12b, and 15a and 15b are the memory control circuit 12, respectively.
A is a data signal line that transmits data written to the memory IJ11 or data read from the memory 11 via a and 12b, and a is controlled as shown in the following table.

In addition, 16a and 16b are signal transfer control circuits that are provided between the two memories 11 and control the transfer of data in the memories between those memories, and 172.17b is a signal transfer control circuit that is provided between the memory 11 and the signal transfer control circuits 16a and 16b. Memory signal lines 18a and 18b for transmitting data in the memory are clock signal lines for transmitting signal transmission timing to signal transmission control circuits 15a and 16b. In addition, the first
In the figure, the data storage device is shown as having a total of four two-terminal storage devices, two columns each in the vertical and horizontal directions.

Next, the operation will be explained.

In FIG. 1, the operations of the two memory control circuits 12a and 12b connected to the memory 11 are the same as in the conventional device, and the memory control circuit 12a on the side of one of the two terminals is
I will explain about it.

First, the operation of reading data stored in the memory 11 will be explained.

In this example, an access signal line 13a and a read/write signal line 14 connected to the memory control circuit 12a are used. Therefore, when reading data from the memory 11, the following control signals are input to the two-terminal storage device.

Access signal line 13a=1 Read/write signal line 14a=0 The memory control circuit 12a reads data in the memory 11 and outputs the data to the data signal line 15a.

Next, the operation of storing data on the data signal line 15a in the memory 11 will be explained.

According to the above table, the following control signals are input to the two-terminal storage device.

Access signal line 13a=1 Read/write signal! vIl 4 a = 1 The memory control circuit 12a writes the data transmitted from the data signal line 15a into the memory 11.

The other terminal operates similarly via the memory control circuit 12b.

Next, the operation of sequentially transmitting data in the memory 11 to an adjacent memory will be explained.

In FIG. 1, two signal transfer control circuits 16'a and 16b connected to the memory 11 operate in the same way, so only the signal transfer control circuit 16a will be explained here.

In this embodiment, the signal transmission control circuit 16a performs the operations shown in the table below.

First, when the clock signal line 18a is controlled to the 0 (low) state, the data in the memory 11 in the previous stage of the signal transmission control circuit 16a is transferred to the memory signal lines 1, . 7a to the signal transmission control circuit 16a, and this signal transmission control circuit 16a
a holds this memory content according to the table above.

Next, when the clock signal line 18a is controlled to the 1 (high) state, the data in the previous stage memory 11 held by the signal transmission control circuit 16a is transmitted to the subsequent stage memory 11 via the memory signal line 17a. Ru.

As described above, in FIG. 1, when the clock signal line 18a is controlled, the contents of the memory 11 are sequentially transmitted to the memory 11 on the right.

The same applies to the signal transmission control circuit 16b, but in this case, the previous stage and the subsequent stage mean the upper side and the lower side, respectively, and the contents of the memory 11 are sequentially converted into memory signals according to the clock signal line 18b via 9t7b. It is transmitted to the lower memory 11.

In the above embodiment, as shown in FIG. 1, the clock signal line is one vertical and horizontal line of the line 18a for horizontal transmission control and the line 18b for vertical transmission control, and all of the data storage devices are connected to each other. Although the clock signal lines are supplied to the signal transmission control circuits 16a and 16b, there may be a plurality of clock signal lines in the vertical and horizontal directions.

FIG. 2 shows a circuit configuration of a data storage device having two clock signal lines in each direction. In this figure, 21a
, 22a is a clock signal line for lateral transmission control, 21b
, 22b is a clock signal line for longitudinal transmission control;
Other than this, the configuration is the same as that of the first embodiment.

Next, the operation of the memory control circuit in such a configuration will be explained.

The read/write operations for data in the memory 11 from the two terminals are the same as in FIG.
Only data transmission control between 1 and 1 will be explained. Four clock signal lines 21a, 21b, 22a shown in FIG.
, 22b can be controlled independently.

The clock signal line 21a transmits the same control signal as in the example of FIG. 1, but the data transmitted by this control signal is shown in a configuration of four signal transmission control paths in FIG. In this figure, 19a and 19b are data transmission direction control signal lines, and clock signal lines tea,
18b to signal transmission control circuits 36a, 36b, and transfers data in the memory 11 to memory signal lines 17a, 1.
7b to control the direction of transmission. The rest is the same as the first embodiment.

Next, the operation of the memory control circuit in such a configuration will be explained.

The read/write operations for data in the memory 11 from the two terminals are the same as in FIG.
Data transmission control between 1 and 1 will be explained.

In this embodiment, operations are performed as shown in the following table according to the state of the signal line.

Of the seed circuits 16a, only the upper two circuits are connected to the clock signal line 21a.

Similarly, the clock signal line 22a can control:
These are the two signal transmission control circuits 16a in the lower row of FIG.

Furthermore, the vertical signal transmission control circuit 16b can be similarly controlled by the clock signal lines 21b and 22b.

In this embodiment, in addition to the effects of the first embodiment, the transmission of data in the memory 11 can be limited to a limited portion and controlled.

In addition, the above 1. In the second embodiment, FIG.

As shown in FIG. 2, a signal transmission control circuit 16a.

16b is the clock signal line 18a, 18b or 21
A 21b, 22a, and 22b are used for control, but in addition to the black/7 signal lines, a direction control signal line for data transmission may be provided.

FIG. 3 shows the circuit diagram of a data storage device in this embodiment when there is a data transmission direction control signal line in addition to a clock signal line.
The clock signal lines 18a, 18b and the data transmission direction control signal line 19 are connected to the signal transmission control circuits 36a, 36b.
Since signal transmission control circuits 36a and 19b operate in the same way, only one signal transmission control circuit 36a will be explained.

First, when the data transmission direction control signal line 19a=O (low), the operation is the same as that shown in FIG.

Next, when the data transmission direction control signal line 19a=1 (high), the data flow is opposite to that shown in FIG.

That is, when the clock signal line 18a is controlled to the O (low) state, the data in the memory 11 on the right side is transmitted to the signal transmission control circuit 36a on the left side via the memory signal line 17a, and this signal transmission control circuit 36a Maintain this memory content according to the table above.

Next, when the clock signal line 18a is controlled to the 1 (high) state, the data in the right memory 11 held by the signal transmission control circuit 36a is transmitted to the left memory 11 via the memory signal line 17a. Retained.

Further, the signal transmission control circuit 36b operates in the same manner as the circuit 36a in the vertical direction under the control of the clock signal line 18b and the data transmission direction control signal line 19b.

In addition to the effects of the first embodiment, this embodiment has the advantage that data in the memory 11 can be freely transmitted in any direction, left or right or up or down.

〔Effect of the invention〕

As described above, according to the present invention, a signal transmission control circuit is provided between memories in the vertical direction and between memories in the horizontal direction of a two-terminal storage device, and the memories and the signal transmission control circuit are connected by a memory signal line. , the data stored in the memory is directly transmitted between the memories based on clock signals, etc., so 2.
Without reading data in the memory of the terminal storage device to the data signal line, you can quickly and arbitrarily move the data in the other two directions, up, down, left, and right.
It is possible to provide a data storage device that can be moved to the memory of a terminal storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data storage device having a two-terminal storage device according to a first embodiment of the present invention, and FIGS. A diagram showing the configuration of a data storage device according to the third embodiment, and FIG. 4 is a configuration diagram showing an example of a conventional data storage device. 11...Memory, 12a, 12b...Memory control circuit, 13a, 13b...Access signal line, 14a14
b...Read/write signal line, 15a, 15b...Data signal line, 16a, 16b...Signal transmission control circuit, 1
7a, 17b...Memory signal line, 18a, 18b...
- Clock signal lines, 19a, 19b...Data transmission direction control signal lines, 21a, 21b, 22a. 22b... Clock signal line, 36a, 36b... Signal transmission control circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A memory having two terminals for data input/output,
A plurality of two terminals consisting of two memory control circuits that independently control reading and writing of data from each terminal, and an access signal line, a read/write signal line, and a data signal line connected to the memory control circuits. In a data storage device having a storage device, a signal transmission control circuit that is connected to the memory of the two-terminal storage device via a memory signal line and transmits data stored in the memory between the memories based on a transmission control signal is arranged in a vertical direction. A data storage device characterized in that it is provided between memories and between memories in the horizontal direction.