JPH0624908Y2 - Data transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is shared by a plurality of host devices such as a central processing unit, and performs control for data transfer between these host devices and a semiconductor memory device. The present invention relates to a data transfer control device.

Recently, semiconductor memory devices have been used as direct access memory devices in place of the conventional magnetic disk devices, and as a result, the data transfer rate between a higher-level device and these direct access memory devices has dramatically improved. ，
For example, one having a capacity of 3 megabytes / second has come into practical use.

On the other hand, these direct access storage devices are often shared by a plurality of host devices due to, for example, time division. In such a case, the host devices may have different data transfer rates. Not a little
At times, it may include older higher-level devices that have a lower data transfer rate than that of direct access storage devices.

In such a case, regardless of the data transfer capability of the host device, data must be transferred to the direct access storage device without error.

[Conventional technology]

FIG. 2 is an explanatory diagram of a conventional example of a data transfer control device,
1a, 1b, 1c and 1d have a data transfer capacity of 3 megabytes / second, 2.5 megabytes / second, 2 megabytes / second and 1.5 megabytes / second, respectively. The data transfer control device is shared by 1c and 1d, and controls data transfer to and from the direct access storage device 3 described later.

Further, 3 is a direct access storage device (DAS) having a data transfer capacity of 3 megabytes / second, which is composed of a semiconductor storage element.
D).

The data transfer control device 2 is provided with a buffer 21, and all data transfer between the higher-level device 1a, 1b, 1c or 1d and the direct access mechanism device 3 is performed via the buffer 21.

[Problems to be solved by the invention]

As described above, in the conventional data transfer control device, the data transfer between the host device and the direct access storage device is performed via the buffer. For example, in order to reliably perform error control associated with the data transfer, , The data transfer between the host device and the data transfer control device and the data transfer between the data transfer control device and the direct access storage device are not allowed to be performed independently,
Therefore, there is a problem that the control becomes very complicated and the circuit configuration becomes complicated.

[Means for solving problems]

A data transfer control device according to the present invention is provided between a complex host device and a semiconductor disk device, and controls the semiconductor disk device by a command issued from any one of the plurality of host devices. In the data transfer control device that performs the control for performing the data transfer between the higher-level device that issued the command and the semiconductor disk device, set the data transfer rate of each of the plurality of higher-level devices. Setting unit, a selecting unit for selecting the setting unit that sets the data transfer rate of the host device that issued the command, and the semiconductor disk device for the semiconductor disk device according to the data transfer rate set in the set setting unit The problem is solved by providing a clock signal generator for generating the control clock signal.

[Action]

In other words, by using the control clock signal according to the data transfer rate of the host device and making the read and write cycle times of the direct access storage device variable, it is possible to directly communicate with the host device of the old model with a slow data transfer rate. Data can be transferred.

〔Example〕

Next, the gist of the present invention will be specifically described with reference to the embodiment shown in FIG.

FIG. 1 is a block diagram showing the configuration of a data transfer control device according to an embodiment of the present invention. In the figure, 22a, 22b, 22c and 22d are respectively connected to four host devices 1a.
A setting unit or register for setting the data transfer rates of 1b, 1c and 1d.

23a, 23b, 23c, 23d and 24 are four host devices 1a
A selecting unit for selecting one of the data transfer rates of 1b, 1c and 1d is constituted, and 23a, 23b, 23c, 23d and 24 are ANs.
D circuit and 24 are OR circuits.

Next, 25, 26a, 26b, 26c, 26d and 27 form a clock signal generator that generates a control clock signal according to the selected data transfer rate, and 25 is a combiner that combines the output of the OR circuit 24. Yes, 26a, 26b, 26c and 26d are AND circuits, and 27 is an OR circuit.

With the above configuration, the four host devices 1a, 1b,
Selection signals A, B, C generated by either 1c or 1d
Or D to register 22a, 22b, 22c respectively
Or, the set value set in 22d is selected and the OR circuit 2
4 is given to the decoder 25.

The decoder 25 decodes the output of the OR circuit 24 and sends a logical signal "1" to any of the AND circuits 26a, 26b, 26c or 26d depending on the contents of the output.

On the other hand, one of the input terminals of the AND circuits 26a, 26b, 26c and 26d has clock signals CL1 and CL2 of different speeds respectively.
CL3 and CL4 are connected, and any one of them is output from the OR circuit 27 according to the output of the decoder 25.

As a result, the direct access storage device 3 receives the clock signal CL1, CL2, CL3 or CL4 supplied from the OR circuit 24,
Switch read and write cycle times.

[Effect of device]

As described above with reference to the embodiments, according to the present invention, the read and write cycle times of the semiconductor memory device can be switched according to the data transfer capability of the host device. , It is possible to reduce errors in data transfer with a higher-level device whose data transfer rate is lower than that of the direct access storage device.

[Brief description of drawings]

 FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional example. In the figure, 1a, 1b, 1c and 1d are host devices, 3 is a direct access storage device, 22a, 22b, 22c and 22d are transistors, 23b, 23c, 23d and 24 are AND circuits, 24 is an OR circuit, and 25 is a decoder. , 26a, 26b, 26c and 26d are AND circuits, and 27 is an OR circuit.

Claims (1)

[Scope of utility model registration request] 1. A host device which is provided between a plurality of host devices and a semiconductor disk device and which controls the semiconductor disk device by a command issued from any one of the host devices and issues the command. A data transfer control device for controlling data transfer between a semiconductor disk device and a semiconductor disk device, a setting unit for setting a data transfer rate of each of the plurality of host devices, and a data of the host device which issued the command. A selection unit that selects the setting unit that sets the transfer rate, and a clock signal generation unit that generates a control clock signal for the semiconductor disk device according to the data transfer rate set in the set setting unit are provided. A data transfer control device characterized by the above.