JPH0667769A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To perform data transfer between plural devices by adding a small number of circuits. CONSTITUTION:An address selection circuit 9 switches selection switches 10, 11, and 12 corresponding to the address designation signals AD1 or AD2 of an external device, and selects a clock input/output terminal 3 or 6 dedicated for external device, a serial input terminal 4 or 7, and a serial output terminal 5 or 8 provided at each external device to be a transfer object separately, and performs the serial transfer of the data from a shift register 1 to the external device by using a selected input/output terminal, and also, stores the data tranferred in series from the external device in the shift register 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer (hereinafter referred to as a single chip microcomputer).

[0002]

2. Description of the Related Art FIG. 2 shows a conventional single chip microcomputer (hereinafter referred to as a single chip microcomputer).
3 is a diagram showing a schematic configuration of a serial transfer block in FIG. In the figure, 1 is a data bus DB from an internal CPU (not shown)
Transfer data transmitted to the external device via the serial output terminal 5 is serially output to the external device, or transfer data from the external device serially input via the serial input terminal 4 is stored. It is a shift register for storing. The write signal W from the internal CPU is used for writing the transfer data to the shift register 1 and reading the transfer data from the shift register 1 by the internal CPU.
And read signal R respectively.

In the figure, reference numeral 2 indicates an internal clock CLK or an external clock input from a clock input / output terminal 3 based on a write signal W output from an internal CPU and an address designation signal AD of an external device together with a data transfer instruction and transfer data. The clock control circuit selects any one of the above and supplies it to the shift register 1.

Next, the operation of serial input / output will be described. In case of serial output, the output data is the data bus DB
The output data is written to the shift register 1 by being supplied with the addressing signal AD and the write signal W. At the same time, the address designation signal AD and the write signal W are input to the clock control circuit 2, and the clock control circuit 2 receives the internal clock CLK or the external clock input / output terminal 3
The shift register 1 is supplied with one of the external clocks input from. The data stored in the shift register 1 is serially output from the serial output terminal 5 to an external device in synchronization with the clock.

In case of serial input, serial input terminal 4
When the first data for operating the clock control circuit 2 among the transfer data serially input from is written in the shift register 1, the clock control circuit 2 is input from the internal clock CLK or the external clock input / output terminal 3. Supply one of the external clocks to shift register 1.

Further, transfer data serially input from the serial input terminal 4 are stored in the serial register 1 one after another. After completing the data transfer from the external device,
The internal CPU generates an address designation signal AD and a read signal R for the internal memory and reads the data in the shift register 1 via the data bus DB.

[0007]

In the conventional single chip microcomputer as described above, since the input / output terminals used for serial transfer with a plurality of external devices are common to the external devices, a plurality of external devices can be used. Data transfer with a device is performed, for example, by providing a chip select terminal to the external device and giving a chip select signal to the external device to be transferred. Therefore, if the external device to be transferred does not have a chip select terminal, data transfer to this external device cannot be performed.

The present invention has been made in order to solve such a problem, and by performing data transfer using different input / output terminals for each external device to which data is to be transferred, a plurality of external devices can be transferred. The purpose of the present invention is to provide a single-chip microcomputer that can transfer data in a single chip.

[0009]

A single-chip microcomputer according to the present invention is provided with an input / output terminal for data transfer for each external device, and based on specific data unique to the external device attached to the external device to be transferred. , It is characterized by selecting an input / output terminal used for data transfer.

[0010]

When the data transfer command is output, the single-chip microcomputer according to the present invention selects the input / output terminal used for data transfer based on the specific data such as the address of the external device, and selects the selected input / output terminal. Use it to transfer data to and from that external device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a diagram showing a schematic configuration of a serial transfer block of a single-chip microcomputer according to the present invention, which is the same as the conventional single-chip microcomputer shown in FIG.
Alternatively, the corresponding parts will be denoted by the same reference numerals and the description thereof will be omitted. A pair of clock input / output terminals 3 and 6, serial input terminals 4 and 7, and serial output terminals 5 and 8 are provided for each of the two external devices.
By switching between 0, 11, and 12, the input / output terminal corresponding to the external device to be transferred is selected.

The selection switches 10, 11 and 12 are connected to an address selection circuit 9, and the address selection circuit 9 is an address designation signal which is specific data of an external device to be transferred.
The selection switches 10, 11, 12 are switched according to the input of AD1 or AD2.

Next, the serial input / output operation will be described. In case of serial output, the output data is the data bus DB
Output data is written to the shift register 1 by being supplied with the addressing signal AD1 or AD2 and the write signal W. Address selection circuit 9 is switch 10
And 12 are switched to select the clock terminal 3 or 6 and the serial output terminal 5 or 8. At the same time, the address control signal AD1 or AD2 and the write signal W are input to the clock control circuit 2, and the clock control circuit 2 receives the internal clock CL.
Either K or the external clock input from the external clock input / output terminal 3 or 6 is supplied to the shift register 1. The data stored in the shift register 1 is serially output from the serial output terminal 5 or 8 to an external device in synchronization with the clock.

Address input signal AD for serial input
1 or AD2 causes the address selection circuit 9 to switch the switches 10 and 11 to select the clock input / output terminal 3 or 6 and the serial input terminal 4 or 7, and transfer data from the serial input terminal 4 or 7 to the shift register 1. Serial input. After completing the data transfer from the external device,
The CPU generates a read signal R and reads the data in the shift register 1 via the data bus DB.

Although the serial transfer of data has been described in the present embodiment, it can be applied to parallel transfer as long as the input / output terminals have a margin, and the same effect as that of the present embodiment can be obtained.

Further, although the case where the specific data of the external device is an address has been described in the present embodiment, the specific data is not limited to the address, and the specific data may be newly provided for each external device only for terminal selection. .

Further, although the case where the number of external devices is two has been described in this embodiment, the number of external devices to be transferred is not limited to two.

Further, although the case where the data transfer is performed in synchronization with the clock has been described in the present embodiment, the data transfer is not limited to the synchronous type and may be the asynchronous type, and the same effect as that of the present embodiment can be obtained. .

[0019]

As described above, the single-chip microcomputer according to the present invention sets the input / output terminals for data transfer for each external device, and sets the input / output terminals for data transfer according to the external device to be data-transferred. Since the selection is made, an excellent effect that data can be transferred to and from a plurality of external devices can be achieved with a slight increase in circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part configuration of a single-chip microcomputer according to the present invention.

FIG. 2 is a block diagram showing a main part configuration of a conventional single-chip microcomputer.

[Explanation of symbols]

 1 shift register 2 clock control circuit 3,6 clock input / output terminal 4,7 serial input terminal 5,8 serial output terminal 9 address selection circuit 10,11,12 selection switch AD1, AD2 address designation signal CLK internal clock DB data bus R Read signal W Write signal

Claims (1)

[Claims] 1. An input / output terminal for data transfer, which is provided for each external device to which data is to be transferred, and data to and from the external device based on specific data of the external device attached to each external device. A single-chip microcomputer including a circuit for selecting an input / output terminal provided to be used for transfer.