JPH03260728A - Register data writing system - Google Patents

Abstract

PURPOSE:To improve the writing efficiency by providing a memory to temporarily hold the data to be written into each register and transferring the data stored in the memory to those registers at one time. CONSTITUTION:A processor 10 outputs previously the data to a data bus 001 via an address 002 for a register corresponding to the address of a memory 20. Then the processor 10 writes the data to be written in the registers 50 and 60 into the memory 20. When it is required to write data to each register from the processor 10, the processor 10 switches a selector signal 007 to a counter output address 003 and produces an instructions with a data writing instruction signal 006. A counter 30 is counted up by a processor basic clock 004, and the addresses of the memory 20 are successively switched. Then the data to be written into the registers 50 and 60 corresponding to the address 002 are successively outputted from the memory 20. Thus the processor 10 can write data into the registers with high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a register writing method in an information processing device.

[Conventional technology]

2. Description of the Related Art Conventionally, data writing to registers in information processing devices has generally been carried out by a processor writing data to each register one register at a time.

[Problem to be solved by the invention]

In the conventional register data writing method described above, the processor writes to each register one by one, so if there are a large number of registers, the processor is occupied with writing to the registers. On the other hand, when writing the same data, efficiency deteriorates and processing capacity becomes a problem.

[Means to solve the problem]

The register data writing method of the present invention includes a processor,
Multiple registers that can be written to by an external processor, and a memory that temporarily holds data to be written to each external register.
an address counter that switches the address of the memory;
a clock control circuit that controls data writing to the register; a selector that switches an address signal output from the processor and an output of the address counter using a selector switching signal output from the processor; a data bus commonly connected to the memory and each of the registers; a clock signal commonly input to the processor, the counter, and the clock control circuit; an address signal output from the processor; and the processor of the address counter. By having a memory data write clock directed from the processor to the memory, a register write instruction signal directed from the processor to the counter and the clock control circuit, and a register write clock directed from the clock control circuit to the register. is transferred to each of the registers at once.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

10 is a processor, 20 is a memory, 30 is an address counter, 40 is a clock control circuit, 50.60 is a register, 001 is a data bus, 002 is a memory address, 00
3 is the counter output address, 004 is the processor basic clock, 005 is the memory write clock, 006 is the data write instruction signal, 007 is the select signal, 008,00
9 is the data write clock for registers 50 and 60, 01
0 is a control signal including a register selection and register data write clock.

In this embodiment, the processor 10 has two registers 50.
The case where data is written to 60 will be explained, but the same operation will be performed when an arbitrary number of registers are provided.

Normally, when data is written from the processor 10 to the registers 50 and 60, the data to be written is output to the data bus 001, and the register selection signal in the control signal 010 and the data write clock are used to write the data to the register 50 or 60.
Written to 0.

The operation when it becomes necessary to write data from the processor 10 to the registers 50 and 60 at once is as follows. In advance, address 002 and register 5
0.60 is a one-to-one correspondence (in this example, address 0 corresponds to register 50, and address 1 corresponds to register 60).

The processor 10 uses address 002 to output data to the data bus 001 in advance for the register corresponding to the address of the memory 20, and outputs data to the data bus 001 using the memory write clock 0.
05, the data to be written in registers 50 and 60 is written to addresses 0 and 1 of memory 002.

When it becomes necessary for the processor 10 to write data to each register, the processor 10 switches the selector signal 007 to the counter output address 003 side and issues an instruction using the data write instruction signal 006.

The counter 30 is incremented by the basic clock 004, the addresses in the memory 20 are sequentially switched, and the register 5 corresponding to the address 002 from the memory 20 is
The data written to 0.60 is output in order.

Further, data is inputted to the clock control circuit 40 from the data bus 001, and the data has a bit for instructing whether to write to the register or not, and the lock control circuit 40 judges whether the data is written or not.

Then, register write signals 008 and 009 are sequentially written to registers 50 and 60 in synchronization with basic clock 004.

〔Effect of the invention〕

As explained above, the present invention includes a processor, a plurality of registers that can be written to by the processor, a memory that temporarily holds data to be written to each register, an address counter that switches memory addresses, and a register that can write data to the registers. a data bus having a clock control circuit for controlling the processor, a data bus commonly connected to the processor, the memory, and the register; a selector that switches the address signal output from the processor and the output of the address counter using a selector switching signal output from the processor; a memory data write clock from the processor to the memory;
By having a register write instruction signal from the processor to the counter and clock control circuit, and a register write clock from the clock control circuit to the register,
This has the effect that data writing processing from the processor to the register can be performed efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 10...Processor, 20...Memory, 30...Address counter, 40...
・Clock control circuit, 50...Register, 60
...Register, 001...Data bus, 002...Memory address, 003...
... Counter output address, 004 ... Basic clock, 005 ... Memory write clock, 0
06... Data write instruction signal, 007...
... Selector signal, 008 ... Data write clock, 009 ... Data write clock,
OlO... Control signal.

Claims (1)

[Scope of Claims] A processor, a plurality of registers that can be written by the processor, a memory that temporarily holds data to be written to each register, an address counter that switches addresses of the memory, and data for the registers. a clock control circuit that performs write control; a selector that switches an address signal output from the processor and the output of the address counter using a selector switching signal output from the processor; a data bus connected to the processor, a clock signal commonly input to the processor, the counter, and the clock control circuit; an address signal output from the processor; and memory data writing of the address counter from the processor to the memory. clock and
By having a register write instruction signal from the processor to the counter and the clock control circuit, and a register write clock from the clock control circuit to the register, data in the memory is transferred to each register at once. A register data writing method characterized by: