JPH0553906A - Register access system - Google Patents

Abstract

PURPOSE:To shorten time for accessing plural registers from a processor by temporarily holding data to be written in the plural registers in a memory and simultaneously writing these data in the plural registers. CONSTITUTION:This system is equipped with a processor 10, memory 20, address counter 30, clock control circuit 40 and registers 50 and 60. By using a data bus 001 connected to the processor 10, memory 20 and registers 50 and 60, addresses 002 and 003, basic clock 004, memory write clock 005, data write signal 006, select signal 007, data write clock 008 and control signal 010, the data written in the memory 20 are simultaneously written in the registers 50 and 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to a register writing system.

[0002]

2. Description of the Related Art Conventionally, as a method of writing data to a register in an information processing apparatus of this type, a method of writing data from a processor to each register has been generally used.

[0003]

In the above-described conventional register data writing method, the processor sequentially performs writing to each register one by one. Therefore, when the number of registers is large, the processor does not write the registers. It will be occupied, and in processing, when writing the same data to a plurality of registers, the efficiency will be poor and the processing capacity will be a problem.

It is an object of the present invention to provide a register access system which allows a processor to efficiently write data to a register.

[0005]

In order to achieve the above object, in a register access method according to the present invention, in an information processing apparatus having a processor, a plurality of control registers writable by the processor and the respective control registers are provided. A memory for storing data to be written, an address counter for switching an address of the memory, a clock control circuit for controlling data writing to the control register, the processor, the control registers, and the memory are commonly connected. A selector for selecting a data bus, a processor clock signal input to the address counter and the clock control circuit, an address signal output from the processor, and an output of the address counter, and the output of which is an address of the memory. The data stored in the memory The one in which writing to the plurality of registers at once.

[0006]

According to the present invention, data to be written to a plurality of registers is temporarily stored in the memory and these data are written to a plurality of registers at once, so that the processor can efficiently write data to the registers. is there.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the present embodiment, a plurality of control registers 50 and 60 writable by the processor 10 and a memory 20 for storing data to be written in each control register 50 and 60,
Address counter 3 for switching the address of the memory 20
0, a clock control circuit 40 for controlling data writing to the control registers 50 and 60, a data bus 001 commonly connected to the processor 10, the control registers 50 and 60, and the memory 20, an address counter 30, and a clock control circuit 40. It has a selector 70 that selects an input processor clock signal, an address signal output from the processor 10, and an output of the address counter 30, and that output becomes an address of the memory 20.

In FIG. 1, 002 is a memory address,
003 is a counter output address, 004 is a processor basic clock, 005 is a memory write clock, 006 is a data write instruction signal, 007 is a select signal, and 00.
8, 009 is a data write clock for the registers 50, 60, and 010 is a control signal including a register selection and register data write clock.

In this embodiment, the case where the processor 10 writes data to the two registers 50 and 60 will be described. Note that the same operation is performed when the processor 10 has an arbitrary number of registers.

Normally, from the processor 10 to the register 50,
When data is written to 60, the written data is output to the data bus 001 and written to the register 50 or 60 by the register selection signal in the control signal 010 and the data write clock.

When it is necessary to write data from the processor 10 to the registers 50 and 60 at once, the operation is as follows.

Address 002 and register 5
0 and 60 correspond one to one. In this example, the register 50 corresponds to the address 0 and the register 60 corresponds to the address 1.

The processor 10 outputs data to the data bus 001 using the address 002 to the register corresponding to the address of the memory 20 in advance, and the memory write clock 005 causes the address 0 and 1 of the memory 20 to be output.
The data to be written in the registers 50 and 60 is written in the address.

When it is necessary to write data from the processor 10 to each register, the processor 10 issues a select data write instruction signal 006 to the select output signal 007 to the counter output address 003 side.

The counter 30 is incremented by the basic clock 004, the addresses of the memory 20 are sequentially switched, and the data to be written in the registers 50 and 60 corresponding to the address of the address 002 are sequentially output from the memory 20.

Further, data is input to the clock control circuit 40 from the data bus 001, and the data has a bit for instructing whether to write to the register, and the instruction is judged in the clock control circuit 40. ..

The register write signal 008,00
9 synchronizes with the base clock 004 and registers 50 and 6
It will be written to 0 sequentially.

[0020]

As described above, according to the present invention, data to be written in a plurality of registers is temporarily held in a memory, and these data are written in a plurality of registers at once, so that the processor can efficiently write data to the registers. You can do it well.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 10 processor 20 memory 30 address counter 40 clock control circuit 50 register 60 register 70 selector 001 data bus 002 memory address 003 counter output address 004 basic clock 005 memory write clock 006 data write instruction signal 007 select signal 008 data write clock 009 data write clock 010 control signal

Claims (1)

[Claims] 1. An information processing apparatus having a processor, a plurality of control registers writable by the processor, a memory for storing data to be written in each control register, an address counter for switching an address of the memory, and the control. A clock control circuit for controlling data writing to a register, the processor, the control registers, a data bus commonly connected to the memory, a processor clock signal input to the address counter and the clock control circuit, and An address signal output from a processor and an output of the address counter are selected, and the selector has a selector whose output is an address of the memory, and the data written in the memory is written in a plurality of registers at a time. Characteristic register access method.