JPH04243445A - Register data writing system for information processor - Google Patents

Abstract

PURPOSE:To efficiently conduct a same data writing to a plurality of resister from a processor. CONSTITUTION:Plural registers capable of being written from the processor, a memory storing data to be written to the register for each control pattern, a control circuit 30 controlling the address in the memory, and a clock control circuit 40 instructing for writing to each register, are provided. The processor controls the control circuit 30 and the clock control circuit 40 to simultaneously write optional address data in the memory to optional plural registers 50 and 60.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register data writing method for an information processing device.

0002

[Prior Art] Conventional register data writing methods for information processing devices generally write data to one register at a time when a processor writes the same data to multiple registers. there were.

0003

[Problem to be Solved by the Invention] In the register data writing method of the conventional information processing device described above, when a processor writes the same data to multiple registers, writing to each register is performed sequentially one by one. ,
If there are a large number of registers, the processor will be occupied with writing to the registers, and depending on the type of constraint pattern, the same processing may be performed many times, resulting in poor efficiency. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a register data writing method for an information processing device that allows efficient writing of the same data to a plurality of registers.

[0005]

[Means for Solving the Problems] A register data writing method for an information processing device of the present invention is a register data writing method for an information processing device having a processor. A memory that stores data to be written for each control pattern, a control circuit that controls addresses of the memory, and a clock control circuit that instructs each of the registers to write data is provided, and the processor and the memory are connected to each other. a data bus commonly connected to each of the registers and the control circuit; a control signal from the processor to the control circuit; a register selection signal from the control circuit to each register and a clock control signal to the clock control circuit; A register write clock is provided from a clock control circuit to each of the registers, and the same data is simultaneously written to the plurality of registers according to instructions from the processor.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

10 is a processor, 20 is a memory, 30 is a control circuit, 40 is a clock control circuit, 50 is a register A
, 60 is register B, 001 is data bus, 00
2 is memory write clock, 003 is address, 004
is a counter address, 005 is a control signal, 006 is an address, 007 is a clock control signal, 008 is a register selection signal, and 009 is a register write clock.

The memory 20 holds data to be written to the register A50 and the register B60 for each control pattern.

Next, the operation will be explained.

[0011] First, the processor 10 selects address 003.
, 006, and write the data to be written into the memory 20 using the data bus 001 and the memory write clock 002, and write the data to be written into each register for each control pattern.

Next, when the processor 10 writes the same control data to each register during command execution, the control circuit 3
0, it is determined in which address in the memory 20 the control data is stored according to the type of command to be executed using the control signal 005, and the start address of the control data is set via the data bus 001. Next, the control circuit 30 is again instructed to write data into each register using the control signal 005. The control circuit 30 outputs the address of the memory 20 where the control data is stored to the counter address 004, and the register selection signal 008 determines which register the data will be written to, and the clock control signal 007 is used to control the clock. circuit 4
0, synchronized with register write clock 009,
Data is written to register A50 and register B60 via data bus 001 from memory 20 in which control data is stored.

[0013]

As described above, the present invention provides an information processing device having a processor, which includes a processor, a plurality of registers writable by the processor, and a memory that stores data to be written to each register for each control pattern. , a control circuit that controls memory addresses, and a clock control circuit that instructs each register to write data.
For the processor, memory, each register and control circuit,
Control signals from the commonly connected data bus and processor to the control circuit, register selection signals from the control circuit to each register, clock control signals to the clock control circuit, and register write clocks from the clock control circuit to each register. This has the effect that the processor can efficiently write the same data to a plurality of registers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

10 Processor 20 Memory 30 Control circuit 40 Clock control circuit 50 Register A 60 Register B 001 Data bus 002 Memory write clock 003,006 Address 004 Counter address 005 Control signal 007 Clock control signal 008 Register selection signal

Claims (1)

[Claims] 1. A register data writing method for an information processing device having a processor, comprising: a plurality of registers writable by the processor; a memory storing data to be written in each register for each control pattern; A control circuit that controls addresses and a clock control circuit that instructs data writing to each of the registers are provided, and a data bus that is commonly connected to the processor, the memory, each of the registers, and the control circuit is provided. , comprising a control signal from the processor to the control circuit, a register selection signal from the control circuit to each register and a clock control signal to a clock control circuit, and a register write clock from the clock control circuit to each register, A register data writing method for an information processing device, characterized in that the same data is simultaneously written to the plurality of registers according to instructions from a processor.