JPS61122771A - Multi-microprocessor system - Google Patents

Abstract

PURPOSE:To attain parallel operation of microprocessors at the reading of common memories by forming a common memory in each microprocessor. CONSTITUTION:The microprocessors (MPs) 1, 2 include common memories 3, 4 respectively. When the MP 1 is to execute a writing request in the common memory, information on a local bus signal line 102 is controlled by a common memory control device 20 and a waiting signal is sent to the MP 1. Then, a signal on a control signal line 110 is started to open a base gate circuit 12, a signal line 102 of the MP 1 is connected to a write-only bus signal line 105 and bus selecting circuits 10, 11 are switched to the signal line 105 to connect main storages 3, 4 to the signal line 102 of the MP 1. Then, a write command is sent to write data in all the common memories simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the organization of shared memory in multi-microprocessor systems.

(Prior Art) Conventionally, in order to improve system performance, a multi-microprocessor system in which a plurality of microprocessors operate in parallel has been employed.

In such systems, an inter-processor communication method using a channel or an inter-processor communication method using a single shared memory is used for communication between microprocessors.

(Problems to be Solved by the Invention) However, when a large amount of information is transmitted using the conventional communication method using a channel, there is a drawback that the speed becomes slow and the performance of the system deteriorates.

Furthermore, in the interprocessor communication method using a single shared memory as an intermediary, when one microprocessor uses the shared memory, other microprocessors are forced to wait before using it, which reduces system performance.

The purpose of the present invention is to focus on the fact that when shared memory is used in a multi-microprocessor system, data is overwhelmingly read and used, and by preparing a shared memory for each processor and reading it out. When used in a system, each microprocessor can operate in parallel, and when writing data to a shared memory, data is written to all shared memories at the same time, thereby eliminating the above disadvantages by ensuring data consistency in the shared memories. An object of the present invention is to provide a multi-microprocessor system that speeds up communication between processors via a shared memory.

(Means for Solving the Problems) A multi-microprocessor system according to the present invention includes a plurality of microprocessors, a plurality of main memories, a plurality of bus selection circuits, a plurality of bus gate circuits, and a shared memory control device. It has been prepared and configured.

For a plurality of microprocessors, a part of the addressable area can be commonly designated as a shared memory header.

The plurality of main memories are provided with a shared memory area.

The plurality of bus selection circuits are for selectively switching between a write-only bus signal line of the shared memory or a local bus signal line specific to the plurality of microprocessors, and sending the signal to the plurality of main memories.

The plurality of bus gate circuits are for selectively sending signals on the local bus signal lines to write-only bus signal lines.

A shared memory control device is for controlling the queuing of multiple microprocessors, multiple main memories, and multiple bus selection circuits.

In the present invention, when at least one of the plurality of microprocessors performs an embedding operation in the shared memory area with the above configuration, the shared memory control device operates on the local bus (M
Shared memo I by address on Jill and 1-include request
J l) By recognizing that it is a busy request and opening the bus gate circuit after confirming the completion of the bus cycle currently being executed by all of the multiple microprocessors,
Sends the local bus signal line of the microprocessor that sent the shared memory write request to the write-only bus line,
It is configured so that one of the write-only bus signal lines is selected by one of the plurality of bus selection circuits and one of the plurality of main memories is connected to simultaneously perform one write to all the shared memories of the microprocessor. be.

(Implementation row) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention using two microprocessors.

In Figure 81, 1.2 is a microprocessor, 4 is a main memory including a shared memory, 10.11 is a bus selection circuit, 12.13 is a bus gate circuit, and 20. is a shared memory system a
It is a device. 100 and 101 are control signals consisting of multiple lines for controlling memory read/write and for making the microprocessor wait for execution.
02゜103 are local bus signal lines, and 1
05 is a write-only bus communication line, and 110 is a control signal line for controlling the bus selection circuit and the bus gate circuit.

FIG. 2 is a time chart explaining the operation of the multi-microprocessor system shown in the tPL1 diagram. In FIG. 2, 201 is the system clock, 202 is the write command signal on the control line 100, and 203 is the control line A line 100.
, 101; 204 is a decision signal on control signal line 100.101 for determining the bus cycle being executed;
205 is a control signal line 10 that confirms the end of the bus cycle.
0° 101 is the waiting signal, 206 is the starting signal on the communication station 1W110, 207 is the control a-ji! line 100.101
This is the write command signal above. The broken line portion of the waiting signal 205 is a judgment signal on the signal 204 and indicates suppression of output due to the presence of a bus cycle.

In normal operation in FIG. 1, local bus signal lines 102 and 105 are connected to bus selection circuits 10 and 11, respectively.
The output of the bus selection circuit 10゜11 is selected by the main memory 4.
The two microprocessors 1 and 2 execute specific processing in parallel.

In this state, when microprocessor 1 executes a write request to the shared memory, local bus signal #10
2 is loaded with an address specifying the shared memory area, and a control signal fj! 100 Tsuge write command signal is loaded. (See 202 in FIG. 2) Therefore, the shared memory control device 20 determines that the above information is a write request to the shared memory, and sends a waiting signal to the microprocessor 1 (see 202 in FIG. 2).
06). Also, it is determined by the control signal line 101 whether or not there is a 6th cycle (see 204 in the t#2 diagram) currently being executed for the microprocessor 2, and it is determined whether there is a bus cycle currently being executed. In this case, a waiting signal is sent after confirming the completion (see 205 in Figure 2 of Hayabusa). Next, activate the signal on the control aI signal line 110 to open the bus gate circuit 12, connect the local bus signal line 102 of the microprocessor 1 to the write-only bus signal line 105, and select the bus selection circuits 10 and 11. is switched to the write-only bus signal line 105 and connected to the main memories 3, 4 and the local bus signal line 102 of the microprocessor 1 (see 206 in FIG. 2). Next, a write command is sent to execute writing to all shared memories simultaneously (see 207 in FIG. 2).

When writing is finished, the sending of the waiting signal is stopped,
By switching the bus selection circuit 10, the local bus signal line 102
and the main memory 3 and return to normal operation.

(Effects of the Invention) As explained above, the present invention enables parallel operation of the microprocessors when reading the shared memory by providing a shared memory for each microprocessor, improves system performance, and further improves the performance of each shared memory. By writing to the memory simultaneously, one microprocessor can notify multiple other microprocessors at the same time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multi-microprocessor system according to the present invention. FIG. 2 is a waveform diagram showing waveforms at various parts in FIG. 1. 1.2・11@Microprocessor 3.4...Main memory 10.11...Bus selection circuit 12.16...Bus gate circuit 20...Shared memory control device

Claims (1)

[Claims] a plurality of microprocessors that can commonly define a part of the addressable area as a shared memory area; a plurality of main memories each having the shared memory area; and a write-only bus signal line for the shared memory; Alternatively, a plurality of bus selection circuits for selectively switching local bus signal lines specific to the plurality of microprocessors and sending the signals to the plurality of main memories, and selectively writing the signals on the local bus signal lines. comprising a plurality of bus gate circuits for sending data to a dedicated bus signal line, a shared memory control device for controlling the queuing of the plurality of microprocessors, the plurality of main memories, and the plurality of bus selection circuits; When at least one of the plurality of microprocessors performs a write operation in the shared memory area, the shared memory control device recognizes the address on the local bus signal line and the write request as a shared memory write request, and After confirming the completion of the bus cycle currently being executed by all of the plurality of microprocessors, the bus gate circuit is opened to connect the local bus signal line of the microprocessor that sent the shared memory write request to the write-only bus signal. A corresponding one of the plurality of bus selection circuits selects the write-only bus signal line and connects the corresponding one of the plurality of main memories to all the shared memories of the microprocessor. A multi-microprocessor system characterized in that it is configured to simultaneously write to.