JPS5821737B2 - Memory access processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access processing method, and is particularly applicable to a data processing system in which a central processing unit and a storage device are linked by a common bus, such as a data processing system including a microprocessor. When accessing, the central texturing device sets write data to the write data register on the storage device, so that the central texturing device operates with a shortened CPU cycle, and the texturing speed of the entire system is improved. This paper relates to a memory access processing method.

Conventionally, in data processing systems, a central texturing device executes processing in synchronization with a predetermined clock.

That is, for example, processing is performed by dividing one CPU cycle into a first clock φ1 period and a second clock φ2 period.

In read access and write access to the storage device, respectively, read data is surely received or write data is delivered at the end of the CPU cycle.

However, as will be described later with reference to FIG. 1, during read access, the storage device may output read data at the end of the CPU cycle, and the central α-capacity device may output read data until the end of the CPU cycle. The central processing unit must wait to receive read data, but if it is possible for the central processing unit to reliably transfer even the write data during write access, the two units will wait until the end of the CPU cycle specified above. do not have.

In consideration of the above points, the present invention aims to improve the processing speed of the entire system by creating a shortened CPU cycle during write access.

Therefore, the memory access processing method of the present invention is a data processing system in which a central processing unit performs read access and write access to a storage device configured with a plurality of independently accessible storage units to proceed with processing. , the light emitted by the central processing unit
A write data register that holds data so that it is received and completed by the end of the current CPU cycle period, and a write instruction signal that writes the contents of the write data register at the beginning of the next CPU cycle. The storage device includes a write instruction signal generation unit that generates a write instruction signal and a clock control circuit that controls a clock generation circuit, and the central processing unit operates with a clock corresponding to one CPU cycle shortened at the time of write access. After setting the write data in the write data register, write to the storage device.
The write instruction signal generating section is configured to be separated from the access operation, and the write instruction signal generating section instructs the storage unit in which the contents of the write data register set by the end of one CPU cycle period are to be set, and generates the write instruction signal. (ii) a reduced CPU cycle in response to a write access from the central processing unit; and (ii) a normal mode in response to a read access from the central processing unit. lCP of
A clock generating circuit is configured to supply the central processing unit with clocks corresponding to the U cycle and G11) an extended 1 CPU cycle when an access to the same storage unit occurs following the write access. It is characterized by control.

This will be explained below with reference to the drawings.

FIG. 1 is an explanatory diagram illustrating the problems that are the premise of the present invention,
FIG. 2 is an explanatory diagram illustrating memory access processing according to an embodiment of the present invention, and FIG. 3 shows the configuration of an embodiment of the present invention.

Conventionally, in data processing systems, processing is carried out by dividing the CPU cycle period into a first clock φ1 period and a second clock φ2 period, as shown in FIG.

When the central texture device performs read access or write access to the storage device, it is performed as follows.

That is, (1) at the time of read access, the central processing unit determines the time required for the storage device to output the read data by the end of one CPU cycle, and then calculates the data as shown in the figure. The address information is issued with a view to ensuring the setup time TDS.

The central processing unit then receives the read data output from the storage device within the time period TDS.

In other words, in the worst case, the read/write is executed at the end of one CPU cycle.
Receive data.

(2) At the time of write access, the central processing unit performs a write access before the illustrated data hold time TDH in order to ensure that the write data can be written onto the storage device during the data hold time TDH. Emit address information to.

Then, write data is supplied after waiting the illustrated write data delay time TWD from the beginning of one CPU cycle.

Conventionally, as described above, a central processing unit performs read access or write access to a storage device.

However, considering the time of write access, as can be seen from the figure, the storage device performs a write operation to the address location from the time it receives the address information, and the data is stored at least from the time TWD elapses to the time TDH. If the required write data can be guaranteed, the central processing capacity can move away from the write access and perform other processing.

Considering this point, in the case of the present invention, as shown in FIG. 2, the CPU cycle during write access is shortened to the time TDH shown in FIG. 1, so to speak, and the overall speed of the system is improved. I have to.

That is, (3) at the time of write access, the central processing unit:
Address information is issued before the end of the shortened CPU cycle (time T2'), and write data is issued immediately before the above time T2', and the write data WD is stored on the storage device at least at time T2'. Set it on the write data register.

The central processing unit is then isolated from write access processing operations.

(4) The contents of the write data register set above are stored at a desired address location on the storage device by a write instruction signal independently issued by the storage device at the initial stage of the next CPU cycle.

(5) At the time of read access, it operates under a normal CPU cycle, and the central texturer receives the read data at the end of the CPU cycle, just as in the case shown in FIG.

(6) When the memory unit containing the address location stored by the above operation (3×4) is accessed in the next CPU cycle, a certain amount of switching time is required, so The relevant CPU as shown in
It may occur that the cycle has to be extended, such as from time T2' to T3.

In this case, it is determined that there has been a write access and then a read access to the same storage unit, and the CPU cycle is extended.

(7) However, in general, the frequency of successive accesses to the same memory unit is sufficiently low, and as shown in the upper part of Figure 2, the reduction in CPU cycles reduced during write accesses is accumulated sequentially. I'm going to go.

(8) The first clock φ1' is generated in accordance with each of the shortened 1 CPU cycle, normal 1 CPU cycle, and extended 1 CPU cycle.

φ1. φ1'' and second clocks φ2', φ2.φ2'' are prepared.

FIG. 3 shows an embodiment of the present invention that performs the above operations.

In the figure, 1 is a central processing unit, 2 is a common bus, 3 is a storage device, 4 is a processor, and 5 is a clock generation circuit. '.

φ2′, or φ1. 6 is a write data register provided in the storage device; 7-1 to 7-4 are storage units that can be accessed independently; and 8 is a An access circuit 9 is an address analysis circuit which checks which storage unit has been accessed and functions as a write instruction signal generating section according to the present invention, and 10 is a 70-trick control circuit.

The clock control circuit 10 normally issues a time width control signal to the clock generation circuit 5 so that the circuit 5 generates ranks φ1 and φ2.

When the central processing unit 1 performs read access,
The central processing unit 1 notifies the clock control circuit 10 that this is a read access.

The read address information is then supplied to the access circuit 8 of the storage device 3 via the common bus 2.

Then, as explained with reference to FIG. 2, the central processing unit receives the read data at the end of clock φ2.

Needless to say, the address analysis circuit 9 remembers which storage unit has been read accessed.

Next, when the central processing unit 1 performs write access, the central processing unit 1 performs write access to the clock control circuit 10.
Notify of access.

As a result, the clock control circuit 10 controls the clock generation circuit 5 to generate clocks φ1' and φ2'.

In response, the central processing unit 1 sends write address information via the common bus 2 to the
In the latter half of the cycle, that is, near the end of clock φ2', write data is sent and the write data is set in write data register 6.

The central processing unit can then end the write access and begin the next process.

On the other hand, in the storage device 3, as explained with reference to FIG. 2, an access operation to a desired address position is started based on the write address information, and
At the beginning of the PU cycle, the address analysis circuit 9 gives a write instruction signal "W instruction" to a desired storage unit, for example, the unit 7-1.

This allows the above write data to be applied to the storage unit.
The contents of register 6 are stored.

At this time, the address analysis circuit 9 stores which storage unit has been write accessed.

Normally, as described above, the clock control circuit 10 outputs data φ1' to the clock generation circuit 5 each time a write access is performed.
and φ2' are instructed to be generated.

However, if there is a write access first and a read access is performed to the same storage unit immediately after, the clock control circuit 10 receives the information from the address analysis circuit 9 and controls the clock generation circuit 5. clocks φ1'' and φ2'' are generated.

As explained above (according to the present invention), focusing on the fact that storage devices are generally interleaved and the same storage unit is rarely accessed consecutively, the central The time required for the texture device to participate in the write access processing can be shortened, and the processing speed of the entire system can be improved.

For example, in the case of a data processing system such as a data processing device including a microprocessor, in which the access time of the storage device is approximately half of the CPU cycle in which the processor operates, the first half of the CPU cycle is actively used. For example, it is allocated to a direct memory access texture period.

However, if the access time of the storage device is slightly longer than half of the CPU cycle, the above allocation may not be possible.

Even in such a case, since the time required for the central processing unit to access the storage device can be reduced as in the present invention, the time the central processing unit occupies the common bus can be shortened, and this time can be reduced. This enables effective use for other data transfers.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating the problems that are the premise of the present invention,
FIG. 2 is an explanatory diagram illustrating memory access processing according to an embodiment of the present invention, and FIG. 3 shows the configuration of an embodiment of the present invention. In the figure, 1 is a central processing unit, 2 is a common bus, 3 is a storage device,
4 is a processor, 5 is a clock generation circuit, and 6 is a write/write circuit.
Data registers, 1-1 to 7-4 are storage units, 9
Reference numeral 10 indicates an address analysis circuit corresponding to the write instruction signal generation section, and 10 indicates a clock control circuit.

Claims (1)

[Scope of Claims] 1. In a data texture system in which a central texture device performs read access and write access to a storage device configured with a plurality of independently accessible storage units to proceed with processing, the central α Write data is stored so that the write data issued by the control device is received and completed by the end of the CPU cycle period of the relevant device.
A register, a write instruction signal generation unit that generates a write instruction signal for writing the contents of the write data register at the initial point of the next CPU cycle, and a clock control circuit that controls the clock generation circuit are installed on the storage device side. Additionally, the central processing unit operates with a clock corresponding to the shortened ICPU cycle during write access to set write data in the write data register, and then performs a write access operation on the storage device. The write instruction signal generating section generates the write instruction signal by instructing a storage unit in which the contents of the write data register set by the end of one CPU cycle period are to be set. and the clock control circuit is configured to provide at least (1) a shortened CPU cycle in response to a write access from the central processing unit, and (ii) a normal mode in response to a read access from the central texture unit. and G11) an extended CPU cycle when an access to the same storage unit occurs following the write access to the central processing unit. A memory access processing blade type that is characterized by controlling. 2. The memory access processing method according to claim 1, wherein the central processing unit is constituted by a microprocessor, and the central texture unit and the storage device are connected by a common bus. .