JPS5222438A - Method of generating timing of memory - Google Patents

Method of generating timing of memory

Info

Publication number
JPS5222438A
JPS5222438A JP50098718A JP9871875A JPS5222438A JP S5222438 A JPS5222438 A JP S5222438A JP 50098718 A JP50098718 A JP 50098718A JP 9871875 A JP9871875 A JP 9871875A JP S5222438 A JPS5222438 A JP S5222438A
Authority
JP
Japan
Prior art keywords
memory
generating timing
starting
overlapping
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50098718A
Other languages
Japanese (ja)
Other versions
JPS5610707B2 (en
Inventor
Yoshio Nakano
Haruyuki Fukuda
Sadao Oba
Noboru Suemori
Toru Tejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP50098718A priority Critical patent/JPS5222438A/en
Publication of JPS5222438A publication Critical patent/JPS5222438A/en
Publication of JPS5610707B2 publication Critical patent/JPS5610707B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make a high speed processing possible by starting the timing chain with the operation cycle of the memory element at a mode which has a timing chain and with which an overlapping possible and by starting the memory chain with a faster operation cycle with the mode with which an overlapping is possible.
COPYRIGHT: (C)1977,JPO&Japio
JP50098718A 1975-08-13 1975-08-13 Method of generating timing of memory Granted JPS5222438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50098718A JPS5222438A (en) 1975-08-13 1975-08-13 Method of generating timing of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50098718A JPS5222438A (en) 1975-08-13 1975-08-13 Method of generating timing of memory

Publications (2)

Publication Number Publication Date
JPS5222438A true JPS5222438A (en) 1977-02-19
JPS5610707B2 JPS5610707B2 (en) 1981-03-10

Family

ID=14227290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50098718A Granted JPS5222438A (en) 1975-08-13 1975-08-13 Method of generating timing of memory

Country Status (1)

Country Link
JP (1) JPS5222438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5457918A (en) * 1977-10-18 1979-05-10 Fujitsu Ltd Memory access processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5457918A (en) * 1977-10-18 1979-05-10 Fujitsu Ltd Memory access processing system
JPS5821737B2 (en) * 1977-10-18 1983-05-02 富士通株式会社 Memory access processing method

Also Published As

Publication number Publication date
JPS5610707B2 (en) 1981-03-10

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