JPS5836373B2 - Access time variable device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an access time variable device that increases the efficiency of a computer (hereinafter referred to as a CPU) and enables an emergency processing program to be executed without delay.

Magnetic drums, magnetic disks, and magnetic tape devices are often used as auxiliary storage devices in computers, but as the cost of magnetic cores decreases, magnetic cores are also used as auxiliary storage devices because of their superior speed. It started to be done.

The operation of this auxiliary storage device requires the CPU to specify ``data read/write'', ``number of transferred words'', ``start address of computer main memory'', and ``start address within auxiliary storage device'' to the auxiliary storage device. The process starts with , and continues until the specified number of words have been transferred.

In this case, the transfer speed is the fixed time (
access time, cycle time, etc.), the cycle time of the computer's main memory, and the priority of the auxiliary storage device connected to the main memory.

Now, the following cases can be considered as tasks performed within the CPU.

(1) When a program existing in the auxiliary storage device is brought to the CPU and executed.

(2) When executing a program that resides in the computer's main memory (resident has a high priority).

Of these, when executing task (1), the purpose of using a magnetic core as an auxiliary storage device is to bring the program to the CPU as quickly as possible.

However, in this case, the operating speed of the magnetic core is fast and the data transfer speed is fast.

In other words, the computer main memory is accessed by the magnetic core, which is the auxiliary storage device, for a considerable period of time.

If there is a request to execute the task (2) above in this state (transferring), the program will not be executed within the requested time (of course, the task (1) may be postponed to some extent),
There is a drawback that inconveniences may occur.

This invention has been made in consideration of the above points, and by controlling the access time of devices that can access the main memory of a computer as necessary, the CPU
It is an object of the present invention to provide an access time variable device that can increase the efficiency of U and make it possible to execute an emergency processing program to be executed by a CPU without delay.

Embodiments of the access time varying device of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment thereof.

In the figure, 1 is the CPU, and 2 is the main memory of the CPUI.

The CPU 1 is connected to a memory bus 3 and an input/output bus 4.

Further, 5 is an input/output control device, which has a main memory access interval storage circuit 6.

This input/output control device 5 is connected to a memory bus 3 and an input/output bus 4.

An auxiliary storage device 7 is connected to the memory bus 3 and input/output bus 4.

The auxiliary storage device 7 includes a main memory access interval storage circuit 8 .

On the other hand, FIG. 2 is a time chart for explaining the operation of the access time variable device of the present invention configured as described above, and FIG. 2A shows a state in which the main memory 2 operates continuously. There is.

Further, FIG. 2B shows a state in which the CPU 1 is constantly using (accessing) the main memory 2, and FIGS. 2C to F show a state in which the CPU 1 and the auxiliary storage device 7 are alternately using the main memory 2. This shows a state in which the CPU 1 uses the main memory 2 more than the current state.

The priority order of the CPU 1 and the auxiliary storage device 7 relative to the main memory 2 indicates that the CPU 1 is low.

Here, to explain in more detail about FIGS. 2C to 2F, FIG. 2C shows a state in which CPU 1 is using main memory 1, and FIG. 2D shows a state in which CPUi requests main memory. It is in a state of being.

2E shows a state in which the auxiliary storage device 7 is using the main memory 2, and FIG. 2F shows a state in which the auxiliary storage device 7 requests the main memory 2.

Next, the operation of the access time variable device of the present invention will be explained using FIGS. 2A to 2F.

Now, there is a request to transfer a large amount of data from the auxiliary storage device 7 to the main memory 2, and at this time, the CPU 1 has no other task to perform urgently, and the maximum speed of the auxiliary storage device 7 (
If a command is issued to send data to main memory 2 at point a (2lIs in the example in Figure 2), and data transfer begins at point a in Figure 2, then the amount of time that CPU 1 can use main memory 2 is is the % before point a in FIG. 2C.

At this time, if there is a request to execute the program in the main memory 2 within 1ms, and for this purpose the CPU 1 must access the main memory 2 700 times,
If this continues, it will take 1.4ms to execute the program.

Therefore, the CPU 1 instructs the auxiliary storage device 7 to change the access interval to the main memory 2, and the main memory access interval from the auxiliary storage device 7 becomes 4 μs (b in Fig. 2E).
point).

As a result, the CPU 1 executes the program within 1 ms and thereafter issues a command to the auxiliary storage device 7 to speed up the access interval, thereby making it possible to execute the emergency processing program to be executed by the CPU 1 without delay.

Here, a command to temporarily stop accessing the main memory 2 may be issued to the auxiliary storage device 7 as an access interval change command to the main memory 2, but it is not possible to slow down the access interval without stopping the access. Needless to say, this increases transfer efficiency.

As described above, according to the present invention, the CPU, which normally has the lowest priority with respect to the main memory, operates as if it had the highest priority only at necessary times.
The processing effect of the CPU can be improved.

In addition to this improved processing effect, data transfer between the main memory and the auxiliary storage device or between the main memory and the input/output control device can be efficiently performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the access time variable device of the present invention, and FIGS. 2A to 2F are time charts for explaining the operation of the access time variable device, respectively. 1...CPU, 2...Main memory, 5.
. . . Input/output control device, 6, 8 . . . Main memory access interval storage circuit, 7 . . . Auxiliary storage device.

Claims (1)

[Claims] 1 A computer that determines the priority of tasks and instructs the input/output device or auxiliary storage device to access the main memory, and a computer that receives instructions from this computer to specify or change the access time to the main memory. An access time variable device comprising main memory access interval setting means provided in the input/output device or auxiliary storage device for determining or changing the access interval to the main memory according to a command.