JP2002288037A - Memory control device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accessing efficiency in switching a bank by moving the access to another bank in a clock cycle where the data is not exchanged in a bank, in a memory control device and a memory control method for controlling SDRAM composed of plural banks. SOLUTION: An inputted request is divided into requests for each of the banks by a request distributing circuit 11, and a command for each bank is generated by command generating circuits 12A, 12B for each bank. During a period when the data is not exchanged in the present bank, a precharge command of the present bank is procrastinated, and the access command of another bank takes priority. Therefore a weight in exchanging the bank is not generated, and the access can be efficiently executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDR used in a main memory of a computer or an image processor.
The present invention relates to a memory control device and method suitable for controlling AM.

[0002]

2. Description of the Related Art In recent years, a main storage memory of a computer,
SDRAM (Sync
hronous Dynamic Random Access Memory) has been widely used. The SDRAM is capable of continuous data transfer synchronized with a clock. When burst transfer is specified, data transfer for the specified number of bytes is performed by one.
It can be performed continuously in clock units. Also, SD
The storage area in the RAM is divided into a plurality of banks. When the banks are divided in this manner, by performing burst transfer by switching for each bank, it is possible to conceal a precharge operation required when accessing different pages, and to improve a transfer rate. .

FIG. 6 is a block diagram showing a configuration of a memory controller of a conventional SDRAM. In FIG.
The memory controller 101 includes a request processing circuit 11
1, the command generation circuit 112, and the command output circuit 1
13 and a data control circuit 114.

[0004] A request for performing processing on a memory is given to a request processing circuit 111. The request processing circuit 111 holds the request and outputs the request to the command generation circuit 112. Command generation circuit 1
12 generates a command for this request. This command comprises a command set of bank active, read / write, and precharge for a certain request. The command generated by the command generation circuit 112 is output from the command output circuit 113 and provided to the SDRAM 102. The data control circuit 114 performs control for reading / writing data from / to the SDRAM 102 in synchronization with a clock.

[0005]

In the SDRAM, each bank is independent, and a command can be issued to each bank independently. In such an SDRAM having a plurality of banks, the data lines are shared by the banks, so that the read / write operation cannot be performed at the same time. In a clock cycle without data access that occurs between
Access to other banks can be performed simultaneously.

Therefore, it is conceivable that another bank is accessed in such a clock cycle without data access to increase the access efficiency when the bank is switched.

That is, in the SDRAM, an active command is sent to a bank, and a read / write command is sent, and then data is read / written. A waiting time is required until a read / write command can be sent after sending an active command, and until data is actually read / written after sending a read / write command. Therefore, if an active command is sent to another bank in a clock cycle in which data is not exchanged in that bank, there is no waiting time when switching to another bank, and data is immediately read / written. it can.

However, in the above-mentioned conventional SDRAM controller, a command set is issued sequentially for each request. Therefore, a command set for another bank cannot be issued until a command set including bank active, read / write, and precharge for one bank is issued. For this reason, it is difficult to access another bank in a clock cycle in which data is not exchanged in that bank to improve access efficiency.

FIG. 7 is a flowchart showing a command issuing algorithm in the conventional memory controller 101 described above. In FIG. 7, from the idling state (step S101), it is determined whether or not there is an access request (step S102). If there is an access request, an active command is issued (step S101).
103). The process waits until a read / write command can be issued (step S105). When the read / write command can be issued, a read / write command is issued (step S106). Until the data reading is completed (step S108), the wait is performed (step S108).
107) Until the burst access ends (step S109), a read / write command issuance (step S106), a wait (step S107), and determination of the end of data reading are performed (step S108).
If it is determined in step S109 that the burst access has been completed, a read / write command is issued in step S106. When the data reading is completed in step S108, a wait is performed (step S1) until precharging becomes possible (step S110).
11) When precharge becomes possible, precharge is executed (step S112).

For example, it is assumed that a read request to bank A of the SDRAM and a read request to bank B occur. In this case, in the conventional memory controller 101,
As shown in FIG. 8, after a command set including bank active, read / write, and precharge is issued to bank A, a command set including bank active, read / write, and precharge is issued to bank B.

FIG. 8 shows a conventional memory controller 101 in which a read request to bank A and a bank B
This is an operation when a request to read data is issued. Note that the CAS latency is “2” and the burst length is “2”.

In FIG. 8, clock cycle "1"
Then, a bank active command for bank A is issued. The clock cycle “2” becomes a wait, and the read command of the bank A is issued in the clock cycle “3”. Clock cycle “4” becomes a wait, and a read command for bank A is issued in clock cycle “5”. Clock cycle “6” becomes a wait, and a precharge command for bank A is issued in clock cycle “7”.

As described above, the command set for the bank B is issued from the cycle after the command set for the bank active, read, and precharge for the bank A is issued.

At clock cycle "8", an active command for bank B is issued. Clock cycle "9" becomes a wait, and clock cycle "10"
Issues an active command to bank B.
A clock cycle “11” becomes a wait, and a precharge command for bank B is issued in clock cycle “12”.

As described above, in the conventional memory controller, after issuing the command set for bank A,
Since the command set for bank B was issued,
It takes 12 clock cycles to perform a read operation on bank A and a read operation on bank B.

Here, a period from issuing the active command of bank A in clock cycle "1" to issuing a read command in clock cycle "3" or clock cycle "5", and clock cycle "7"
, The access to the other bank B can be performed at the same time. During this time, if an active command is given to bank B,
Immediately after reading the data in bank A, the data in bank B can be read.

However, as described above, in the conventional memory controller, a command set consisting of bank active, read / write, and precharge is sequentially applied to each bank. There is a problem that access efficiency cannot be improved by accessing another bank in a clock cycle in which data is not exchanged during issuance of the precharge.

Accordingly, an object of the present invention is to provide a memory control device and method for controlling an SDRAM comprising a plurality of banks, by shifting access to another bank in a clock cycle in which data is not exchanged in that bank, and An object of the present invention is to provide a memory control device and a memory control method capable of improving access efficiency at the time of switching.

[0019]

SUMMARY OF THE INVENTION The present invention is a memory control device for controlling a synchronous memory which comprises a plurality of banks and reads and writes data by using a clock. Request distributing means for distributing each of the banks, a plurality of command generating means for generating a command for each of the plurality of banks based on the request, and a command generated by the plurality of command generating means are selected. A command selection unit for supplying a command to the pattern memory, wherein the command selection unit is configured to prioritize a command of another bank during a period in which no data access of the bank is performed.

The present invention comprises a plurality of banks,
A memory control method for controlling a synchronous memory that reads and writes data by using a clock, wherein an input request is distributed to each of the plurality of banks, and a command for each of the plurality of banks is transmitted based on the request. A memory control method for generating, selecting the generated command, and supplying the selected command to the synchronous memory, wherein the selection is made to prioritize a command of another bank during a period in which there is no data access of the bank. .

The input request is divided into a request for each bank and a command is generated for each bank by a command generation circuit for each bank. Then, during a period in which no data is exchanged in the current bank, the precharge command of the current bank is postponed, and the access command of another bank is given priority. As a result, there is no wait when switching banks, and access is performed efficiently.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a memory controller, and 2 is an SDRAM. SDRAM2
Has two banks A and B as shown in FIG. The memory controller 1 controls the SDRAM 2 including the two banks A and B. When a burst transfer is designated, the SDRAM can perform data transfer for the designated word line in one clock cycle.

In FIG. 1, a memory controller 1 to which the present invention is applied includes a request distribution circuit 11, command generation circuits 12A and 12B, and a command selection circuit 1.
3 and a data control circuit 14.

The request distribution circuit 11 is provided with a request for performing processing on the memory. This request includes a request for bank A and a request for bank B. The request distribution circuit 11 divides the given request into a request for bank A and a request for bank B.
A, and the request for the command B is supplied to the command generation circuit 12B.

The command generation circuit 12A is connected to the SDRAM 2
In response to the request from the bank A of the first bank. The command generation circuit 12B generates a command corresponding to a request from the bank B of the SDRAM 2.

Commands include active, read / write, and precharge. The active command is a command for instructing a word line corresponding to the selected memory cell to apply a predetermined pulse voltage (to activate the word line). The read command is a command for instructing reading of stored data from the potential of the data line of the selected memory cell. The write command is a command for instructing to apply a potential according to data to be written to the data line of the selected memory cell. The precharge command is a command for instructing to set a data line corresponding to a memory cell to be accessed in the SDRAM 2 to a predetermined potential.

The commands from the command generation circuits 12A and 12B are supplied to the command selection circuit 13. The command selection circuit 13 selects a command for the bank A and a command for the bank B so that the SDRAM 2 can be accessed efficiently, and
It is sent to RAM2.

That is, another bank can be accessed in a clock cycle in which no data is exchanged during the period from the issuance of the active command to the read / write period and the period of issuance of the precharge command. Therefore, for example, during access to the bank A, an active command among commands to the bank B is preferentially issued in a clock cycle in which no data is exchanged, and a precharge command is postponed. In this way, when access is transferred from bank A to bank B, read / write of bank B can be performed immediately, and efficient access can be performed.

As described above, the command selection circuit 13 gives priority to the issuance of an active command if another bank issues an active command in a clock cycle in which data is not exchanged in the current bank. Thus, access when a bank is switched can be performed efficiently.

The data control circuit 14 controls reading and writing of data from the SDRAM 2 in synchronization with a clock.

As described above, in the embodiment of the present invention,
The request distribution circuit 11 allows the memory controller 1
Are divided into a request for bank A and a request for bank B, and the command generation circuits 12A and 12B generate a command for each bank. In the clock cycle in which data is not exchanged in the current bank, if an active command is issued in another bank, the command selection circuit 13 gives priority to the SDRAM 2 so that the SDRAM 2 is accessed efficiently. ,
The precharge command is postponed.

FIG. 3 shows an example of a command selection algorithm of the command selection circuit 13. In FIG. 3, the command of the currently accessed bank is executed (step S1). Then, it is determined whether there is a next command (step S2). If there is a next command, it is determined whether or not the next command is a precharge command (step S3). If not, the process returns to step S1 and the command of the current bank is continuously executed.

If it is determined in step S3 that the command is a precharge command, the precharge command is postponed, so that the process moves to the next bank (step S4), returns to step S1, and executes the command of the next bank. .

In step S2, if there is no next command, it is determined whether there is an active command of another bank (step S5). If there is an active command of another bank, the active command of another bank is issued with priority (step S6), and the process returns to step S2.

In step S5, if there is no active command of another bank, it is determined whether or not there is a precharge command of another bank (step S7). If there is a precharge command for another bank, a precharge command for the accessed bank is issued (step S
8) Return to step S2.

In step S7, if there is no precharge command for another bank, no command is issued (step S9), and the process returns to step S2.

For example, in the case where the bank A and the bank B are accessed, assuming that the bank A is currently accessed, a command for the bank A is first output (step S1). Here, next, it is determined which command should be output. First, it is determined whether there is a next valid command for the current bank A (step S2). If there is a valid command, it is determined whether the next is a precharge command (step S2). Step S
3) If the next is a command other than the precharge command, the command is issued. If the next is the precharge command, the access is moved to the next bank waiting for the access request (step S4). .

If there is no next command in bank A,
If there is a bank issuing an active command request (step S5), this is issued (step S6).
If there is no bank issuing an active command request, it is determined whether there is a bank waiting for precharge (step S7). If there is a bank waiting for precharge, a precharge is issued (step S8). If there is no bank waiting for precharge, no command is issued in the next clock (step S9), and the process returns to step S2 to proceed to the determination in the next clock. Such processing is repeatedly performed.

FIG. 4 shows a memory controller 1 to which the present invention is applied.
This is an operation when a request to read data is issued. Note that the CAS latency is “2” and the burst length is “2”.

In FIG. 4, clock cycle "1"
Then, a bank active command for bank A is issued. The clock cycle “2” becomes a wait, and the read command of the bank A is issued in the clock cycle “3”.

In clock cycle "4", since an active command for bank B is issued, the active command for bank B is given priority.

At clock cycle "5", a read command for bank A is issued. The clock cycle “6” becomes a wait.

At clock cycle "7", a precharge command for bank A should be issued, which is postponed, access is transferred to bank B, and a read command for bank B is issued.

At clock cycle "8", a precharge command for bank A is issued, and at clock cycle "9", a precharge command for bank B is issued.

Conventionally, active, read / write,
While the precharge command set is sequentially transmitted to the bank, in the embodiment of the present invention, as described above, during the period when data is not exchanged in the current bank, the data is transmitted to another bank. If an active command is issued, it is given priority, and the precharge command is postponed.

The data access timing when using the memory controller to which the present invention shown in FIG. 4 is applied is compared with the data access timing when using the conventional memory controller shown in FIG. As can be seen, when the command set of active, read / write, and precharge is sequentially sent to the bank as in the related art, it takes 12 clock cycles for the process of reading from bank A and reading from bank B. On the other hand, in the embodiment of the present invention, processing can be performed in nine clock cycles. As described above, according to the embodiment of the present invention, it is possible to reduce the time by three clocks.

In the above example, the number of banks of the SDRAM 2 is two. However, the present invention can be similarly applied to a case where the number of banks is plural.

FIG. 5 shows an example in which the number of banks of the SDRAM 2 is four. If the number of banks is 4,
Command generation circuits 12A and 12A corresponding to each bank
B, 12C and 12D are provided. In the request distribution circuit 11, requests are distributed corresponding to the four banks, and the command generation circuits 12A, 12B, 12C, 12
D, a command for each bank is generated. Then, the commands are distributed by the command selection circuit 13 so that the SDRAM 2 is accessed efficiently. At this time, as in the case of two banks, the precharge command among the commands for that bank may be postponed, and the active command among the commands for other banks may be issued earlier. Is
This is the same as the processing of FIG. 3 described above.

[0049]

According to the present invention, an input request is divided into a request for each bank, and a command generation circuit for each bank generates a command for each bank. Then, during a period in which no data is exchanged in the current bank, the precharge command of the current bank is postponed, and the access command of another bank is given priority.
As a result, there is no wait when switching banks, and access is performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram used for describing an SDRAM.

FIG. 3 is a flowchart used for describing one embodiment of the present invention.

FIG. 4 is a timing chart used for describing one embodiment of the present invention.

FIG. 5 is a block diagram of another embodiment of the present invention.

FIG. 6 is a block diagram of an example of a conventional memory controller.

FIG. 7 is a flowchart used to describe an example of a conventional memory controller.

FIG. 8 is a timing chart used to describe an example of a conventional memory controller.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory controller, 11 ... Request distribution circuit, 12A, 12B, 12C ... Command generation circuit, 13 ... Command selection circuit

Claims (8)

[Claims] 1. A memory control device comprising a plurality of banks for controlling a synchronous memory which reads and writes data using a clock, wherein the request distribution distributes an input request to each of the plurality of banks. Means, a plurality of command generation means for generating commands for each of the plurality of banks based on the request, and a command selection means for selecting a command generated by the plurality of command generation means and supplying the command to the synchronous memory A memory control device, wherein the command selecting means gives priority to a command of another bank during a period when there is no data access of the bank. 2. The memory control device according to claim 1, wherein said command selection means prioritizes an active command of another bank during a period when there is no data access of a bank. 3. The memory control device according to claim 1, wherein said command selection means postpones a precharge command. 4. The memory control device according to claim 1, wherein said command selection means prioritizes an active command of another bank and pre-charges a precharge command during a period when there is no data access of a bank. 5. A memory control method for controlling a synchronous memory which is composed of a plurality of banks and reads and writes data using a clock, wherein an input request is distributed to each of the plurality of banks. Generating a command for each of the plurality of banks based on a request; selecting the generated command; and supplying the selected command to the synchronous memory; A memory control method that gives priority to commands. 6. The memory control method according to claim 5, wherein said selection gives priority to an active command of another bank during a period when there is no data access of a bank. 7. The memory control method according to claim 5, wherein the selection is made to postpone a precharge command. 8. The memory control method according to claim 5, wherein said command selection means prioritizes an active command of another bank and pre-charges a precharge command during a period when there is no data access of a bank.