JP2000011645A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify a plurality of rows in the same memory array bank by a single external row address regarding a semiconductor storage suited for speeding up access to a memory cell. SOLUTION: A semiconductor storage for enabling access to a corresponding memory cell by inputting row and column addresses from outside is provided. The external row address is supplied to row address controllers 26 and 28 via row address buffers 12 and 14. The row address controllers 26 and 28 specify a burst length and supply an internal reference row address to burst counters 30 and 32. The burst counters 30 and 32 generate internal reference row addresses whose number is equivalent to the burst length with a received internal reference row address as a starting point in synchronization with a clock signal. A plurality of memory cells are specified by a plurality of generated internal reference row addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device suitable for speeding up access to a memory cell.

[0002]

2. Description of the Related Art FIG. 21 shows a block diagram of a conventional synchronous semiconductor memory device (hereinafter referred to as SDRAM).
The conventional SDRAM shown in FIG. 21 includes a control signal generation circuit 10. Control signal generation circuit 1
To 0, an external address signal is supplied along with a chip select signal CS, a row address (row address) strobe signal RAS, a column address (column address) strobe signal CAS, a write enable signal WE, and the like.

A conventional SDRAM has a plurality of row address buffers 12 and 14 and a column address buffer 16.
It has. External address signals are supplied to these address buffers 12 to 16 as in the control signal generation circuit 10. Control signal generation circuit 10
Generates an activation signal for controlling those address buffers 12-16. The row address buffers 12, 14 and the column address buffer 16 each take in an external address signal at an appropriate timing under the control of the control signal generating circuit 10, and generate an internal reference address.

The internal reference column address generated by the column address buffer 16 is supplied to a column address counter 18. The column address counter 18 generates a predetermined number of internal reference column addresses in synchronization with the clock signal, with the above-mentioned internal reference column address as the leading address. Hereinafter, the predetermined number is referred to as a burst length. Column address counter 1
The internal reference column address generated by 8 is supplied to the selector 20.

[0005] The selector 20 is supplied with the internal reference column address and the external bank address. The conventional SDRAM includes a plurality of memory array banks 22 and 24. The selector 20 supplies a plurality of internal reference column addresses supplied from the column address counter 18 to a memory array bank specified by an external bank address.

In a conventional SDRAM, internal reference row addresses generated by row address buffers 12, 14 are supplied to memory array banks 22, 24, respectively. In the conventional SDRAM, as described above, the row address buffers 12, 14 and the selector 20
By issuing the internal reference row address and the internal reference column address, a memory cell to be accessed is specified.

FIG. 22 is an enlarged view showing the periphery of a memory array bank 22 provided in a conventional SDRAM. Conventional SD
In the RAM, by inputting one row address from the outside, one internal reference row address can be supplied to the memory array bank 22. By inputting one column address from the outside, a plurality of internal reference column addresses can be sequentially supplied to the memory array bank 22. Therefore, according to the conventional SDRAM, as shown in FIG. 22, a plurality of memory cells belonging to the same row can be sequentially accessed for one address input.

In a conventional SDRAM, a memory array bank is divided into two, and the memory cells are accessed by an interleave method of alternately accessing each bank. Further, in the conventional SDRAM, the above C
The S signal, the RAS signal, the CAS signal, and the WE signal form a specific command by the following combinations. The conventional SDRAM reads the command at the rise of the clock signal and executes a desired process.

CS = L, RAS = L, CAS = H, WE
= H: ACT command CS = L, RAS = H, CAS = L, WE = L: WRI
TE command CS = L, RAS = H, CAS = L, WE = H: REA
D command CS = H, RAS = H, CAS = H, WE = H: NOP
command

FIG. 23 is a timing chart for explaining the operation of a conventional SDRAM at the time of data writing. As shown in FIG. 23, in the conventional SDRAM, addresses (bank addresses) of banks to be accessed (bank 1 and bank 2) are sequentially input in synchronization with a clock signal during generation of an ACT command. During the generation of the ACT command, the row (X1 and X1) of the memory to be accessed in each bank is
An address (external row address) designating 2) is sequentially input in synchronization with the clock signal.

When the address input is completed, the NOP command is maintained for a predetermined time (hereinafter referred to as TRCD). To request data writing, N
After the OP command, a WRITE command is issued. When the WRITE command is issued as described above, the bank (bank 1) to be accessed first is selected. When the WRITE command is generated, an address (external start column address) designating a column (Y1) of a memory cell to be accessed first in the bank is input.

When the external start column address is input as described above, the NOP command is maintained thereafter for the elapse of a clock cycle (here, four cycles) corresponding to the burst length. During this time, the column address counter 18 operates in synchronization with the clock signal, and the number of internal reference column addresses Y1 to Y1 + 3 corresponding to the burst length is generated. as a result,
Data is sequentially written to a plurality of memory cells belonging to the X1 row of the bank 1.

When a clock cycle corresponding to the burst length has elapsed, a WRITE command is generated again. Here, a bank to be accessed next (bank 2) is selected, and an external start column address Y2 for the bank is input. Thereafter, internal reference column addresses Y2 to Y2 + 3 corresponding to the burst length are generated, and bank 2
Is sequentially written to a plurality of memory cells belonging to row X2.

FIG. 24 is a timing chart for explaining the operation of the conventional SDRAM when reading data. As shown in FIG. 24, in a conventional SDRAM, when data is read, after an external row address and an external bank address are fetched, a READ command is set, and an external start column address for a bank to be accessed first is set. Y1 is input.

When the external start column address is input as described above, the setting of the NOP command is maintained while the clock cycle (here, four cycles) corresponding to the burst length elapses. During this time, the column address counter 18 operates in synchronization with the clock signal, and the number of internal reference column addresses Y1 to Y1 + 3 corresponding to the burst length is generated. As a result, without having to input the column address from outside,
Data is sequentially read from the memory cells of the burst length belonging to the X1 row of the bank 1.

When a clock cycle corresponding to the burst length has elapsed, a READ command is set again. here,
The bank (bank 2) to be accessed next is selected, and the external start column address Y2 for that bank is selected.
Is entered. Thereafter, the internal reference column addresses Y2 to Y2 + 3 corresponding to the burst length are generated, and
Data is sequentially read from a plurality of memory cells belonging to two rows. As described above, according to the conventional SDRAM, by supplying one external bank address, one external row address, and one external column address to one memory array bank, the memory array bank is provided. It was possible to access a plurality of memory cells belonging to the same row.

[0017]

However, the conventional S
The DRAM can generate only one internal reference row address in response to one external row address input.
Similarly, the conventional SDRAM can generate only one internal reference bank address in response to one external bank address input. For this reason, when trying to access memory cells belonging to a plurality of rows in the same memory array bank, or accessing memory cells belonging to a plurality of memory array banks, an external row address or , It is necessary to input a plurality of external bank addresses.

For this reason, in the conventional SDRAM structure, when the memory capacity is increased, that is, when the number of memory cells to be accessed is increased, the number of external addresses to be input becomes excessive, and high-speed operation is not performed. There is a problem that it becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. A semiconductor memory device capable of designating a plurality of rows in the same memory array bank by a single external row address is provided. The primary purpose is to provide.

A second object of the present invention is to provide a semiconductor memory device capable of designating a plurality of memory array banks with a single external bank address.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor memory device capable of accessing a corresponding memory cell by externally inputting a row address and a column address. And a reference row address generating means for generating a plurality of internal reference row addresses by supplying one row address from the outside.

According to a second aspect of the present invention, in the semiconductor memory device, a row address rule for setting a rule when the reference row address generation means generates the plurality of internal reference row addresses in accordance with an external command. It is characterized by comprising setting means.

A semiconductor memory device according to a third aspect of the present invention is characterized in that it comprises a row address simultaneous specifying means for simultaneously specifying the plurality of internal reference row addresses.

According to a fourth aspect of the present invention, there is provided a semiconductor memory device having reference column address generating means for generating a plurality of internal reference column addresses when one column address is supplied from outside. It is.

According to a fifth aspect of the present invention, in the semiconductor memory device, a column address rule for setting a rule when the reference column address generating means generates the plurality of internal reference column addresses in accordance with an external command. It is characterized by comprising setting means.

A semiconductor memory device according to claim 6, wherein a row address simultaneous specifying means for simultaneously specifying said plurality of internal reference row addresses, and a column address sequential specifying means for sequentially specifying said plurality of internal reference column addresses. And the following.

A semiconductor memory device according to claim 7, wherein said plurality of internal reference row addresses are sequentially specified by a row address sequential specifying means, and said plurality of internal reference column addresses are simultaneously specified by a column address simultaneous specifying means. And the following.

A semiconductor memory device according to claim 8 or 9 of the present invention is a semiconductor memory device which can access a corresponding memory array bank by inputting a bank address from the outside. Reference bank address generating means for generating a plurality of internal reference bank addresses by supplying one bank address is provided.

According to a tenth aspect of the present invention, in the semiconductor memory device, a bank address rule for setting a rule when the reference bank address generating means generates the plurality of internal reference row addresses in accordance with an external command. It is characterized by comprising setting means.

The semiconductor memory device according to claim 11 of the present invention is characterized by comprising a bank address simultaneous specifying means for simultaneously specifying the plurality of internal reference bank addresses.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals, and redundant description will be omitted.

Embodiment 1 FIG. 1 shows a block diagram of a synchronous semiconductor memory device (hereinafter referred to as an SDRAM) according to a first embodiment of the present invention. SDRAM of this embodiment
Includes a control signal generation circuit 10. The control signal generation circuit 10 includes a chip select signal C
S, row address (row address) strobe signal RA
S, column address (column address) strobe signal CA
An address signal is supplied along with S, the write enable signal WE, and the like.

The SDRAM of this embodiment also has a plurality of row address buffers 12, 14 and a column address buffer 16. These address buffers 12 to
Similarly to the control signal generation circuit 10, an external address signal is supplied to the control signal generator 16. The control signal generation circuit 10 is provided with the address buffers 12 to
6 to generate an activation signal. The row address buffers 12, 14 and the column address buffer 16 receive an address signal at an appropriate timing under the control of the control signal generating circuit 10, and generate an internal reference address.

The internal reference column address generated by the column address buffer 16 is supplied to a column address counter 18. The column address counter 18 uses the above-mentioned internal reference column address as a leading address and synchronizes with a clock signal in synchronization with a predetermined burst length (4 in this embodiment).
) Internal reference column addresses. The internal reference column address generated by the column address counter 18 is stored in the selector 2
0 is supplied.

The selector 20 is supplied with the internal reference column address and the external bank address. The SDRAM of the present embodiment includes a plurality of memory array banks 22 and 24. The selector 20 supplies the plurality of internal reference column addresses supplied from the column address counter 18 to the memory array bank specified by the external bank address.

In the SDRAM of this embodiment, the internal reference row addresses generated by the row address buffers 12 and 14 are supplied to row address controllers 26 and 28, respectively. To the row address controllers 26 and 28, burst counters 30 and 32 are connected.

The burst counters 30 and 32 are supplied from the row address buffers 12 and 14 to the row address controller 26.
, Generating a plurality of internal reference row addresses having the internal reference row address supplied as a reference address. To the row address controllers 26 and 28, a rule (hereinafter, referred to as an address generation rule) when the burst counters 30 and 32 generate a plurality of internal reference row addresses is instructed by an external command.

Specifically, the row address controller 2
6 and 28 are instructed on the number of internal reference row addresses to be generated by the burst counters 30 and 32, that is, the burst length related to the row address and the operation rules for determining a plurality of internal reference row addresses. These commands are sent from the row address controllers 26 and 28 to the burst counter 3
0 and 32, and are reflected in the processing when the burst counters 30 and 32 generate the internal reference row address.

The plurality of internal reference row addresses generated by the burst counters 30 and 32 are stored in the row address controller 2.
After being temporarily stored in the memory array banks 6, 28, they are supplied to the memory array banks 22, 24 at an appropriate timing. In the SDRAM of the present embodiment, as described above, a plurality of internal reference row addresses and a plurality of internal reference column addresses are issued from the row address controllers 26 and 28 and the selector 20, respectively, so that the memory cells to be accessed can be determined. Specified.

The memory array banks 22 and 24 have I / O
O registers 34 and 36 are connected. Also, I / O
An output buffer 40 and an input buffer 42 are connected to the registers 34 and 36 via a selector 38.
Further, the output buffer 40 and the input buffer 42 include
The data terminal DQ is connected.

In the SDRAM of this embodiment, the selector 38 is a circuit for selectively conducting one of the I / O registers 34 and 36 to the input / output buffers 40 and 42. According to the above configuration, by switching the state of the selector 38, the storage contents of the memory array banks 22 and 24 can be selectively guided to the data terminal DQ, and the memory array bank can be selectively switched from the data terminal DQ. Data can be supplied to one of the terminals 22, 24.

FIG. 2 is an enlarged view of the periphery of the memory array bank 22 provided in the SDRAM of this embodiment. More specifically, FIG. 2 shows a state realized when the row address controller 26 and the burst counter 30 generate m continuous internal reference row addresses in accordance with a command specifying a burst length or the like.

In the SDRAM of this embodiment, the row address controller 26 stores a plurality of internal reference row addresses, and then supplies the plurality of row addresses to the memory array bank 22 at a predetermined timing. In this case, in the memory array bank 22, each time one internal reference column address is specified, as shown in FIG.
A plurality of adjacent memory cells are simultaneously specified over m rows.

As described above, the memory array bank 2
2, the number of internal reference column addresses corresponding to a predetermined burst length is sequentially supplied to the input of one external column address in synchronization with the clock signal. Therefore, according to the SDRAM of the present embodiment, one external row address,
By inputting one external column address, it is possible to sequentially access m memory cells belonging to a plurality of columns for each clock cycle.

The SDRAM of this embodiment attempts to access memory cells by an interleaving method in which two memory array banks 22 and 24 are alternately accessed. In the SDRAM of this embodiment, when accessing a memory cell, first, an instruction of an address generation rule is issued to the row address controllers 26 and 28. Next, the SDRAM of the present embodiment is
Like the AM, the CS signal, RAS signal, CAS
A desired process is executed in accordance with a command constituted by a combination of a signal and a WE signal, that is, a command described below.

CS = L, RAS = L, CAS = H, WE
= H: ACT command CS = L, RAS = H, CAS = L, WE = L: WRI
TE command CS = L, RAS = H, CAS = L, WE = H: REA
D command CS = H, RAS = H, CAS = H, WE = H: NOP
command

FIG. 3 is a timing chart for explaining the operation of the SDRAM of this embodiment when writing data. When requesting the SDRAM of this embodiment to perform data write processing, the row address controller 2
After issuing an address generation rule to the SDRAM 6, 28, an ACT command is set in the SDRAM as shown in FIG. 3, and the external bank address (1, 2) and the external row address (X1, X2) are synchronized with the clock signal. Supply.

The SDRAM recognizes the order in which the external bank addresses are supplied as the order of the memory bank array to be accessed. Further, the SDRAM recognizes the external row address supplied together with each bank address as an address of a row to be an access starting point in each bank, that is, an external start row address.

The SDRAM is supplied with a NOP command following the above address input. The NOP command is
It is maintained for at least the clock cycle (for example, m cycles) corresponding to the burst length specified by the address generation rule and for at least the cycle corresponding to the predetermined specified time TRCD. During this time, the row address controllers 26 and 28 operate to give the row address controllers 26 and 28 respectively m internal reference row addresses (row addresses for m rows starting from X1 and starting from X2). m row addresses) are stored.

When requesting the SDRAM to write data, following the NOP command, the SDRAM
The WRITE command and the external column address (Y1) are supplied. At this time, the SDRAM supplies the selector 20 with the internal reference bank address (1) corresponding to the memory array bank (bank 1) to be accessed first. At this point, the SDRAM has an external column address (Y
After 1) is taken into the column address buffer 16, it is supplied to the selected memory array bank as an external start column address. Further, at this time, the SDRAM simultaneously supplies the plurality of internal reference row addresses (for X1 to m rows) stored in the row address controllers 26 and 28 to the selected memory array bank.

As a result of execution of the above processing, SDRAM
In the selected memory array bank (bank 1), access is made to m memory cells belonging to the Y1 column and belonging to the m rows starting from X1. SDR
Thereafter, the AM sequentially accesses the m memory cells belonging to the columns Y1 + 1, Y1 + 2, and Y1 + 3 in synchronization with the clock signal during a clock cycle (four cycles) corresponding to a predetermined burst length.

When the above access is completed, next, the SD
The WRITE command and the external column address (Y2) are supplied to the RAM. At this time, the SDRAM selects a memory array bank (bank 2) to be accessed next, and stores an internal reference column address (Y2) and a plurality of internal reference row addresses (X2 to m rows) in the memory array bank. Min) and supply.

As a result of the above processing being executed, the SDRAM
Then, in the selected memory array bank (bank 2), access is made to m memory cells belonging to the Y2 column and belonging to the m rows starting from X2. SDR
The AM then sequentially synchronizes with the clock signal for a clock cycle (four cycles) corresponding to the predetermined burst length,
Access is made to m memory cells belonging to columns Y2 + 1, Y2 + 2, and Y2 + 3.

When a request to read data is made to the SDRAM, data to be stored in the memory cells are sequentially stored in the data terminal in synchronization with the clock signal over a predetermined period starting from the period at which the WRITE command is issued. DQ. According to the above configuration, in each memory array bank, the same data can be simultaneously written into m rows of memory cells at every clock cycle.

As described above, according to the SDRAM of the present embodiment, a single external row address and a single external column address are input to the SDRAM, so that they are arranged over a plurality of rows and a plurality of columns. Data can be efficiently written to a plurality of memory cells. Therefore, according to the SDRAM of the present embodiment, the data write processing can be speeded up.

FIG. 4 is a timing chart for explaining the operation of the SDRAM of this embodiment when reading data. When requesting the SDRAM of this embodiment to perform data read processing, the row address controller 2
After issuing an address generation rule to the SDRAM 6, 28, an ACT command is set in the SDRAM as shown in FIG. 4, and the external bank address (1, 2) and the external row address (X1, X2) are synchronized with the clock signal. Enter

The SDRAM recognizes the order of inputting the external bank addresses as the order of the memory bank array to be accessed. Further, the SDRAM uses the external row address input together with each bank address as an address of a row to be an access starting point in each bank,
That is, it is recognized as an external start row address.

A NOP command is set in the SDRAM following the above address input. The NOP command is maintained for at least the clock cycle (for example, m cycles) specified by the address generation rule and for at least the cycle corresponding to the predetermined specified time TRCD. During this time, the row address controllers 26 and 28 operate and the row address controller 2
6, 28 each have m internal reference row addresses (X1
, And a row address for m rows starting from X2).

When requesting the SDRAM to read data, a READ command and an external column address (Y1) are input to the SDRAM after the NOP command. SDR
At this point, the AM selects the memory array bank (bank 1) to be accessed first, as well as the data write process, and stores
An external column address (Y1) is input, and a plurality of internal reference row addresses (X1 to m rows) are supplied.

When the above processing is executed, in the SDRAM, in the selected memory array bank (bank 1), m memory cells belonging to the Y1 column and belonging to the mth row starting from X1 are transferred to the selected memory array bank (bank 1). Access is achieved. SDRA
Thereafter, during a clock cycle (four cycles) corresponding to a predetermined burst length, M sequentially synchronizes with the clock signal.
Access m memory cells belonging to columns 1 + 1, Y1 + 2, Y1 + 3.

When the above access is completed, the SD
A READ command is set in the RAM, and an external column address (Y2) is input. At this point, the SDRAM selects a memory array bank (bank 2) to be accessed next, inputs an external column address (Y2) to the memory array bank, and outputs a plurality of internal reference row addresses (X2 to m2). Line).

When the above processing is executed, in the SDRAM, in the selected memory array bank (bank 2), m memory cells belonging to the Y2 column and belonging to the mth row starting from X2 are transferred to the selected memory array bank (bank 2). Access is achieved. SDRA
Thereafter, during a clock cycle (four cycles) corresponding to a predetermined burst length, M sequentially synchronizes with the clock signal.
Access m memory cells belonging to columns 2 + 1, Y2 + 2, Y2 + 3.

When a data read request is made to the SDRAM, data output from the accessed memory cell is supplied to data terminal DQ via I / O registers 34 and 36, selector 38 and output buffer 40. Is output to According to the SDRAM of the present embodiment, REA
After the D command is issued, after two clock cycles (CAS latency), the data of the specified memory cell is
Appears at data terminal DQ.

Therefore, according to the SDRAM of the present embodiment, data stored in memory cells for m rows can be simultaneously read from each memory array bank every clock cycle. Thus, the S of the present embodiment is
According to the DRAM, by inputting a single external row address and a single external column address to the SDRAM, data is efficiently read from a plurality of memory cells arranged over a plurality of rows and a plurality of columns. be able to.
Therefore, according to the SDRAM of the present embodiment, the data read processing can be speeded up.

Further, according to the SDRAM of the present embodiment,
By appropriately setting the address generation rules, a combination of a plurality of memory cells accessed simultaneously can be arbitrarily set. Therefore, according to the SDRAM of the present embodiment, the data write and read processing can be speeded up without impairing the degree of freedom of access to the memory cells.

By the way, in the above embodiment, S
Although the DRAM accesses the plurality of memory array banks in an interleaved manner, the present invention is not limited to this, and the access scheme for the plurality of memory array banks may be a sequential manner.

In the above embodiment, the row address controllers 26 and 28 and the burst counter 3
0 and 32 correspond to the "reference row address generating means" of the first aspect. Further, in the above embodiment, the "row address rule setting means" is realized by the row address controllers 26 and 28 transmitting the address generation rules to the burst counters 30 and 32. Further, in the above embodiment, the row address controllers 26 and 28 simultaneously output a plurality of internal reference row addresses, thereby realizing the "row address simultaneous designation means" according to the third aspect.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIGS. In these figures, the same parts as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 5 is a diagram showing an SDRA according to the second embodiment of the present invention.
FIG. 3 shows a block diagram of M. SDRAM of this embodiment
Includes a control signal generation circuit 10. The SDRAM according to the present embodiment has a row address buffer 4
4 and a column address buffer 46. The row address buffer 44 and the column address buffer 46 take in an external address at an appropriate timing under the control of the control signal generating circuit 10 and generate an internal reference address.

The internal reference row address generated by the row address buffer 44 is supplied to a row address controller 48. On the other hand, the internal reference column address generated by the column address buffer 46 is supplied to the column address controller 50. Each of the row address controller 44 and the column address controller 46 has a row burst counter 5
2 and column burst counter 54 are connected.

The row burst controller 52 is supplied from the row address controller 48 with an internal reference row address generated by the row address buffer 44 and an address generation rule (burst length and address calculation rule) input as an external command. You. The row burst counter 52 generates a plurality of internal reference row addresses based on the received internal reference row address according to the received address generation rule.

Similarly, the column burst counter 54 receives data from the column address buffer 50 from the column address controller 50.
6 and an internal reference column address and an address generation rule (burst length and address calculation rule) input as an external command are supplied. Column burst counter 54
Generates a plurality of internal reference column addresses based on the received internal reference column address in accordance with the received address generation rule.

A first row address selector 56 and a first column address selector 58 are connected to the row address controller 48 and the column address controller 50, respectively. The first row address selector 56 and the first column address selector 58 are connected to a second row address selector 60 and a second column address selector 62, respectively.

A plurality of internal reference row addresses generated by row burst counter 52 and column burst counter 5
4, the plurality of internal reference column addresses are temporarily stored in the row address controller 48 or the column address controller 50, respectively, and thereafter, at an appropriate timing, the first row address selector 56 or the first column address selector 58. Supplied to

An external bank address is supplied to the first row address selector 56 and the second column address selector 58 together with the internal reference address. First
The row address selector 56 supplies a plurality of internal reference row addresses to the second row address selector 60 when the external bank address is specified. In this case, the second row address selector 60 enters a standby state for outputting a plurality of internal reference row addresses to the memory array bank specified by the external bank address.

On the other hand, the first column address selector 58 supplies a plurality of internal reference column addresses to the second column address selector 62 when an external bank address is specified. In this case, the second column address selector 62 enters a standby state for outputting a plurality of internal reference column addresses to the memory array bank specified by the external bank address.

A control signal is supplied from a selector 64 to the second row address selector 60 and the second column address selector 62. The selector 64 has a function of selectively conducting the I / O registers 34 and 36 to the output buffer 40 or the input buffer 42. Second row address selector 60 and second column address selector 62
Receives a control signal from the selector 64 and supplies a plurality of internal reference addresses to the memory array bank specified by the external bank address.

In the SDRAM of this embodiment, as described above, the plurality of internal reference row addresses stored in the row address controller 48 and the plurality of internal reference column addresses stored in the column address controller 50 are: First and second row address selectors 5, respectively.
The memory cell to be accessed is specified by being supplied to the memory array bank via the first, second, and sixth or first and second column address selectors 58 and 62.

FIG. 6 is an enlarged view of the periphery of the memory array bank 22 provided in the SDRAM of this embodiment. More specifically, FIG. 6 shows that row address controller 48 and row burst counter 52 generate m consecutive internal reference row addresses in accordance with a command specifying a burst length, etc. The state around the memory array bank 22 realized when the burst counter 54 generates n consecutive internal reference column addresses in accordance with a command designating a burst length or the like is shown.

In the SDRAM of this embodiment, the row address controller 48 stores a plurality of internal reference row addresses, and then supplies the plurality of row addresses to the memory array bank 22 at a predetermined timing. In this case, in the memory array bank 22, as shown in FIG. 2, every time an internal reference column address is specified, a plurality of adjacent memory cells over m rows are simultaneously specified.

Further, in the SDRAM of the present embodiment, as described above, a plurality of internal reference column addresses can be generated according to an address generation rule for one external column address input. The SDRAM of this embodiment sequentially supplies the plurality of internal reference column addresses to the memory array bank 22 in synchronization with a clock signal. Therefore, according to the SDRAM of the present embodiment, by inputting one external row address and one external column address, m memory cells belonging to a plurality of columns are sequentially accessed at each clock cycle. can do.

In the SDRAM of this embodiment, the memory cells are accessed by an interleave method in which two memory array banks 22 and 24 are alternately accessed. In the SDRAM of the present embodiment, when accessing a memory cell, first, an instruction of an address generation rule is issued to the row address controller 48 and the column address controller 50. Next, the SDRAM according to the present embodiment, as in the case of the first embodiment, executes a command (ACT, WR) composed of a combination of the above-described CS signal, RAS signal, CAS signal, and WE signal.
ITE, READ and NOP commands).

FIG. 7 is a timing chart for explaining the operation of the SDRAM of this embodiment when writing data. When requesting the SDRAM of this embodiment to perform data write processing, the row address controller 4
After issuing the address generation rules to the SDRAM 8 and the column address controller 50, as shown in FIG. 7, an ACT command is set in the SDRAM, and the external bank address (1, 2) and the external row address (X1) are synchronized with the clock signal. , X2),
Also, it supplies the external column address (Y1.Y2).

The SDRAM recognizes the order in which the external bank addresses are supplied as the order of the memory bank array to be accessed. In addition, the SDRAM uses the external row address and external column address supplied together with each bank address as the row and column addresses from which access is to be started in each bank, ie, the external start row address and external start column address. recognize.

The SDRAM sets a NOP command following the above address input. The NOP command is not less than any of the periods (m period and n period in the present embodiment) specified for each of the row address and the column address, and has a predetermined specified time TRC.
It is maintained for at least the period corresponding to D. During this time, the row burst counter 52 and the column burst counter 54 operate, and the row address controller 48 and the column address controller 50 respectively provide m internal reference row addresses (row addresses for m rows starting from X1), and,
n internal reference column addresses (column addresses for n rows starting from Y1) are stored.

When requesting the SDRAM to write data, following the NOP command,
Set the WRITE command. At this time, the SDRAM stores the first internal reference bank address (1) corresponding to the memory array bank (bank 1) to be accessed first.
It is supplied to a row address selector 56 and a first column address selector 58. At this time, the selector 64 supplies a control signal to the second row address selector 60 and the second column address selector 62.

As a result, when the above WRITE command is generated, the second row address selector 60 and the second row address selector 60
The column address selector 62 is ready to supply the internal reference address to the selected memory array bank (bank 1). In the SDRAM according to the present embodiment, the row address controller 48 sets all the stored internal reference row addresses (X1 to m
Are output at the same time. On the other hand, after the above state is formed, the column address controller 50 outputs the stored plurality of internal reference row addresses (for Y1 to n rows) one by one in synchronization with the clock signal.

As a result, in the selected memory array bank (bank 1), at the same time when the WRITE command is generated, access to the m memory cells belonging to the Y1 column is attempted, and thereafter, a predetermined clock cycle (n period)
, Y1 + 1 and Y1 in synchronization with the clock signal.
Access to m memory cells belonging to columns 1 + 2 to Y1 + n is sequentially performed.

When the above access is completed, the SD
The WRITE command is set again in the RAM.
At this time, the SDRAM selects a memory array bank (bank 2) to be accessed next, and stores an internal reference column address (Y2) and a plurality of internal reference row addresses (X2 to m rows) in the memory array bank. Min) and supply. Thereafter, the SDRAM synchronizes with the clock signal for a predetermined clock cycle (n cycles), and
The m memory cells belonging to columns 2 + 1, Y2 + 2 to Y2 + n are sequentially accessed.

When a data write request is made to the SDRAM, data to be stored in the memory cell is sequentially synchronized with a clock signal for a predetermined period starting from the cycle at which the WRITE command is issued, for a predetermined cycle. Supplied to According to the above configuration, in each memory array bank, the same data can be simultaneously written into m rows of memory cells at every clock cycle. Incidentally, FIG.
This shows a case where a data pattern repeated for each bit is written.

As described above, according to the SDRAM of the present embodiment, by supplying a single external row address and a single external column address to the SDRAM, a plurality of rows (m) can be provided.
Data can be efficiently written to a plurality of memory cells arranged over a plurality of columns (n). Therefore, according to the SDRAM of the present embodiment, the data write processing can be speeded up.

FIG. 8 is a timing chart for explaining the operation of the SDRAM of this embodiment when reading data. When requesting the SDRAM of this embodiment to read data, after issuing an address generation rule to the row address controller 48 and the column address controller 50, an ACT command is set in the SDRAM as shown in FIG. In synchronization, the external bank address (1, 2), the external row address (X1, X2), and the external column address (Y1, Y2) are input.

The SDRAM recognizes the input order of the external bank addresses as the order of the memory bank array to be accessed. Further, the SDRAM recognizes the external row address and external column address input together with each bank address as an internal reference row and column address to be a starting point of access in each bank.

The SDRAM sets a NOP command following the above address input. The NOP command is longer than the clock period (m period and n period in this embodiment) specified for the row address and the column address, and
It is maintained for a period equal to or longer than the period corresponding to the predetermined specified time TRCD. During this time, the row burst counter 52 and the column burst counter 54 operate, and the row address controller 48 and the column address controller 50 transmit m
Internal reference row addresses (row addresses for m rows starting from X1) and n internal reference column addresses (Y1
Is stored as column addresses for n rows).

When requesting the SDRAM to read data, following the NOP command, the SDRAM
Set the READ command. At this point, the SDRAM selects a memory array bank (bank 1) to be accessed first and stores a plurality of internal reference column addresses (Y1 to n columns) in the memory array bank, as in the case of writing data. ) And a plurality of internal reference row addresses (X1 to m rows).

When the above processing is executed, in the SDRAM, in the selected memory array bank (bank 1), m memory cells belonging to the Y1 column and belonging to the mth row starting from X1 are transferred to the selected memory array bank (bank 1). Access is achieved. SDRA
Thereafter, M is synchronized with the clock signal for a predetermined clock cycle (n cycles), and is Y1 + 1, Y1 + 2, respectively.
The m memory cells belonging to the Y1 + n column are sequentially accessed.

When the above access is completed, the SD
The READ command is set again in the RAM. S
At this time, the DRAM selects a memory array bank (bank 2) to be accessed next, and stores the external column address (Y2) and a plurality of internal reference row addresses (X2 to m rows) in the memory array bank. ) And supply. Thereafter, the SDRAM operates at a predetermined clock cycle (n cycles).
, Y2 + 1 and Y2 in synchronization with the clock signal.
The m memory cells belonging to columns 2 + 2 to Y2 + n are sequentially accessed.

When a data read request is made to the SDRAM, data output from the accessed memory cell is supplied to data terminal DQ via I / O registers 34 and 36, selector 64 and output buffer 40. Is output to According to the SDRAM of the present embodiment, REA
After setting the D command, the data of the specified memory cell appears on the data terminal DQ without waiting for the CAS latency time.

Therefore, according to the SDRAM of the present embodiment, data stored in memory cells of m rows can be simultaneously read from each memory array bank every clock cycle. Thus, the S of the present embodiment is
According to the DRAM, by supplying a single external row address and a single external column address to the SDRAM, a plurality of memory cells arranged over a plurality of rows (m) and a plurality of columns (n) can be used. Thus, data can be read efficiently. Therefore, according to the SDRAM of the present embodiment, the data read processing can be speeded up.

Further, according to the SDRAM of the present embodiment,
By appropriately setting the address generation rules, it is possible to arbitrarily set the number (m) of a plurality of memory cells to be simultaneously accessed and the number of times (n) to sequentially access the memory cell group. Therefore, the SDRAM of the present embodiment
According to this, the data write and read processing can be sped up without impairing the degree of freedom in accessing the memory cells.

In the above embodiment, when accessing a memory cell, m internal reference row addresses are simultaneously output, and n internal reference column addresses are sequentially output every clock cycle. However, the present invention is not limited to this. That is, when attempting to access the memory cell, n internal reference column addresses may be simultaneously output, and m internal reference row addresses may be sequentially output every clock cycle.

In the above embodiment, the SDR
Although the AM accesses the plurality of memory array banks in an interleaved manner, the present invention is not limited to this, and the access scheme for the plurality of memory array banks may be a sequential manner.

In the above embodiment, the row address controller 48 and the row burst counter 52
The row address controller 48 transmits the address generation rule to the row burst counter 52 and corresponds to the "row address rule setting means". means"
Has been realized.

In the above embodiment, column address controller 50 and column burst counter 54
Corresponds to the "reference column address generating means" according to claim 4, and the column address controller 50
By transmitting the address generation rule to the column burst counter 54, the "column address rule setting means" according to claim 5 is realized.

In the above embodiment, the row address controller 48 outputs a plurality of internal reference row addresses at the same time, so that the "row address simultaneous designation means" according to claim 6 is provided to the column address controller 48 by a plurality of means. By sequentially outputting the internal reference column addresses, the "column address sequential designation means" according to claim 6 is realized.

Further, in the above-described embodiment, the row address controller 48 sequentially outputs a plurality of internal reference row addresses, so that the "row address sequential designating means" according to claim 7 is provided to the column address controller 50 by a plurality of means. By simultaneously outputting the internal reference column addresses, the "column address simultaneous specifying means" according to claim 7 is realized.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to FIGS. still,
In these drawings, the same portions as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 9 is a diagram showing an SDRA according to the third embodiment of the present invention.
FIG. 3 shows a block diagram of M. SDRAM of this embodiment
Is characterized in that it has a plurality of memory array banks including the memory array banks 22 and 24 and a bank controller 66 and a burst counter 68 for banks. The bank controller 66 includes:
An external bank address is provided. The bank controller 66 generates an internal reference bank address corresponding to the external bank address and supplies it to the bank burst counter 68.

The bank controller 66 is also supplied with an address generation rule (burst length and address calculation rule) relating to the bank address from outside. The bank address controller 66 supplies the address generation rule to the bank burst counter 68. The bank burst counter 68 generates a plurality of internal reference bank addresses starting from the above-described internal reference bank address in accordance with the address generation rules.

A plurality of internal reference bank addresses generated by the bank burst counter 68 are temporarily stored in the bank controller 66 and then supplied to the selector 20 at an appropriate timing. The selector 20 supplies the internal reference column address generated by the column address counter 18 to all memory array banks specified by the internal reference bank address at an appropriate timing.

In the SDRAM of this embodiment,
A plurality of memory array banks (memory array bank 22,
24 is supplied with an internal reference row address from a corresponding address buffer (including the address buffers 12 and 14) at an appropriate timing. SD of this embodiment
In the RAM, as described above, the internal reference address issued from the row address buffer and the selector 20 is:
A memory cell to be accessed is specified by being supplied to an appropriate memory array bank.

FIG. 10 is an enlarged view of the periphery of a plurality of memory array banks provided in the SDRAM of this embodiment. More specifically, FIG. 10 shows a state realized when the bank controller 66 and the bank burst counter 68 generate L consecutive internal reference bank addresses.

In the SDRAM of the present embodiment, the bank controller 66 stores a plurality of internal reference bank addresses, and then supplies the plurality of bank addresses to a plurality of memory array banks at a predetermined timing. For this reason, according to the SDRAM of this embodiment, as shown in FIG. 2, it is possible to simultaneously access the memory cells belonging to a plurality (L) of memory array banks.

In the SDRAM of this embodiment, when accessing a memory cell, first, an instruction of an address generation rule is issued from the bank controller 66. Next, the SDRAM according to the present embodiment provides the CS signal, the RAS signal, and the C signal as described in the first and second embodiments.
Commands (ACT, WRITE, READ and N) constituted by a combination of the AS signal and the WE signal
(OP command).

FIG. 11 is a timing chart for explaining the operation of the SDRAM of this embodiment at the time of data writing. When requesting the SDRAM of this embodiment to perform data write processing, the bank controller 66
After issuing more address generation rules, as shown in FIG.
An ACT command is set in the SDRAM, and an external bank address (1) and an external row address (X1) are supplied in synchronization with a clock signal.

The SDRAM recognizes the external bank address supplied by the above processing as the bank address of the starting point of the memory array bank to be accessed, that is, the external start bank address. Also, the SDRAM uses the external row address supplied together with the external bank address,
Recognize as the external start row address.

A NOP command is set in the SDRAM following the above address input. The NOP command is maintained for a period (L period in this embodiment) specified for the bank address and for a period corresponding to a predetermined specified time TRCD. During this time, the bank burst counter 68 operates and the bank controller 66 stores L internal reference bank addresses (L bank addresses starting from 1).

When requesting the SDRAM to write data, following the NOP command, the SDRAM
WRITE command is set, and the internal reference column address (Y
Enter 1). At this point, the SDRAM selects L memory array banks (bank 1 to bank L), and supplies an internal reference row address (X1) and an internal reference column address (Y1) to those memory array banks. Supply.

By executing the above processing, SD
In the RAM, a state where the memory cells of the L memory array banks can be accessed is realized. Since then
The internal reference column addresses Y1 to Y1 + 3 for a predetermined burst length (four cycles) are sequentially supplied to the L memory array banks in synchronization with the clock signal. As a result, SDR
In AM, in all of the L memory array banks,
Access to sequentially different memory cells is achieved. When the above access is completed, the WRITE command and the new internal reference column address Y are again sent to the SDRAM.
2 are supplied. Thereafter, the SDRAM performs the same processing again using Y2 as the external start column address.

When a data write request is made to the SDRAM, data to be stored in the memory cell is sequentially synchronized with the clock signal for a predetermined period starting from the cycle at which the WRITE command is issued, for a predetermined cycle. Supplied to According to the above configuration, the same data can be simultaneously written to a plurality of memory array banks for each clock cycle.

As described above, according to the SDRAM of the present embodiment, by supplying a single external bank address to the SDRAM, data can be efficiently written into memory cells of a plurality (L) of bank addresses. It can be performed. Therefore, according to the SDRAM of the present embodiment,
Data writing can be speeded up.

FIG. 12 is a timing chart for explaining the operation of the SDRAM of this embodiment when reading data. When requesting the SDRAM of this embodiment to read data, after issuing an address generation rule to the bank controller 66, as shown in FIG.
An ACT command is set in AM, and an external bank address (1) and an external row address (X1) are input in synchronization with a clock signal.

The SDRAM recognizes the external bank address input by the above processing as the bank address of the starting point of the memory array bank to be accessed, that is, the external start bank address. Also, the SDRAM uses the external row address supplied together with the external bank address,
Recognize as the external start row address.

A NOP command is set in the SDRAM following the above address input. The NOP command is maintained for a period (L period in this embodiment) specified for the bank address and for a period corresponding to a predetermined specified time TRCD. During this time, the bank burst counter 68 operates and the bank controller 66 stores L internal reference bank addresses (L bank addresses starting from 1).

When requesting the SDRAM to read data, following the NOP command, the SDRAM
A READ command is set, and the internal reference column address (Y
Supply 1). At this point, the SDRAM selects L memory array banks (bank 1 to bank L), and supplies an internal reference row address (X1) and an internal reference column address (Y1) to those memory array banks. Supply.

By executing the above processing, SD
In the RAM, a state where the memory cells of the L memory array banks can be accessed is realized. Since then
The internal reference column addresses Y1 to Y1 + 3 for a predetermined burst length (four cycles) are sequentially supplied to the L memory array banks in synchronization with the clock signal.

Next, WRITE is again stored in the SDRAM.
A command is set, and a new internal reference column address Y2 is supplied. Thereafter, the SDRAM performs the same processing again using Y2 as the external start column address. According to the above processing, it becomes possible to simultaneously access different memory cells for each clock cycle for the L memory array banks.

When a data read request is made to the SDRAM, data output from the accessed memory cell is supplied to data terminal DQ via I / O registers 34 and 36, selector 38 and output buffer 40. Is output to According to the SDRAM of the present embodiment, REA
After setting the D command, after two clock cycles (CAS latency), the data of the accessed memory cell becomes
Appears at data terminal DQ.

Therefore, according to the SDRAM of the present embodiment, L data can be sequentially read from the L memory array banks simultaneously for each clock cycle. As described above, according to the SDRAM of the present embodiment, a single external row address, a single external column address, and a single bank address are input to the SDRAM, so that the SDRAM is arranged over a plurality of memory array banks. Data can be efficiently read from a plurality of memory cells to be executed. Therefore, according to the SDRAM of the present embodiment,
Data reading can be speeded up.

In the above embodiment, the combination of memory array banks accessed simultaneously is not changed. However, the present invention is not limited to this, and the combination of memory addresses accessed simultaneously is changed. It is also good to make it. Further, the memory banks to be simultaneously accessed may be divided into, for example, two groups, and the accesses to the memory banks may be executed by an interleave method or a sequential method.

Further, in the above embodiment, a plurality of internal reference bank addresses are generated for a single external bank address, and the plurality of internal reference bank addresses are specified at the same time. However, the present invention is not limited to this, and a plurality of generated internal reference bank addresses may be sequentially specified.

In the above embodiment, the bank controller 66 and the bank burst counter 68 correspond to the "reference bank address generating means". In the above embodiment, the bank controller 66 transmits the address generation rule to the bank burst counter 68, thereby realizing the "bank address rule setting means". Further, in the above embodiment, the bank controller 66 simultaneously outputs a plurality of internal reference bank addresses, thereby realizing the "bank address simultaneous specifying means" according to the eleventh aspect.

Embodiment 4 Next, a fourth embodiment of the present invention will be described with reference to FIGS.
In these figures, FIG. 1 to FIG.
12 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 13 shows an SDR according to the fourth embodiment of the present invention.
FIG. 3 shows a block diagram of an AM. SDRAM of this embodiment
Are the SDRAM of the first embodiment and the SDRAM of the third embodiment.
It has a configuration in which it is combined with a RAM. That is,
The SDRAM of the present embodiment has a row address controller 2
6, 28 and row burst counters 30 and 32, and a bank controller 66 and a burst counter 68 for banks.

FIG. 14 is a conceptual diagram for explaining the function of the SDRAM of the present embodiment. As shown in FIG. 14, according to the SDRAM of the present embodiment, the bank controller 6
6 and the function of the burst counter 68, a plurality of internal reference bank addresses can be generated in response to the input of a single external bank address, and a plurality of memory array cells can be accessed simultaneously by those addresses. According to the SDRAM of the present embodiment, the functions of the row address controller 26 and the burst counter 30 generate a plurality of internal reference row addresses in response to the input of a single external row address, and a plurality of internal reference row addresses over a plurality of rows. The memory cells can be accessed simultaneously.

FIG. 15 is a timing chart for explaining the operation at the time of writing data in the SDRAM of the present embodiment. FIG. 16 shows the SDR of the present embodiment.
4 is a timing chart for explaining an operation at the time of reading data of AM.

As shown in FIGS. 15 and 16, according to the SDRAM of the present embodiment, a single external bank address (1), a single external row address (X1), and
By entering a single external column address, multiple (L
Write or read processing can be simultaneously performed on memory cells of a plurality of memory array banks (m rows). Then, the memory cell group to be subjected to the write or read processing can be changed every clock cycle over a predetermined burst length (four cycles).

As described above, according to the SDRAM of the present embodiment, the write or read processing for a plurality of memory cells can be performed extremely efficiently. Therefore, according to the SDRAM of the present embodiment, the data write processing and the data read processing can be significantly speeded up.

Embodiment 5 FIG. Next, a fifth embodiment of the present invention will be described with reference to FIGS.
In these figures, FIG. 5 to FIG. 8 or FIG.
12 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 17 shows an SDR according to the fifth embodiment of the present invention.
FIG. 3 shows a block diagram of an AM. SDRAM of this embodiment
Has a configuration in which the SDRAM of the second embodiment (see FIG. 5) and the SDRAM of the third embodiment (see FIG. 9) are combined. That is, the SDRAM of this embodiment is
It includes a row address controller 48 and a row burst counter 52, a column address controller 50 and a row burst counter 54, and a bank controller 66 and a bank burst counter 68.

FIG. 18 is a conceptual diagram for explaining the function of the SDRAM of the present embodiment. As shown in FIG. 18, according to the SDRAM of the present embodiment, the bank controller 6
6 and the function of the burst counter 68, a plurality of internal reference bank addresses can be generated in response to the input of a single external bank address, and a plurality of memory array cells can be accessed simultaneously by those addresses.

According to the SDRAM of the present embodiment,
The function of row address controller 48 and row burst counter 52 allows multiple internal reference row addresses to be generated for a single external row address input to simultaneously or sequentially access multiple memory cells across multiple rows. Can be. Further, according to the SDRAM of the present embodiment,
The function of column address controller 50 and column burst counter 54 allows multiple internal reference column addresses to be generated for a single external column address input to simultaneously or sequentially access multiple memory cells across multiple columns. Can be.

FIG. 19 is a timing chart for explaining the operation of the SDRAM of this embodiment at the time of data writing. FIG. 20 shows the SDR of this embodiment.
4 is a timing chart for explaining an operation at the time of reading data of AM.

As shown in FIGS. 19 and 20, according to the SDRAM of this embodiment, a single external bank address (1), a single external row address (X1),
By entering a single external column address (Y1)
Write or read processing can be performed on memory cells in a plurality of rows (m rows) of a plurality of (L) memory array banks simultaneously. Then, the memory cell group to be subjected to the write or read processing can be changed every predetermined clock cycle (n cycles).

According to the SDRAM of the present embodiment,
By inverting the role of the row and column addresses, a single external bank address (1), a single external row address (X1), and a single external column address (Y
By inputting 1), write or read processing can be simultaneously performed on memory cells in a plurality of columns (n columns) of a plurality (L) of memory array banks. Then, the memory cell group to be subjected to the write or read processing is set to a predetermined clock cycle (m cycle).
It can be changed every time.

As described above, according to the SDRAM of the present embodiment, the write or read processing for a plurality of memory cells can be performed extremely efficiently. Therefore, according to the SDRAM of the present embodiment, the data write processing and the data read processing can be significantly speeded up.

[0147]

Since the present invention is configured as described above, it has the following effects. Claim 1
According to the described invention, a plurality of internal reference row addresses can be generated by inputting a single external row address. Therefore, according to the present invention, the number of addresses to be input can be reduced with respect to the number of memory cells to be accessed, and the operation can be speeded up.

According to the second aspect of the present invention, a plurality of internal reference row addresses can be generated according to different rules in response to a single external row address input. Therefore, according to the present invention, it is possible to increase the operation speed without impairing the degree of freedom regarding access to the memory cells.

According to the third aspect of the present invention, it is possible to simultaneously designate a plurality of internal reference row addresses, that is, to simultaneously access a plurality of memory cells corresponding to those addresses. Therefore, according to the present invention, the operation can be effectively speeded up.

According to the present invention, a plurality of internal reference row addresses can be generated by inputting a single external row address, and a plurality of internal reference row addresses can be generated by inputting a single external column address. Can be generated. Therefore, according to the present invention, the number of addresses to be input can be reduced with respect to the number of memory cells to be accessed, and the operation can be speeded up.

According to the fifth aspect of the present invention, a plurality of internal reference column addresses can be generated according to different rules for a single external column address input. Therefore, according to the present invention, it is possible to increase the operation speed without impairing the degree of freedom regarding access to the memory cells.

According to the present invention, a plurality of internal reference row addresses can be simultaneously specified, and a plurality of internal reference column addresses can be sequentially specified. That is, according to the present invention, a plurality of memory cells belonging to the same column can be accessed simultaneously, and the column can be sequentially changed. Therefore, according to the present invention, the operation can be effectively speeded up without greatly impairing the degree of freedom regarding access to the memory cells.

According to the seventh aspect of the present invention, a plurality of internal reference row addresses can be simultaneously specified, and a plurality of internal reference row addresses can be sequentially specified. That is, according to the present invention, it is possible to simultaneously access a plurality of memory cells belonging to the same row and sequentially change the row. Therefore, according to the present invention, the operation can be effectively speeded up without significantly impairing the degree of freedom regarding the access to the memory cell.

According to the eighth or ninth aspect of the present invention, a plurality of internal reference bank addresses can be generated by inputting a single external bank address. Therefore, according to the present invention, the number of addresses to be input can be reduced with respect to the number of memory array banks to be accessed, and the operation can be speeded up.

According to the tenth aspect of the present invention, a plurality of internal reference bank addresses can be generated according to different rules in response to a single external bank address input. Therefore, according to the present invention, the operation can be speeded up without impairing the degree of freedom regarding access to a plurality of memory array banks.

According to the eleventh aspect, it is possible to simultaneously designate a plurality of internal reference bank addresses, that is, to simultaneously access a plurality of memory array banks corresponding to those addresses. Therefore, according to the present invention, the operation can be effectively speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a conceptual diagram for explaining an operation of the semiconductor memory device shown in FIG.

FIG. 3 is a time chart for explaining an operation at the time of data writing of the semiconductor memory device shown in FIG. 1;

FIG. 4 is a time chart for explaining an operation at the time of data reading of the semiconductor memory device shown in FIG. 1;

FIG. 5 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention;

6 is a conceptual diagram for explaining the operation of the semiconductor memory device shown in FIG.

FIG. 7 is a time chart for explaining an operation at the time of data writing of the semiconductor memory device shown in FIG. 5;

8 is a time chart for describing an operation at the time of data reading of the semiconductor memory device shown in FIG. 5;

FIG. 9 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention.

10 is a conceptual diagram for explaining the operation of the semiconductor memory device shown in FIG.

11 is a time chart for describing an operation at the time of data writing of the semiconductor memory device shown in FIG. 9;

12 is a time chart illustrating an operation of the semiconductor memory device shown in FIG. 9 when reading data.

FIG. 13 is a block diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 14 is a conceptual diagram for explaining the operation of the semiconductor memory device shown in FIG.

FIG. 15 is a time chart for explaining an operation at the time of data writing of the semiconductor memory device shown in FIG. 13;

16 is a time chart illustrating an operation of the semiconductor memory device shown in FIG. 13 at the time of reading data.

FIG. 17 is a block diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

18 is a conceptual diagram for explaining the operation of the semiconductor memory device shown in FIG.

19 is a time chart for describing an operation of the semiconductor memory device shown in FIG. 17 at the time of data writing.

20 is a time chart illustrating an operation of the semiconductor memory device shown in FIG. 17 when reading data.

FIG. 21 is a block diagram of a conventional semiconductor memory device.

FIG. 22 is a conceptual diagram for explaining the operation of the semiconductor memory device shown in FIG.

23 is a time chart for describing an operation at the time of data writing of the semiconductor memory device shown in FIG. 21;

24 is a time chart illustrating an operation of the semiconductor memory device shown in FIG. 21 when reading data.

[Explanation of symbols]

10 control signal generation circuit, 12, 14, 4
4 row address buffer, 22, 24 memory array bank, 26, 28; 48 row address controller, 30, 32; 52 row burst counter,
46 column address buffer, 50 column address controller, 54 column burst counter, 66
Bank controller, burst counter for 68 banks.

Claims (11)

[Claims] 1. A semiconductor memory device capable of accessing a corresponding memory cell by externally inputting a row address and a column address, wherein a plurality of external memory cells are supplied by supplying one row address from the outside. A semiconductor memory device comprising a reference row address generating means for generating an internal reference row address. 2. The apparatus according to claim 1, further comprising: a row address rule setting unit configured to set a rule when the reference row address generating unit generates the plurality of internal reference row addresses in accordance with an external command. 2. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 1, further comprising a row address simultaneous designating means for simultaneously designating said plurality of internal reference row addresses. 4. The semiconductor memory device according to claim 1, further comprising a reference column address generating means for generating a plurality of internal reference column addresses when one column address is supplied from outside. 5. The apparatus according to claim 1, further comprising a column address rule setting unit configured to set a rule when the reference column address generation unit generates the plurality of internal reference column addresses in accordance with an external command. 5. The semiconductor memory device according to 4. 6. The apparatus according to claim 1, further comprising: a row address simultaneous designation unit for simultaneously designating the plurality of internal reference row addresses; and a column address sequential designation unit for sequentially designating the plurality of internal reference column addresses. 6. The semiconductor memory device according to 4 or 5. 7. The apparatus according to claim 1, further comprising: a row address sequential designating unit for sequentially designating the plurality of internal reference row addresses; and a column address simultaneous designating unit for simultaneously designating the plurality of internal reference column addresses. 6. The semiconductor memory device according to 4 or 5. 8. A semiconductor memory device capable of accessing a corresponding memory array bank by externally inputting a bank address, wherein a plurality of internal reference signals are supplied by externally supplying one bank address. 8. The semiconductor memory device according to claim 1, further comprising reference bank address generation means for generating a bank address. 9. A semiconductor memory device capable of accessing a corresponding memory array bank by externally inputting a bank address, wherein a plurality of internal reference signals are supplied by externally supplying one bank address. A semiconductor memory device comprising reference bank address generating means for generating a bank address. 10. A bank address rule setting means for setting a rule when the reference bank address generating means generates the plurality of internal reference row addresses in accordance with an external command. 10. The semiconductor memory device according to 8 or 9. 11. The semiconductor memory device according to claim 8, further comprising a bank address simultaneous specifying means for simultaneously specifying said plurality of internal reference bank addresses.